California Micro Devices PACDN002Q, PACDN002S Datasheet

CALIFORNIA MICRO DEVICES

17 CHANNEL ESD PROTECTION ARRAY

PAC DN002

Features

 17-channel ESD protection

 8kV contact discharge ESD protection per

IEC 61000-4-2

 15kV ESD protection (HBM)

Applications

 Parallel printer port protection

 ESD protection for sensitive

electronic equipment

 Drop-in replacement for PDN 002

 Low loading capacitance, 5.5pF typ.

 20-pin SOIC or QSOP package

Product Description

The PAC DN002 is a diode array designed to provide 17 channels of ESD protection for electronic components or

sub-systems. Each channel consists of a pair of diodes which steers the ESD current pulse either to the positive (V

negative (V

) supply. The PAC DN002 will protect against ESD pulses up to 15KV Human Body Model.

N

This device is particularly well-suited to provide additional ESD protection for parallel printer ports. It exhibits low

loading capacitance for all signal lines.

ABSOLUTE MAXIMUM RATINGS

Diode Forward DC Current

(Note 1) 20mA

Storage Temperature -65

°

C to 150°C

SCHEMATIC CONFIGURATION

Operating Temperature Range -20°C to 85°C

DC Voltage at any Channel Input V

Note 1: Only one diode conducting at a time.

-0.5V to VP+0.5V

N

P

) or

retemaraP.niM.pyT.xaM

retemaraP.niM.pyT.xaM

(tnerruCylppuSV

P

(tnerruCylppuSV

P

noitcetorPDSE

noitcetorPDSE

00 stneisnartevitageN

00 stneisnartevitageN

V

V

P

P

Note 2: From I/O pins to VP or VN only. VP bypassed to VN with 0.2 µF ceramic capacitor.

Note 3: Human Body Model per MIL-STD-883, Method 3015, C

Note 4: This parameter is guaranteed by characterization.

V,V21=

V,V21=

,V0=VNIV6=(

,V0=VNIV6=(

N

N

(egatloVylppuSgnitarepOV

V-

)V0.21

P

N

V-

(egatloVylppuSgnitarepOV

V-

N

V-

N

,egatloVdrawroFedoiDI

F

,egatloVdrawroFedoiDI

F

lennahCynataegatloVtupnI

lennahCynataegatloVtupnI

stneisnartevitisoP

stneisnartevitisoP

gnitaRrewoPegakcaP

gnitaRrewoPegakcaP

)V0.21

P

N

=T,V0.21=)C°52Aµ01

=T,V0.21=)C°52Aµ01

(C°52=T,evobadeificeps

(C°52=T,evobadeificeps

C°52=T,tnerruCegakaeLlennahC Aµ1.0±Aµ0.1±

C°52=T,tnerruCegakaeLlennahC Aµ1.0±Aµ0.1±

C°52=T,Am02=V56.0V0.1

C°52=T,Am02=V56.0V0.1

5103dohteM,ledoMydoBnamuH

eeS()3,2etoN

eeS()3,2etoN

5103dohteM,ledoMydoBnamuH

(2-4-0001CEIrepegrahcsiDtcatnoC

(2-4-0001CEIrepegrahcsiDtcatnoC

)4,3,2setoN

)4,3,2setoN

)4etoNeeS

)4etoNeeS

)zHM1@derusaeM(ecnaticapaCtupnIlennahC

)zHM1@derusaeM(ecnaticapaCtupnIlennahC

snoitidnoctsetDSErednuegatloVpmalClennahC

snoitidnoctsetDSErednuegatloVpmalClennahC

)4etoNeeS

)4etoNeeS

Discharge

=100pF, R

Discharge

SNOITACIFICEPSDRADNATS

SNOITACIFICEPSDRADNATS

VK51±

VK51±

VK8±

VK8±

Fp5.5Fp21

Fp5.5Fp21

=1.5KΩ, VP=12V, VN=GND.

V

P

V

P

V

N

V

N

V0.31+

V0.31+

V0.31-

V0.31-

W00.1

W00.1

©1999 California Micro Devices Corp. All rights reserved.

11/99

215 Topaz Street, Milpitas, California 95035 Tel: [phone] Fax: [phone] www.calmicro.com

P/Active and PAC are trademarks of California Micro Devices.

C0270498D

1

CALIFORNIA MICRO DEVICES

)

Input Capacitance vs. Input Voltage

12
11
10

9
8
7
6
5

Input Capacitance (pF

4
3
2

024681012

Input Voltage (V)

PAC DN002

with V

IN

IN

& VN)

P

(VP = 12V, V

Typical variation of C

= 0V, 0.1µF chip capacitor between V

N

NOITAMROFNIGNIREDROTRAPDRADNATS

egakcaPrebmuNtraPgniredrO

sniPelytSgnikraMtraP

02CIOSS200NDCAP
02POSQQ200NDCAP

When placing an order please specify desired shipping: Tubes or Tape & Reel.

Application Information

See also California Micro Devices Application note AP209, Design Considerations for ESD protection.

In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize

parasitic series inductances to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of a positive

ESD pulse applied between an input channel and Chassis Ground. The parasitic series inductance back to the power

supply is represented by L

V

= Forward voltage drop of D1 + L1 x d(I

Z

where I

is the ESD current pulse, and V

esd

. The voltage VZ on the line being protected is:

1

)/dt + V

esd

is the positive supply voltage.

Supply

Supply

An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge

per the IEC 61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1nS. Here d(I

approximated by ∆I

© 1999 California Micro Devices Corp. All rights reserved.

2

215 Topaz Street, Milpitas, California 95035 Tel: [phone] Fax: [phone] www.calmicro.com

/∆t, or 30/(1x10

esd

Figure 1

)/dt can be

-9

). So just 10nH of series inductance (L1) will lead to a 300V increment in VZ!

esd

11/99