Caen V1724 Series, V1724B, V1724LC, V1724E, V1724C Technical Information Manual

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Technical Information Manual

Revision n. 7

6 November 2007

MOD. V1724

8 CHANNEL 14 BIT

100 MS/S DIGITIZER

MANUAL REV.7

NPO:

00103/05:V1724x.MUTx/07

CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling, negligence on behalf of the User, accident or any abnormal conditions or operations.

CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User. It is strongly recommended to read thoroughly the CAEN User's Manual before any kind of operation.

CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice.

Disposal of the Product

The product must never be dumped in the Municipal Waste. Please check your local regulations for disposal of electronics products.

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TABLE OF CONTENTS

1. GENERAL DESCRIPTION.........................................................................................................................8

1.1. OVERVIEW ...............................................................................................................................................8

1.2. BLOCK DIAGRAM .....................................................................................................................................9

2. TECHNICAL SPECIFICATIONS............................................................................................................10

2.1. PACKAGING............................................................................................................................................10

2.2. POWER REQUIREMENTS ..........................................................................................................................10

2.3. FRONT PANEL.........................................................................................................................................11

2.4. EXTERNAL CONNECTORS........................................................................................................................12

2.4.1. ANALOG INPUT connectors.........................................................................................................12

2.4.2. CONTROL connectors...................................................................................................................12

2.4.3. ADC REFERENCE CLOCK connectors .......................................................................................12

2.4.4. Digital I/O connectors...................................................................................................................13

2.4.5. Optical LINK connector ................................................................................................................ 13

2.5. OTHER FRONT PANEL COMPONENTS ....................................................................................................... 13

2.5.1. Displays.........................................................................................................................................13

2.6. INTERNAL COMPONENTS ........................................................................................................................13

2.7. TECHNICAL SPECIFICATIONS TABLE .......................................................................................................15

3. FUNCTIONAL DESCRIPTION................................................................................................................16

3.1. ANALOG INPUT.......................................................................................................................................16

3.1.1. Single ended input .........................................................................................................................16

3.1.2. Differential input ...........................................................................................................................16

3.2. CLOCK DISTRIBUTION ............................................................................................................................17

3.2.1. Direct Drive Mode.........................................................................................................................17

3.2.2. PLL Mode......................................................................................................................................18

3.2.3. Trigger Clock.................................................................................................................................18

3.2.4. Output Clock..................................................................................................................................18

3.2.5. AD9510 programming...................................................................................................................18

3.2.6. PLL programming.........................................................................................................................19

3.2.7. Direct Drive programming............................................................................................................19

3.2.8. Configuration file .......................................................................................................................... 19

3.2.9. Multiboard synchronisation...........................................................................................................20

3.2.10. Internal clock.................................................................................................................................20

3.2.11. External clock and multiboard synchronisation............................................................................20

3.3. ACQUISITION MODES .............................................................................................................................20

3.3.1. Acquisition run/stop.......................................................................................................................20

3.3.2. Gate and Sample mode acquisition ...............................................................................................21

3.3.2.1. Gate mode .................................................................................................................................................21

3.3.3. Sample mode..................................................................................................................................22

3.3.4. Acquisition Triggering: Samples and Events.................................................................................22

3.3.4.1. Custom size events....................................................................................................................................23

3.3.5. Event structure...............................................................................................................................24

3.3.6. Memory FULL management..........................................................................................................25

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3.4. ZERO SUPPRESSION ................................................................................................................................25

3.4.1. Zero Suppression Algorithm..........................................................................................................25

3.4.1.1. Full Suppression based on the integral of the signal..................................................................................25

3.4.1.2. Full Suppression based on the amplitude of the signal.............................................................................. 25

3.4.1.3. Zero Length Encoding ZLE.......................................................................................................................25

3.5. TRIGGER MANAGEMENT.........................................................................................................................30

3.5.1. External trigger.............................................................................................................................30

3.5.2. Software trigger.............................................................................................................................30

3.5.3. Local channel auto-trigger............................................................................................................31

3.5.4. Trigger distribution .......................................................................................................................31

3.6. FRONT PANEL I/OS................................................................................................................................. 31

3.7. ANALOG MONITOR.................................................................................................................................32

3.7.1. Trigger Majority Mode (Monitor Mode = 0).................................................................................32

3.7.2. Test Mode (Monitor Mode = 1).....................................................................................................33

3.7.3. Analog Monitor/Inspection Mode (Monitor Mode = 2) ................................................................33

3.7.3.1. Procedure to enable “Analog Monitor” mode ...........................................................................................34

3.7.3.2. Applications examples .............................................................................................................................. 34

3.7.4. Buffer Occupancy Mode (Monitor Mode = 3)...............................................................................35

3.7.5. Voltage Level Mode (Monitor Mode = 4)......................................................................................35

3.8. TEST PATTERN GENERATOR....................................................................................................................36

3.9. RESET, CLEAR AND DEFAULT CONFIGURATION .....................................................................................36

3.9.1. Global Reset ..................................................................................................................................36

3.9.2. Memory Reset................................................................................................................................36

3.9.3. Timer Reset....................................................................................................................................36

3.10. VMEBUS INTERFACE.........................................................................................................................36

3.10.1. Addressing capabilities..................................................................................................................36

3.10.1.1. Base address..........................................................................................................................................36

3.10.1.2. CR/CSR address ...................................................................................................................................37

3.10.1.3. Address relocation ................................................................................................................................37

3.11. DATA TRANSFER CAPABILITIES ..........................................................................................................38

3.12. EVENTS READOUT ..............................................................................................................................38

3.12.1. Sequential readout.........................................................................................................................38

3.12.1.1. SINGLE D32........................................................................................................................................38

3.12.1.2. BLOCK TRANSFER D32/D64, 2eVME.............................................................................................38

3.12.1.3. CHAINED BLOCK TRANSFER D32/D64......................................................................................... 39

3.12.2. Random readout (to be implemented)............................................................................................39

3.12.3. Event Polling.................................................................................................................................40

3.13. OPTICAL LINK ....................................................................................................................................40

3.13.1. CAENVME_Init.............................................................................................................................41

3.13.2. CAENVME_End............................................................................................................................ 41

3.13.3. CAENVME_ReadCycle .................................................................................................................42

3.13.4. CAENVME_WriteCycle.................................................................................................................42

3.13.5. CAENVME_MultiRead..................................................................................................................42

3.13.6. CAENVME_MultiWrite.................................................................................................................43

3.13.7. CAENVME_BLTReadCycle...........................................................................................................43

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3.13.8. CAENVME_FIFOBLTReadCycle..................................................................................................44

3.13.9. CAENVME_MBLTReadCycle.......................................................................................................44

3.13.10. CAENVME_FIFOMBLTReadCycle ..........................................................................................44

3.13.11. CAENVME_IRQCheck..............................................................................................................45

3.13.12. CAENVME_IRQEnable.............................................................................................................45

3.13.13. CAENVME_IRQDisable............................................................................................................45

3.13.14. CAENVME_IRQWait.................................................................................................................46

4. VME INTERFACE.....................................................................................................................................47

4.1. REGISTERS ADDRESS MAP ......................................................................................................................47

4.2. CONFIGURATION ROM (0XF000-0XF084; R).........................................................................................48

4.3. CHANNEL N ZS_THRES (0X1N24; R/W)................................................................................................49

4.4. CHANNEL N ZS_NSAMP (0X1N28; R/W)...............................................................................................50

4.5. CHANNEL N THRESHOLD (0X1N80; R/W)................................................................................................50

4.6. CHANNEL N OVER/UNDER THRESHOLD (0X1N84; R/W) .........................................................................50

4.7. CHANNEL N STATUS (0X1N88; R)...........................................................................................................50

4.8. CHANNEL N AMC FPGA FIRMWARE (0X1N8C; R) ................................................................................50

4.9. CHANNEL N BUFFER OCCUPANCY (0X1N94; R)......................................................................................51

4.10. CHANNEL N DAC REGISTER (0X1N98; R/W) ......................................................................................51

4.11. CHANNEL N ADC CONFIGURATION (0X1N9C; R/W)...........................................................................51

4.12. CHANNEL CONFIGURATION (0X8000; R/W)........................................................................................51

4.13. CHANNEL CONFIGURATION BIT SET (0X8004; W)..............................................................................52

4.14. CHANNEL CONFIGURATION BIT CLEAR (0X8008; W).........................................................................52

4.15. BUFFER ORGANIZATION (0X800C; R/W)............................................................................................52

4.16. BUFFER FREE (0X8010; R/W)..............................................................................................................52

4.17. CUSTOM SIZE (0X8020; R/W) .............................................................................................................52

4.18. ACQUISITION CONTROL (0X8100; R/W)..............................................................................................53

4.19. ACQUISITION STATUS (0X8104; R).....................................................................................................53

4.20. SOFTWARE TRIGGER (0X8108; W)......................................................................................................54

4.21. TRIGGER SOURCE ENABLE MASK (0X810C; R/W)..............................................................................54

4.22. FRONT PANEL TRIGGER OUT ENABLE MASK (0X8110; R/W) .............................................................54

4.23. POST TRIGGER SETTING (0X8114; R/W) .............................................................................................55

4.24. FRONT PANEL I/O DATA (0X8118; R/W).............................................................................................55

4.25. FRONT PANEL I/O CONTROL (0X811C; R/W)......................................................................................55

4.26. CHANNEL ENABLE MASK (0X8120; R/W)...........................................................................................56

4.27. ROC FPGA FIRMWARE REVISION (0X8124; R)..................................................................................56

4.28. DOWNSAMPLE FACTOR (0X8128; R/W) ..............................................................................................56

4.29. EVENT STORED (0X812C; R)..............................................................................................................56

4.30. SET MONITOR DAC (0X8138; R/W)....................................................................................................57

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4.31. BOARD INFO (0X8140; R)...................................................................................................................57

4.32. MONITOR MODE (0X8144; R/W).........................................................................................................57

4.33. EVENT SIZE (0X814C; R)....................................................................................................................57

4.34. ANALOG MONITOR (0X8150; R/W).....................................................................................................57

4.35. VME CONTROL (0XEF00; R/W) .........................................................................................................58

4.36. VME STATUS (0XEF04; R).................................................................................................................58

4.37. BOARD ID (0XEF08; R/W)..................................................................................................................58

4.38. MCST BASE ADDRESS AND CONTROL (0XEF0C; R/W)......................................................................58

4.39. RELOCATION ADDRESS (0XEF10; R/W)..............................................................................................59

4.40. INTERRUPT STATUS ID (0XEF14; R/W)...............................................................................................59

4.41. INTERRUPT EVENT NUMBER (0XEF18; R/W)......................................................................................59

4.42. BLT EVENT NUMBER (0XEF1C; R/W)................................................................................................59

4.43. SCRATCH (0XEF20; R/W) ...................................................................................................................59

4.44. SOFTWARE RESET (0XEF24; W).........................................................................................................59

4.45. SOFTWARE CLEAR (0XEF28; W) ........................................................................................................59

4.46. FLASH ENABLE (0XEF2C; R/W)..........................................................................................................59

4.47. FLASH DATA (0XEF30; R/W)..............................................................................................................60

5. INSTALLATION........................................................................................................................................61

5.1. POWER ON SEQUENCE ...........................................................................................................................61

5.2. POWER ON STATUS................................................................................................................................61

5.3. FIRMWARE UPGRADE..............................................................................................................................61

5.3.1. V1724 Upgrade files description...................................................................................................62

LIST OF FIGURES

FIG. 1.1: MOD. V1724 BLOCK DIAGRAM .................................................................................................................9

FIG. 2.1: MOD. V1724 FRONT PANEL......................................................................................................................11

FIG. 2.2: AMP CLK IN/OUT CONNECTOR ............................................................................................................12

FIG. 2.3: ROTARY AND DIP SWITCHES LOCATION....................................................................................................14

FIG. 3.1: SINGLE ENDED INPUT DIAGRAM ...............................................................................................................16

FIG. 3.2: DIFFERENTIAL INPUT DI AGRAM ...............................................................................................................16

FIG. 3.3: CLOCK DISTRIBUTION DIAGRAM ..............................................................................................................17

FIG. 3.4: CAENPLLCONFIG MAIN MENU ..............................................................................................................19

FIG. 3.5: DATA STORAGE IN GATE MODE ...............................................................................................................21

FIG. 3.6: DATA STORAGE IN SAMPLE MODE ...........................................................................................................22

FIG. 3.7: TRIGGER OVERLAP ..................................................................................................................................23

FIG. 3.8: ZERO SUPPRESSION EXAMPLE..................................................................................................................26

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FIG. 3.9: EXAMPLE WITH POSITIVE LOGIC AND NON-OVERLAPPING N FIG. 3.10: EXAMPLE WITH NEGATIVE LOGIC AND NON-OVERLAPPING N FIG. 3.11: EXAMPLE WITH POSITIVE LOGIC AND NON OVERLAPPING N FIG. 3.12: EXAMPLE WITH POSITIVE LOGIC AND OVERLAPPING N

LBK

/ N

LBK

..............................................................28

LBK

..................................................27

LFWD

/ N

..............................................27

LFWD

.....................................................................29

FIG. 3.13: BLOCK DIAGRAM OF TRIGGER MANAGEMENT........................................................................................30

FIG. 3.14: LOCAL TRIGGER GENERATION................................................................................................................31

FIG. 3.15: MAJORITY LOGIC (2 CHANNELS OVER THRESHOLD; BIT[6] OF CH. CONFIG. REGISTER =0) ....................33

FIG. 3.16: INSPECTION MODE DIAGRAM.................................................................................................................33

FIG. 3.17: EXAMPLE OF MAGNIFY PARAMETER USE ON SINGLE CHANNEL..............................................................34

FIG. 3.18: EXAMPLE OF MAGNIFY AND OFFSET PARAMETERS USE ON SINGLE CHANNEL .......................................35

FIG. 3.19: A24 ADDRESSING...................................................................................................................................37

FIG. 3.20: A32 ADDRESSING...................................................................................................................................37

FIG. 3.21: CR/CSR ADDRESSING............................................................................................................................37

FIG. 3.22: SOFTWARE RELOCATION OF BASE ADDRESS ...........................................................................................37

FIG. 3.23: EXAMPLE OF BLT READOUT..................................................................................................................39

FIG. 3.24: EXAMPLE OF RANDOM READOUT ...........................................................................................................40

FIG. 3.25: OPTICAL LINK DAISY CHAIN ..................................................................................................................41

LIST OF TABLES

TABLE 1.1: MOD. V1724 VERSIONS .........................................................................................................................8

TABLE 2.1: MODEL V1724 POWER REQUIREMENTS................................................................................................10

TABLE 2.2 : FRONT PANEL LEDS ...........................................................................................................................13

TABLE 2.3 : MOD. V1724 TECHNICAL SPECIFICATIONS ..........................................................................................15

TABLE 3.1: BUFFER ORGANIZATION ......................................................................................................................22

TABLE 3.2 : EVENT ORGANIZATION .......................................................................................................................24

TABLE 3.3 : FRONT PANEL I/OS DEFAULT SETTING ................................................................................................32

TABLE 4.1: ADDRESS MAP FOR THE MODEL V1724...............................................................................................47

TABLE 4.2: ROM ADDRESS MAP FOR THE MODEL V1724.....................................................................................49

TABLE 4.3: OUTPUT BUFFER MEMORY BLOCK DIVISION........................................................................................52

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1. General description

1.1. Overview

The Mod. V1724 is a 1-unit wide VME 6U module housing a 8 Channel 14 bit 100 MS/s Flash ADC Waveform Digitizer with threshold Auto-Trigger capabilities. The board is available with different input range, memory and connector configuration, as summarised by the following table:

Table 1.1: Mod. V1724 versions

Model Input type SRAM Memory Optical link AMC FPGA(*) Form factor

V1724LC Single ended 512 Ksamples / ch No EP1C4 6U-VME64 V1724 Single ended 512 Ksamples / ch Yes EP1C4 6U-VME64 V1724B Single ended 4 Msamples / ch Yes EP1C4 6U-VME64 V1724C Differential 512 Ksamples / ch Yes EP1C4 6U-VME64 V1724D Differential 4 Msamples / ch Yes EP1C4 6U-VME64 V1724E Single ended 4 Msamples / ch Yes EP1C20 6U-VME64 V1724F Differential 4 Msamples / ch Yes EP1C20 6U-VME64 VX1724 Single ended 512 Ksamples / ch Yes EP1C4 6U-VME64X VX1724B Single ended 4 Msamples / ch Yes EP1C4 6U-VME64X VX1724C Differential 512 Ksamples / ch Yes EP1C4 6U-VME64X VX1724D Differential 4 Msamples / ch Yes EP1C4 6U-VME64X VX1724E Single ended 4 Msamples / ch Yes EP1C20 6U-VME64X VX1724F Differential 4 Msamples / ch Yes EP1C20 6U-VME64X

(*) AMC: ADC e Memory controller FPGA. Models available: ALTERA Cyclone EP1C4 (4000 Logic elements)

or ALTERA Cyclone EP1C20 (20000 Logic elements).

Single ended input versions, optionally, are available with 10 Vpp dynamic range (default range: 2.25 Vpp).

The DC offset of the signal can be adjusted channel per channel by means of a programmable 16bit DAC.

The board features a front panel clock/reference In/Out and a PLL for clock synthesis from internal/external references. This allows multi board phase synchronisations to an external clock source or to a V1724 clock master board.

The data stream is continuously written in a circular memory buffer; when the trigger occurs the FPGA writes further N samples for the post trigger and freezes the buffer that then can be read either via VME or via Optical Link; the acquisition can continue without dead-time in a new buffer. Each channel has a SRAM memory, divided in buffers of programmable size. The trigger signal can be provided via the front panel input as well as via the VMEbus, but it can also be generated internally, as soon as a programmable voltage threshold is reached. The individual Auto-Trigger of one channel can be propagated to the other channels and onto the front panel Trigger Output.

The VME interface is VME64X compliant and the data readout can be performed in

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Single Data Transfer (D32), 32/64 bit Block Transfer (BLT/MBLT), 2eVME, 2eSST and 32/64 bit Chained Block Transfer (CBLT). The board houses a daisy chainable Optical Link able to transfer data at 80 MB/s, thus it is possible to connect up to eight V1724 (64 ADC channels) to a single Optical Link Controller (Mod. A2818, see Accessories/Controller).

The V1724 can be controlled and readout through the Optical Link in parallel to the VME interface.

The Mod. V1724LC is also available, a simplified version of the Mod. V1724, without Optical Link and Analog Monitor features.

1.2. Block Diagram

FRONT PANEL

INPUTS

CLK IN

CLK OUT

TRG IN

TRG OUT

S IN

MON DAC

DIGITAL I/Os

OSC

x8 channels

ADC

DAC

MUX

CLOCK

MANAGER

(AD9510)

ROC [FPGA]

- Readout control

- VME interface control

- Optical link control

- Trigger control

- External interface control

AMC [FPGA]

ADC &

MEMORY

CONTROLLER

BUFFERS

VCXO

1GHz

LOCAL BUS

TRIGGERS & SYNC

VME

OPTICAL LINK

Fig. 1.1: Mod. V1724 Block Diagram

The function of each block will be explained in detail in the subsequent sections.

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2. Technical specifications

2.1. Packaging

The module is housed in a 6U-high, 1U-wide VME unit. The board hosts the VME P1, and P2 connectors and fits into both VME/VME64 standard and V430 backplanes. VX1724 versions require VME64X compliant crates.

2.2. Power requirements

The power requirements of the module are as follows:

Table 2.1: Model V1724 power requirements

+5 V 4.50 A

+12 V 0.2 A

-12 V 0.2 A

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2.3. Front Panel

Mod. V560E

Mod. V1724

EXTERNAL

CLOCK IN

INTERNAL

CLOCK OUT

LOCAL

TRIGGER OUT

EXTERNAL

TRIGGER IN

SYNC/SAMPLE

START

ANALOG

MONITOR

OUTPUT

DIGITAL

I/O's

ANALOG

INPUT

SCALER

8 CH 14 BIT

100 MS/

DIGITIZER

Fig. 2.1: Mod. V1724 front panel

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2.4. External connectors

2.4.1. ANALOG INPUT connectors

Single ended version (see options in § 1.1):

Function:

Analog input, single ended, input dynamics: 2.25Vpp Zin=50Ω (on request: 10Vpp Zin=1KΩ)

Mechanical specifications:

MCX connector (CS 85MCX-50-0-16 SUHNER)

Differential version (see options in § 1.1): Function:

Analog input, differential, input dynamics: 2.25Vpp Zin=100Ω or 10Vpp Zin=1KΩ

Mechanical specifications:

Tyco MODU II

N.B.: absolute max analog input voltage = 6Vpp (with Vrail max to +6V or -6V) for any DAC offset value

2.4.2. CONTROL connectors

Function:

• TRG OUT: Local trigger output (NIM/TTL, on Rt = 50Ω)

• TRG IN: External trigger input (NIM/TTL, Zin= 50Ω)

• SYNC/SAMPLE/START: Sample front panel input (NIM/TTL, Zin=50Ω)

• MON/Σ: DAC output 1Vpp on Rt=50Ω (not available on Mod. V1724LC)

Mechanical specifications: 00-type LEMO connectors

2.4.3. ADC REFERENCE CLOCK connectors

GND

CLK-

CLK+

Fig. 2.2: AMP CLK IN/OUT Connector

Function:

CLK IN: External clock/Reference input, AC coupled (diff. LVDS, ECL, PECL, LVPECL, CML), Zdiff= 110

Ω.

Mechanical specifications:

AMP 3-102203-4 connector

Function:

CLOCK OUT: Clock output, DC coupled (diff. LVDS), Zdiff= 110

Ω.

Mechanical specifications:

AMP 3-102203-4 connector

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2.4.4. Digital I/O connectors

Function: N.16 programmable differential LVDS I/O signals, Zdiff_in= 110 Ohm. Four

Indipendent signal group 0÷3, 4÷7, 8÷11, 12÷15, In / Out direction control; see also § 3.6.

Mechanical specifications:

3M-7634-5002- 34 pin Header Connector

2.4.5. Optical LINK connector

Mechanical specifications:

LC type connector; to be used with Multimode 62.5/125µm cable with LC connectors on both sides; not featured on Mod. V1724LC

Electrical specifications:

Optical link for data readout and slow control with transfer rate up to 80MB/s; daisy chainable.

2.5. Other front panel components

2.5.1. Displays

The front panel hosts the following LEDs:

Table 2.2 : Front panel LEDs

Name: Colour: Function: DTACK CLK_IN NIM TTL LINK PLL _LOCK PLL _BYPS

RUN TRG DRDY BUSY OUT_LVDS

green VME read/write access to the board green External clock enabled. green Standard selection for CLK I/O (V1724LC Rev.0), TRG OUT, TRG IN, S IN. green Standard selection for CLK I/O (V1724LC Rev.0), TRG OUT, TRG IN, S IN. green/yellow Network present; Data transfer activity green The PLL is locked to the reference clock green The reference clock drives directly ADC clocks; the PLL circuit is switched

off and the PLL_LOCK LED is turned off. green RUN bit set (see § 4.19) green Trigger accepted green Event/data (depending on acquisition mode) are present in the Output Buffer red All the buffers are full green Signal group OUT direction enabled.

2.6. Internal components

SW2..5 “Base Address [31:16]”: Type: 4 rotary switches

Function: Set the VME base address of the module.

SW1 “CLOCK SOURCE” Type Dip Switch

Function: Select clock source (External or Internal)

JP2 “FW” Type: Jumper.

Function: it allows to select whether the “Standard” or the “Back up” firmware must be loaded at power on;

(default position: STD).

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CLK SOURCE: SW1

BASE ADDRESS [31:16]

ROTARY SWITCHES SW2..5

FW JUMPER: JP2

Fig. 2.3: Rotary and dip switches lo cation

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2.7. Technical specifications table

Table 2.3 : Mod. V1724 technical specifications

Package

Analog Input

Digital Conversion

ADC Sampling Clock generation

CLK_IN

CLK_OUT

Memory Buffer

Trigger

Trigger Time Stamp

1-unit wide VME 6U module

8 channels, single-ended or differential (depending on version);

2.25Vpp (10Vpp Single-ended on request) input range, positive or negative; 40MHz Bandwidth; Programmable DAC for Offset Adjust on each channel (Single-ended versions only).

Resolution: 14 bit Sampling rate: 10 MS/s to 100 MS/s simultaneously on each channel Multi board synchronisation (one board can act as clock master). External Gate Clock capability (NIM / TTL) by S_IN input connector, for burst or single sampling mode.

The V1724 sampling clock generation supports three operating modes:

- PLL mode - internal reference (50 MHz local oscillator)

- PLL mode - external reference on CLK_IN. Frequency: 50MHz 100ppm (Other reference

frequency values are available in 10 ÷ 100MHz range.)

- PLL Bypass mode: External clock on CLK_IN drives directly ADC clocks. External clock

Frequency from 10 to 100MHz.

AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM / TTL is also possible via custom CAEN cable).

DC coupled differential LVDS output clock, locked to ADC sampling clock. Frequency values in 10 ÷ 100MHz range are available.

512K sample/ch or 4M sample/ch (see § 1.1); Multi Event Buffer with independent read and write access. Programmable event size and pre-post trigger. Divisible into 1 ÷ 1024 buffers

Common External TRGIN (NIM or TTL) and VME Command Individual channel autotrigger (time over/under threshold) TRGOUT (NIM or TTL) for the trigger propagation to other V1724 boards

32bit – 10ns (43s range). Sync input for Time Stamp alignment

AMC FPGA

Optical Link

VME interface

Upgrade Software

Analog Monitor

(not available in V1724LC)

LVDS I/O

One Altera Cyclone EP1C4 or EP1C20 per channel

Data readout and slow control with transfer rate up to 80 MB/s, to be used instead of VME bus. Daisy chainable: one A2818 PCI card can control and read eight V1724 boards in a chain (not available on Mod. V1724LC).

VME64X compliant D32, BLT32, MBLT64, CBLT32/64, 2eVME, 2eSST, Multi Cast Cycles Transfer rate: 60MB/s (MBLT64), 100MB/s (2eVME), 160MB/s (2eSST) Sequential and random access to the data of the Multi Event Buffer The Chained readout allows to read one event from all the boards in a VME crate with a BLT access

V1724 firmware can be upgraded via VME

General purpose C Libraries and Demo Programs (CAENScope)

12bit / 100MHz DAC controlled by ROC FPGA, supports five operating modes:

- Waveform Generator: 1 Vpp ramp generator

- Majority: MON/Σ output signal is proportional to the number of ch. under/over threshold (1 step

= 125mV)

- Analog Inspection: data stream from one channel ADC drives directly the DAC input producing

the channel input signal (1 Vpp)

- Buffer Occupancy: MON/Σ output signal is proportional to the Multi Event Buffer Occupancy:

1 buffer ~ 1mV

- Voltage level: MON/Σ output signal is a programmable voltage level

16 general purpose LVDS I/O controlled by the FPGA Busy, Data Ready, Memory full, Individual Trig-Out and other function can be programmed An Input Pattern from the LVDS I/O can be associated to each trigger as an event marker

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3. Functional description

3.1. Analog Input

The module is available either with single ended (on MCX connector) or, on request, differential (on Tyco MODU II 3-pin connector) input channels.

3.1.1. Single ended input

Input dynamic is 2,25Vpp (Zin= 50 Ω). 10Vpp (Zin= 1KΩ) dynamic is available on request. A 16bit DAC allow to add up to ±1.125V (±5V with high-range input) DC offset in order to preserve the full dynamic range also with unipolar positive or negative input signals. The input bandwidth ranges from DC to 40 MHz (with 2nd order linear phase anti-aliasing low pass filter).

Input Dynamic Range: 1 Vpp

Input

MCX

50Ω

OpAmp

−

ADC

DAC

Vref

14 bit

16 bit

FPGA

+2.25

+1.125

-1.125

-2.25

Positive Unipolar

DAC = FSR

Bipolar

DAC = FSR/2

Negative Unipolar

DAC = 0

Fig. 3.1: Single ended input diagram

3.1.2. Differential input

Input dynamics is ±1.125V (Zin= 50 Ω). The input bandwidth ranges from DC to 40 MHz (with 2nd order linear phase anti-aliasing low pass filter).

Differential Mode

Tyco

Input

Modu II

110Ω

Fig. 3.2: Differential input diagram

OpAmp

−

ADC

DAC

Vref

14 bit

FPGA

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3.2. Clock Distribution

Fig. 3.3: Clock distribution diagram

The module clock distribution takes place on two domains: OSC-CLK and REF-CLK; the former is a fixed 50MHz clock provided by an on board oscillator, the latter provides the ADC sampling clock. OSC-CLK handles both VME and Local Bus (communication between motherboard and mezzanine boards; see red traces in the figure above). REF-CLK handles ADC sampling, trigger logic, acquisition logic (samples storage into RAM, buffer freezing on trigger) through a clock chain. Such domain can use either an external (via front panel signal) or an internal (via local oscillator) source (selection is performed via dip switch SW1, see § 2.6); in the latter case OSC-CLK and REF-CLK will be synchronous (the operation mode remains the same anyway). REF-CLK is processed by AD9510 device, which delivers 6 clock out signals; 4 signals are sent to ADCs, one to the trigger logic and one to drive CLK-OUT output (refer to AD9510 data sheet for more details:

http://www.analog.com/UploadedFiles/Data_Sheets/AD9510.pdf

); two operating modes

are foreseen: Direct Drive Mode and PLL Mode

3.2.1. Direct Drive Mode

The aim of this mode is to drive externally the ADCs' Sampling Clock; generally this is necessary when the required sampling frequency is not a VCXO frequency submultiple. The only requirement over the SAMP-CLK is to remain within the ADCs' range.

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3.2.2. PLL Mode

The AD9510 features an internal Phase Detector which allows to couple REF-CLK with VCXO (1 GHz frequency); for this purpose it is necessary that REF-CLK is a submultiple of 1 GHz. AD9510 default setting foresees the board internal clock (50MHz) as clock source of REF-CLK.

This configuration leads to Ndiv = 100, Rdiv = 5, thus obtaining 10MHz at the Phase

Detector input and CLK-INT = 1GHz. The required 100 MHz Sampling Clock is obtained by processing CLK-INT through Sdiv dividers. When an external clock source is used, if it has 50MHz frequency, then AD9510 programming is not necessary, otherwise Ndiv and Rdiv have to be modified in order to achieve PLL lock. A REF-CLK frequency stability better than 100ppm is mandatory.

3.2.3. Trigger Clock

TRG-CLK signal has a frequency equal to ½ of SAMP-CLK; therefore a 2 samples “uncertainty” occurs over the acquisition window.

3.2.4. Output Clock

Front panel Clock Output is User programmable. Odiv and Odel parameters allows to obtain a signal with the desired frequency and phase shift (in order to recover cable line delay) and therefore to synchronise daisy chained boards. CLK-OUT default setting is OFF, it is necessary to enable the AD9510 output buffer to enable it.

3.2.5. AD9510 programming

CAEN has developed a software tool which allows to handle easily the clock parameters: CAENPLLConfig is a software tool which allows the PLL management, whenever the module is controlled through a CAEN VME Controller (see http://www.caen.it/nuclear/function1.php?fun=vmecnt The tool is developed through open source classes wxWidgets v.2.6.3 (see http://www.wxwidgets.org/

) and requires the CAENVMETool API’s to be installed (they can be downloaded at http://www.caen.it/nuclear/lista-sw.php?mod=V1718

SW package for CAEN VME Bridges & Slave Boards).

CAENPLLConfig is available at: http://www.caen.it/nuclear/lista-sw.php?mod=V1724 And must be simply run on the PC connected to the used CAEN VME Controller

The User has to select the board type and base address (in the ADC BOARD field), then the used mode (PLL or Direct Feed/BYPASS in the INPUT field); see figure below:

with the

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Fig. 3.4: CAENPLLConfig Main menu

3.2.6. PLL programming

In PLL mode the User has to enter the divider for input clock frequency (input clock divider field in CAENPLLConfig Main menu); since the VCXO frequency is 1GHz, in

order to use, for example, a 50MHz ExtClk, the divider to be entered is 20.

Then it is necessary to set the parameters for sampling clock and CLK_OUT (enable, divide ratio and phase shift/delay in Output Clock field of CAENPLLConfig Main

menu); the tool refuses wrong settings for such parameters.

3.2.7. Direct Drive programming

In Direct Drive/BYPASS mode, the User can directly set the input frequency (Input Clock

field, real values are allowed). Given an input frequency, it is possible to set the parameters in order to provide the required signals.

3.2.8. Configuration file

Once all parameters are set, the tool allows to save the configuration file which includes

all the AD9510 device settings (SAVE button in the upper toolbar of CAENPLLConfig

Main menu). It is also possible to browse and load into the AD9510 device a pre existing

configuration file (OPEN button in the upper toolbar of CAENPLLConfig Main menu). For

this purpose it is not necessary the board power cycle.

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3.2.9. Multiboard synchronisation

More boards can work synchronously, using an external clock source. Synchronisation can be achieved either by daisy chaining the boards or by using a fan out unit as clock distributor. In both cases the REF-CLK signal is common to all boards. When dividers are used, it is possible that, on different boards, the corresponding clock signals have different phases, although the dividers have the same value. The alignment of dividers output can be recovered by using the BSYNC signal, on whose edge all dividers are aligned (this operation is automatically performed at each reset on a single board); if more boards are used, it is necessary to synchronise ALL the BSYNC signals, through the S-IN front panel input. For this purpose, the S-IN signal must be synchronised with EXT-CLK. In order to ensure that also aquisition windows are aligned, it is necessary that also TRGIN is synchronised with EXT-CLK. Also edges must coincide in order to have alignment between triggers and buffers.

3.2.10. Internal clock

The board can work using the internal 50 MHz Local Oscillator as clock source. This source is processed by the clock distribution electronics (AD9510 chip), which delivers the 100 MHz Sampling Clock to the ADCs. The 100 MHz Sampling Clock is fed also to the FPGA ROC (in order to allow trigger synchronisation, see also Fig. 1.1) and to CLK_OUT (processed by a programmable divider and phase adjustment). Clock source (internal or external) is selected via internal switch SW1 (see § 2.6).

3.2.11. External clock and multiboard synchronisation

The board can work providing an external clock source (10÷100 MHz range). This source is processed by the clock distribution electronics (AD9510 device), which delivers the 100 MHz Sampling Clock to the ADCs. The 100 MHz Sampling Clock is fed also to the FPGA ROC (in order to allow trigger synchronisation) and to CLK_OUT (processed by a programmable divider and phase adjustment). It is possible to adjust frequency and phase of CLK_OUT and use such signal as clock source for another board, and so on, in order to have the same clock source for all the boards. Synchronisation is achieved, besides having the same clock source for all the boards, with all the boards sharing the same trigger signal (TRG_IN), and a common synchronisation (S_IN) signal: the latter is necessary in order to avoid a one Sampling Clock period jitter.

3.3. Acquisition Modes

3.3.1. Acquisition run/stop

The acquisition can be started in two ways, according to Acquisition Control register Bits [1:0] setting (see § 4.17):

− setting the RUN/STOP bit (bit[2]) in the Acquisition Control register (bits [1:0] of

Acquisition Control must be set to REGISTER-CONTROLLED RUN MODE or S-IN

CONTROLLED RUN MODE)

− driving S_IN signal high (bits [1:0] of Acquisition Control must be set to 01)

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Subsequentially acquisition is stopped either:

− resetting the RUN/STOP bit (bit[2]) in the Acquisition Control register (bits [1:0] of

Acquisition Control must be set to REGISTER-CONTROLLED RUN MODE or S-IN

CONTROLLED RUN MODE)

− driving S_IN signal low (bits [1:0] of Acquisition Control set to 01)

3.3.2. Gate and Sample mode acquisition

It is possible to use the S_IN signal (see § 2.4.2) as “gate” to enable samples storage. The samples produced by the 100 MHz ADC are stored in memory only if they are validated by the S_IN signal, otherwise they are rejected; data storage takes place by couples of samples (two 32 bit long words) per time. Two operating modes are foreseen, as decrbed in the following.

3.3.2.1. Gate mode

In Gate mode all the values sampled as the S-IN signal is active (high) are stored; for this purpose it is necessary to: Set bits [1:0] of Acquisition Control register to S-IN GATE MODE Set bit [0] of Channel Configuration Register (see § 4.12) to 0 All the values sampled as the S-IN signal is active (high) are stored.

S44

S12

S16

S 20

S 36

S32

S28

S 24

S48

S52

ADC DATA

SAMPLING CLOCK

S-I N

MEMORY

BUFFER

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

D2 D2D3D2

Fig. 3.5: Data Storage

D4 D5

in Gate mode

D9 D10 D11 D12

D2 D3 D4 D5 D6

D11 D12

Underscored = stored

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PRELIMINARY

3.3.3. Sample mode

In Sample mode only the first value sampled after the S-IN signal leading edge is stored; ; data storage takes place by couples of samples (two 32 bit long words) per time. For this purpose it is necessary to:

− Set bits [1:0] of Acquisition Control register to S-IN GATE MODE

− Set bit [0] of Channel Configuration Register (see § 4.12) to 1

Note that, if the S-IN signal is not synchronised with the sampling clock, then a 1 clock period jitter occurs between the S-IN leading edge and the actual sampling time.

S36

S12

S16

S20

S24

S32

S28

S40

S44

S48

S52

ADC DATA

SAMPLING CLOCK

S-I N

MEMORY

BUFFER

D0 D1 D2 D3 D4 D 5 D6 D7 D8 D9 D10

D1 D1 D1 D1 D1D5D1D5D1D5D1D5D1

D11 D12

Fig. 3.6: Data storage2 in Sample Mode

3.3.4. Acquisition Triggering: Samples and Events

When the acquisition is running, a trigger signal allows to:

− store a Trigger Time Tag (TTT): the value of a 32 bit counter which steps on with the sampling clock and represents a time reference

− increment the EVENT COUNTER (see § 4.29)

− fill the active buffer with the pre/post-trigger samples, whose number is

programmable via Post Trigger Setting register (see § 4.23); the Acquisition window width is determined via Buffer Organization register setting (see § 4.15,); then the buffer is frozen for readout purposes, while acquisition continues on another buffer.

Table 3.1: Buffer Organization

BUFFER NUMBER

(see § 4.15)

SRAM 1MB/ch (512KS) SRAM 8MB/ch (4MS) 0x00 1 512K 4M 0x01 2 256K 2M 0x02 4 128K 1M 0x03 8 64K 512K 0x04 16 32K 256K 0x05 32 16K 128K 0x06 64 8K 64K 0x07 128 4K 32K 0x08 256 2K 16K 0x09 512 1K 8K

0x0A 1024 512 4K

SIZE of one BUFFER (samples) REGISTER

Underscored = stored

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An event is therefore composed by the trigger time tag, pre- and post-trigger samples and the event counter. Overlap between “acquisition windows” may occur (a new trigger occurs while the board is still storing the samples related to the previous trigger); this overlap can be either rejected or accepted (programmable via VME). If the board is programmed to accept the overlapped triggers, as the “overlapping” trigger arrives, the current active buffer is filled up, then the samples storage continues on the subsequent one. In this case events will not have all the same size (see figure below).

EVENT n EVENT n+1 EVENT n+2

Recorded

TRIGGER

PRE POST ACQUISITION WINDOW

Not Recorded

Overlapping Triggers

Fig. 3.7: Trigger Overlap

A trigger can be refused for the following causes:

− acquisition is not active

− memory is FULL and therefore there are no available buffers

− the required number of samples for building the pre-trigger of the event is not

reached yet; this happens typically as the trigger occurs too early either with respect to the RUN_ACQUISITION command (see § 3.3.1) or with respect to a buffer emptying after a MEMORY_FULL status

− the trigger overlaps the previous one and the board is not enabled for accepting overlapped triggers

As a trigger is refused, the current buffer is not frozen and the acquisition continues writing on it. The Event Counter can be programmed in order to be either incremented or not. If this function is enabled, the Event Counter value identifies the number of the triggers sent (but the event number sequence is lost); if the function is not enabled, the Event Counter value coincides with the sequence of buffers saved and readout.

3.3.4.1. Custom size events

It is possible to make events with a number of Memory locations, which depends on

Buffer Organization register setting (see § 4.15) smaller than the default value. One memory location contains two ADC samples and the maximum number of memory locations N NS = 512K/Nblocks. Smaller N Custom Size register (see § 4.17).

is therefore half the maximum number of samples per block

LOC

values can be achieved by writing the number of locations N

LOC

into the

LOC

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= 0 means “default size events”, i.e. the number of memory locations is the

LOC

maximum allowed.

= N1, with the constraint 0<N1<½NS, means that one event will be made of 2⋅N1

LOC

samples.

3.3.5. Event structure

An event is structured as follows:

− identifier (Trigger Time Tag, Event Counter)

− samples caught in the acquisition windows

The event is stored in the board memories and can be readout via VME; data format is 32 bit long word, therefore each long_word contains 2 samples. The event format is the following:

31 30 29 28 27 262524 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

101 0

BOARD -ID

0 0

reserved

TRIGGER TIME TAG

SAMPLE [1] – CH[0] SAMPLE [0] – CH [0] SAMPLE [3] – CH[0] SAMPLE [2] – CH [0]

EVENT SIZE

PATTERN

EVENT COUNTERreserved

0 00 0

0 0

CHANNEL MASK

HEADER DATA CH0 DATA CH1

0 0 0 0

0 0

SAMPLE [N-1] – CH[0] SAMPLE [N-2] – CH [0]

SAMPLE [1] – CH[1] SAMPLE [0] – CH [1]

SAMPLE [3] – CH[1] SAMPLE [2] – CH [1]

SAMPLE [N-1] – CH[1] SAMPLE [N-2] – CH [1]

SAMPLE [1] – CH[7] SAMPLE [0] – CH [7] SAMPLE [3] – CH[7] SAMPLE [2] – CH [7]

SAMPLE [N-1] – CH[7] SAMPLE [N-2] – CH [7]

0 0 0 0

0 0

0 0 0 0

0 0

Table 3.2 : Event Organization

Header

It is composed by four words, namely:

− Size of the event (number of 32 bit long words)

− Board ID (GEO); a 16 bit pattern, latched on the LVDS I/O as one trigger arrives (see

§ 4.25); Channel Mask (=1: channels participating to event; ex CH5 and CH7 participating →Ch Mask: 0xA0, this information must be used by the software to acknowledge which channel the samples are coming from)

− Event Counter: It is the trigger counter; it can count either accepted triggers only, or all triggers (see § 4.17).

− Trigger Time Tag: It is a 32 bit counter (31 bit count + 1 overflow bit), which is reset either as acquisition starts or via front panel Reset signal (see § 3.8), and is incremented at each sampling clock hit. It is the trigger time reference.

Samples

Stored samples; data from masked channels are not read.

DATA CH7

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3.3.6. Memory FULL management

Bit5 of Acquisition Control register (see § 4.17), allows to select Memory FULL management mode: In Normal Mode the board becomes full, whenever all buffers are full (see § 4.15); otherwise (“Always one buffer free” mode) it is possible to always keep one buffer free: board becomes full, whenever N-1buffers are full; with N = nr. of blocks (see § 4.15). In Normal Mode, the board waits until one buffer is filled since FULL status is exited (whether the trigger is overlapped or not). The board exits FULL status at the moment which the last datum from the last channel participating to the event is read. In “Always one buffer free” mode, one buffer cannot be used (therefore it is NOT POSSIBLE, with this mode, to set Buffer Code to 0000; see § 4.15), but this allows to eliminate dead time when FULL status is exited.

3.4. Zero suppression

The board implements three algorithms of “Zero Suppression” and “Data Reduction”

- Full Suppression based on the integral of the signal (ZS_INT),

- Full Suppression based on the signal amplitude (ZS_AMP),

- Zero Length Encoding (ZLE), The algorithm to be used is selected via Control register, and its configuration takes place via two more registers (CHANNEL n ZS_THRES and CHANNEL n ZS_NSAMP). It must be noticed that one datum (32 bit long word) contains 2 samples: therefore one datum is considered over threshold as at least one sample reaches (or exceeds) the threshold. As a consequence, one datum is considered under threshold as both samples remain smaller than the threshold.

3.4.1. Zero Suppression Algorithm

3.4.1.1. Full Suppression based on the integral of the signal

Full Suppression based on the integral of the signal allows to discard a full event if the sum of all the samples in the event is smaller than the threshold set by the User (see

§ 4.3). It is also possible to configure the algorithm with “negative” logic: in this case the event is discarded if the sum of all the samples in the event is higher than the threshold set by the User (see § 4.3).

3.4.1.2. Full Suppression based on the amplitude of the signal

Full Suppression based on the signal amplitude allows to discard a full event if the signal does not exceed the programmed threshold for Ns subsequent data at least (Ns is programmable, see § 4.4). It is also possible to configure the algorithm with “negative” logic: in this case the event is discarded if the signal does not remain under the programmed threshold for Ns subsequent data at least (see § 4.4).

3.4.1.3. Zero Length Encoding ZLE

Zero Length Encoding allows to transfer the event in compressed mode, discarding either the data under the threshold set by the User (positive logic) or the data over the threshold set by the User (negative logic).

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With Zero length encoding it is also possible to set N

(LOOK BACK), the number of

LBK

data to be stored before the signal crosses the threshold and/or, N

LFWD

FORWARD), the number of data to be stored after the signal crosses the threshold (see

§ 4.3).

In this case the event of each channel has a particular format which allows the construction of the acquired time interval:

 Total size totale of the event (total number of transferred data)  Control word  [stored valid data, if control word is “good”]  Control word

 [stored valid data, if control word is “good”]  ...

The total size is the number of 32 bit data that compose the event (including the size itself).

The control word has the following format:

Bit Function

0: skip

[31]

1: good

[20:0] stored/skipped words

If the control word type is “good”, then it will be followed by as many data as those indicated in the “stored/skipped words” field; if the control word type is “skip” then it will be followed by a “good” control world, unless the end of event is reached.

Examples: If the input signal is the following:

(LOOK

Fig. 3.8: Zero Suppression example

If the algorithm works in positive logic, and

< N1 ;

LBK

< N5 ;

LFWD

+ N

LBK

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LFWD

< N3 ;

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Fig. 3.9: Example with positive logic and non-overlapping N

LBK

/ N

LFWD

then the readout event is: N'

+ N'4 + 5 (control words) + 1 (size)

Skip N Good N'

- N

LBK

= N

+ N2 + N

LBK

LFWD

... N'2 words with samples over threshold Skip N Good N'

- N

LFWD

= N

- N + N4 + N

LBK

LFWD

... N'4 words with samples over threshold Skip N

- N

LFWD

If the algorithm works in negative logic, and

N N

LBK LBK

+ N + N

LFWD LFWD

< N2 ; < N4 ;

Fig. 3.10: Example with negative logic and non-overlapping N

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LBK

/ N

LFWD

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then the readout event is: N'

+ N'3 + N'5 + 5 (control words) + 1 (size)

Good N'

= N1 + N

LFWD

... N'1 words with samples under threshold Skip N Good N'

- N

LFWD

= N

- N + N3 + N

LBK

LFWD

... N'3 words with samples under threshold Skip N Good N'5 = N

- N

LFWD

LBK

- N

+ N

LBK

... N'5 words with samples under threshold

In some cases the number of data to be discarded can be smaller than N

LBK

and N

1) If the algorithm works in positive logic, and

N N

≤ N

LFWD

LBK

= 0 ;

< N3 ;

LFWD

Fig. 3.11: Example with positive logic and non overlapping N

LBK

then the readout event is: N

+N2 + N'4 + 5 (control words) + 1 (size)

Good N

+ N

... N1 + N2 words with samples over threshold Skip N Good N'

- N

LBK

= N

LBK

+ N

... N'4 words with samples over threshold Skip N

2) If the algorithm works in positive logic, and = 0 ;

LBK

≤ N

LFWD

< N3 ;

then the readout event is: N'

+ N4 +N5 + 5 (control words) + 1 (size)

Skip N

Good N'

= N2 + N

LFWD

... N'2 words with samples over threshold

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Skip N3 - N

LFWD

Good N4 + N

... N4 + N5 words with samples over threshold

3) If the algorithm works in positive logic, and

= 0 ;

LBK

≤ N

LFWD

< N5 ;

then the readout event is: N'

+ 3 (control words) + 1 (size)

Skip N Good N'

= N2 + N3 + N4 + N

LFWD

... N'2 words with samples over threshold Skip N

- N

LFWD

4) If the algorithm works in positive logic, and

LFWD

≤ N

LBK

= 0 ;

< N1 ;

Fig. 3.12: Example with positive logic and overlapping N

LBK

then the readout event is: N'

+N'4 + 4 (control words) + 1 (size)

Skip N Good N'

- N

LBK

= N

LBK

+ N

... N'2 words with samples over threshold Good N'

= N3 + N

... N'4 words with samples over threshold Skip N

N.B: In this case there are two subsequent “GOOD” intervals.

5) If the algorithm works in positive logic, and

0 < N N

LFWD

LBK

< N1 ;

LBK

< N5 ;

+ N

LFWD

≥ N

3 .

then the readout event is:

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N'2 + N'4 + 4 (control words) + 1 (size) Skip N Good N'

- N

LBK

= N

+ N2 + N

LBK

LFWD

... N'2 words with samples over threshold Good N'

= (N3 - N

LFWD

) + N4 + N

LFWD

... N'4 words with samples over threshold Skip N

- N

LFWD

N.B: In this case there are two subsequent “GOOD” intervals. These examples are reported with positive logic; the compression algorithm is the same also working in negative logic.

3.5. Trigger management

All the channels in a board share the same trigger: this means that all the channels store an event at the same time and in the same way (same number of samples and same position with respect to the trigger); several trigger sources are available.

Mother Board

Mezzanines

Memory

TRG OUT

TRG IN

Enable Mask

VME

Interface

SW TRG

Interface

TRIGGER

LOCAL TRG

SCLK

Local Bus

Buffers

Acquisition

Logic

Digital

Thresholds

Fig. 3.13: Block diagram of Trigger management

3.5.1. External trigger

External trigger can be NIM/TTL signal on LEMO front panel connector, 50 Ohm impedance. The external trigger is synchronised with the internal clock (see § 3.2.11); if External trigger is not synchronised with the internal clock, a one clock period jitter occurs.

ADC

3.5.2. Software trigger

Software trigger are generated via VME bus (write access in the relevant register, see

§ 4.20).

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3.5.3. Local channel auto-trigger

Each channel can generate a local trigger as the digitised signal exceeds the Vth threshold (ramping up or down, depending on VME settings), and remains under or over threshold for Nth “quartets” of samples at least (Nth is programmable via VME). The Vth digital threshold, the edge type, and the minimum number Nth of couples of samples are programmable via VME register accesses, see § 4.3 and § 4.6; actually local trigger is delayed of Nth quartets of samples with respect to the input signal. N.B.: the local trigger signal does not start directly the event acquisition on the relevant channel; such signal is propagated to the central logic which produces the global trigger, which is distributed to all channels (see § 3.5.4).

Nth [4samples]

THRESHOLD

CH0 IN

Nth [4samples]

Local Trigger CH0 (Channel

Configuration register <6> =0)

Local Trigger CH0 (Channel

Configuration register <6> =1)

Fig. 3.14: Local trigger generation

3.5.4. Trigger distribution

The OR of all the enabled trigger sources, after being synchronised with the internal clock, becomes the global trigger of the board and is fed in parallel to all the channels, which store an event. A Trigger Out is also generated on the relevant front panel TRG_OUT connector (NIM or TTL), and allows to extend the trigger signal to other boards. For example, in order to start the acquisition on all the channels in the crate, as one of the channels ramps over threshold, the Local Trigger must be enabled as Trigger Out, the Trigger Out must then be fed to a Fan Out unit; the obtained signal has to be fed to the External Trigger Input of all the boards in the crate (including the board which generated the Trigger Out signal).

3.6. Front Panel I/Os

The V1724 is provided with 16 programmable general purpose LVDS I/O signals. Signals can be programmed via VME (see § 4.24 and § 4.25). Default configuration is:

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Table 3.3 : Front Panel I/Os default setting

Nr. Direction Description

0 out Ch 0 Trigger Request 1 out Ch 1 Trigger Request 2 out Ch 2 Trigger Request 3 out Ch 3 Trigger Request 4 out Ch 4 Trigger Request 5 out Ch 5 Trigger Request 6 out Ch 6 Trigger Request 7 out Ch 7 Trigger Request 8 out Memory Full 9 out Event Data Ready 10 out Channels Trigger 11 out RUN Status 12 in Trigger Time Tag Reset (active low) 13 in Memory Clear (active low) 14 - RESERVED 15 - RESERVED

3.7. Analog Monitor

The board houses a 12bit (100MHz) DAC with 0÷1 V dynamics on a 50 Ohm load (see Fig. 1.1), whose input is controlled by the ROC FPGA and the signal output (driving 50 Ohm) is available on the MON/Σ output connector. MON output of more boards can be summed by an external Linear Fan In. This output is delivered by a 12 bit DAC.

The DAC control logic implements five operating modes:

- Trigger Majority Mode ( Monitor Mode = 0)

- Test Mode (Monitor Mode = 1)

- Analog Monitor/Inspection Mode (Monitor Mode = 2)

- Buffer Occupancy Mode (Monitor Mode = 3)

- Voltage Level Mode (Monitor Mode = 4)

Operating mode is selected via Monitor Mode register (see § 4.32)

N.B.: this feature is not available on the Mod. V1724LC

3.7.1. Trigger Majority Mode (Monitor Mode = 0)

It is possible to generate a Majority signal with the DAC: a voltage signal whose amplitude is proportional to the number of channels under/over (see § 4.12) threshold (1 step = 125mV); this allows, via an external discriminator, to produce a global trigger signal, as the number of triggering channels has exceeded a particular threshold.

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THRESHOLD

Nth [4samples]

CH0 IN

THRESHOLD

CH1 IN

MAJORITY

Nth [4samples]

2.5mV

1.25mV

Fig. 3.15: Majority logic (2 channels over threshold; bit[6] of Ch. Config. Register =0)

In this mode the MON output provides a signal whose amplitude is proportional to the number of channels over the trigger threshold. The amplitude step (= +1 channel over threshold) is 125mV.

3.7.2. Test Mode (Monitor Mode = 1)

In this mode the MON output provides a sawtooth signal with 1 V amplitude and 24.41 Hz frequency.

3.7.3. Analog Monitor/Inspection Mode (Monitor Mode = 2)

In this mode the MON output provides a signal whose amplitude is proportional to the sum of the board channels. The following diagram shows the way the channels data are processed.

Fig. 3.16: Inspection Mode diagram

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Data converted by channel ADC are brought to the FPGA via a 2 bit BUS. Data transfer timing is provided by TRG-CLK; the available bandwidth is 200 Mb/s. The FPGA ROC handles 8 bit data. Data rate is ¼ of TRG-CLK. Chx DATA represents the 8 MSB of the converted sample. Data from 8 channels are summed; each channel can be enabled (see Analog Monitor Register at § 4.34) to participate or not to the sum. The sum value is provided on 11 bit; a positive/negative offset (also encoded on 11bit) can be added to the sum (there is a sign bit in the Analog Monitor Register AMR to select offset polarity). The sum value can be multiplied by a fixed factor (MAGNIFY x1, x2, x4, x8). The final result (11 bit dynamics) allows to drive the DAC. The DAC output has 1V dynamics and drives 50 Ohm.

3.7.3.1. Procedure to enable “Analog Monitor” mode

In order to enable Analog Monitor mode is necessary to:

− enable the channels to send data to FPGA ROC, by setting to 1 bit 7 of Channel Configuration register (see § 4.12). If this bit is set the datum sent is always 0.

− Configure the Analog Monitor register with the desired settings.

− Enable Analog Monitor mode: set to 2 the Monitor Mode register.

3.7.3.2. Applications examples

These examples show the effect of the channel/offset/magnify parameters over MON output. Single channel amplified on 0-1 V dynamics:

Fig. 3.17: Example of Magnify parameter use on single channel

The assumption is an input signal on CH0 using the whole dynamics. Only such channel is enabled for Analog Monitor; the triangular waveform is just as example. FPGA AMC of CH0 sends 8MSB to FPGA ROC with 25 Mhz rate (one sample out of four). If no output is added and MAGNIFY factor 1x, the DAC produces a copy of the signal on channel 0 with 0÷125 mV dynamics (1/8 of DAC dynamics). If a larger dynamics is desired, it is necessary increase MAGNIFY factor; with MAGNIFY 8x one channel covers all the DAC available dynamics.

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Channel sum with maximum dynamics:

Fig. 3.18: Example of Magnify and Offset parameters use on single channel

The assumption is an input signal on CH0 using th whole dynamics and all channels participating to Analog Monitor. The ADC on the mezzanine produces data in the 0÷16383 range (14 bit). All channels have 0 offset and therefore the ADC converted value is 8192. The triangular waveform is shown as example. The FPGA AMC of channel 0 sends the 8 MSB to FPGA ROC with a 25 Mhz rate (one sample out of four). If no output is added and MAGNIFY factor 1x, the DAC produces a copy of the signal on channel 0 with 125 mV dynamics (1/8 of DAC dynamics) and 500 mV average value. If a larger dynamics is desired, it is necessary to modify 0FFSET and MAGNIFY factor: in order to avoid saturation it is necessary to subtract to the channel sum a value equal to the minimum of the channel sum (displacement).

3.7.4. Buffer Occupancy Mode (Monitor Mode = 3)

In this mode, MON out provides a voltage value proportional to the number of buffers filled with events; step: 1 buffer = 0.976 mV. . This mode allows to test the readout efficiency: in fact if the average event readout throughput is as fast as trigger rate, then MON out value remains constant; otherwise if MON out value grows in time, this means that readout rate is slower than trigger rate.

3.7.5. Voltage Level Mode (Monitor Mode = 4)

In this mode, MON out provides a voltage value programmable via the 'N' parameter written in the SET MONITOR DAC register, with: Vmon = 1/4096*N (Volt).

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3.8. Test pattern generator

The FPGA AMC can emulate the ADC and write into memory a ramp (0, 1, 2, 3,…3FFF, 3FFF, 3FFE.., 0) for test purposes. It can be enabled via Channel Configuration register, see § 4.12.

3.9. Reset, Clear and Default Configuration

3.9.1. Global Reset

Global Reset is performed at Power ON of the module or via a VME RESET (SYS_RES), see § 4.44. It allows to clear the data off the Output Buffer, the event counter and performs a FPGAs global reset, which restores the FPGAs to the default configuration. It initialises all counters to their initial state and clears all detected error conditions.

3.9.2. Memory Reset

The Memory Reset clears the data off the Output Buffer. The Memory Reset can be forwarded via either a write access to Software Clear Register (see § 4.45) or with a pulse sent to the front panel Memory Clear input (see § 3.6).

3.9.3. Timer Reset

The Timer Reset allows to initialize the timer which allows to tag an event. The Timer Reset can be forwarded with a pulse sent to Trigger Time Tag Reset input (see § 3.6).

3.10. VMEBus interface

The module is provided with a fully compliant VME64/VME64X interface (see § 1.1), whose main features are:

− EUROCARD 9U Format

− J1/P1 and J2/P2 with either 160 pins (5 rows) or 96 (3 rows) connectors

− A24, A32 and CR-CSR address modes

− D32, BLT/MBLT, 2eVME, 2eSST data modes

− MCST write capability

− CBLT data transfers

− RORA interrupter

− Configuration ROM

3.10.1. Addressing capabilities

3.10.1.1. Base address

The module works in A24/A32 mode. The Base Address of the module can be fixed through four rotary switches (see § 2.6) and is written into a word of 24 or 32 bit. The Base Address can be selected in the range:

0x000000 ÅÆ 0xFF0000 A24 mode

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31 16 15 0

2324

OFFSET

SW4 SW5

Fig. 3.19: A24 addressing

0x00000000 ÅÆ 0xFFFF0000 A32 mode

31 16 15 0

2324

OFFSET

SW5SW4SW3SW2

Fig. 3.20: A32 addressing

The Base Address of the module is selected through four rotary switches (see § 2.6), then it is validated only with either a Power ON cycle or a System Reset (see § 3.8).

3.10.1.2. CR/CSR address

GEO address is picked up from relevant backplane lines and written onto bit 23..19 of CR/CSR space, indicating the slot number in the crate; the recognised Address Modifier

for this cycle is 2F. This feature is implemented only on versions with 160pin connectors.

2324

31 16 15 0

19 18

GEO

OFFSET

Fig. 3.21: CR/CSR addressing

3.10.1.3. Address relocation

Relocation Address register (see § 4.39) allows to set via software the board Base Address (valid values ≠ 0). Such register allows to overwrite the rotary switches settings; its setting is enabled via VME Control Register (see § 4.30). The used addresses are:

31 16 15 0

2324

OFFSET

A32

ADER H ADER L

31 1615 0

2324

software

relocation

OFFSET

A24

ADER L

software

relocation

Fig. 3.22: Software relocation of base address

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3.11. Data transfer capabilities

The board supports D32 single data readout, Block Transfer BLT32 and MBLT64, 2eVME and 2eSST cycles. Sustained readout rate is up to 60 MB/s with MBLT64, up to 100 MB/s with 2eVME and up to 160 MB/s with 2eSST.

3.12. Events readout

3.12.1. Sequential readout

The events, once written in the SRAMs (Memory Event Buffers), become available for readout via VME. During the memory readout, the board can continue to store more events (independently from the readout) on the free buffers. The acquisition process is therefore “deadtimeless”, until the memory becomes full. Although the memories are SRAMs, VMEBus does not handle directly the addresses, but takes them from a FIFO. Therefore, data are read from the memories sequentially, according to the selected Readout Logic, from a memory space mapped on 4Kbytes (0x0000÷0x0FFC). The events are readout sequentially and completely, starting from the Header of the first available event, followed by the Trigger Time Tag, the Event Counter and all the samples of the channels (from 0 to 7). Once an event is completed, the relevant memory buffer becomes free and ready to be written again (old data are lost). After the last word in an event, the first word (Header) of the subsequent event is readout. It is not possible to readout an event partially (see also § 3.3.5).

3.12.1.1. SINGLE D32

This mode allows to readout a word per time, from the header (actually 4 words) of the first available event, followed by all the words until the end of the event, then the second event is transferred. The exact sequence of the transferred words is shown in § 3.3.5. We suggest, after the 1

word is transferred, to check the Event Size information and then do as many D32 cycles as necessary (actually Event Size -1) in order to read completely the event.

3.12.1.2. BLOCK TRANSFER D32/D64, 2eVME

BLT32 allows, via a single channel access, to read N events in sequence, N is set via the BLT Event Number register (see § 4.42). The event size depends on the Buffer Size Register setting (§ 4.15); namely:

[Event Size] = [8*(Block Size)] + [16 bytes]

Smaller event size can be achieved via Custom Size setting (see § 3.3.4.1 and § 4.17). Then it is necessary to perform as many cycles as required in order to readout the programmed number of events. We suggest to enable BERR signal during BLT32 cycles, in order to end the cycle avoiding filler readout. The last BLT32 cycle will not be completed, it will be ended by BERR after the #N event in memory is transferred (see example in the figure below).

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Block size = 1024 bytes BERR = enabled BLT size = 16384 bytes N = 4

Fig. 3.23: Example of BLT readout

Since some 64 bit CPU’s cut off the last 32 bit word of a transferred block, if the number of words composing such block is odd, it is necessary to add a dummy word (which has then to be removed via software) in order to avoid data loss. This can be achieved by setting the ALIGN64 bit in the VME Control register (see § 4.30).

MBLT64 cycle is similar to the BLT32 cycle, except that the address and data lines are multiplexed to form 64 bit address and data buses.

The 2eVME allows to achieve higher transfer rates thanks to the requirement of only two edges of the two control signals (DS and DTACK) to complete a data cycle.

3.12.1.3. CHAINED BLOCK TRANSFER D32/D64

The V1724 allows to readout events from more daisy chained boards (Chained Block Transfer mode). The technique which handles the CBLT is based on the passing of a token between the boards; it is necessary toverify that the used VME crate supports such cycles. Several contiguous boards, in order to be daisy chained, must be configured as “first”, “intermediate” or “last” via MCST Base Address and Control Register (see § 4.38). A common Base Address is then defined via the same register; when a BLT cycle is executed at the address CBLT_Base + 0x0000 ÷ 0x0FFC, the “first” board starts to transfer its data, driving DTACK properly; once the transfer is completed, the token is passed to the second board via the IACKIN-IACKOUT lines of the crate, and so on until the “last” board, which completes the data transfer and asserts BERR (which has to be enabled): the Master then ends the cycle and the slave boards are rearmed for a new acquisition. If the size of the BLT cycle is smaller than the events size, the board which has the token waits for another BLT cycle to begin (from the point where the previous cycle has ended).

3.12.2. Random readout (to be implemented)

Events can be readout partially (not necessarily starting from the first available) and are not erased from the memories, unless a command is performed. In order to perform the

random readout it is necessary to execute an Event Block Request via VME.

Indicating the event to be read (page number = 12 bit datum), the offset of the first word to be read inside the event (12 bit datum) and the number of words to be read (size = 10 bit datum). At this point the data space can be read, starting from the header (which

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reports the required size, not the actual one, of the event), the Trigger Time Tag, the Event Counter and the part of the event required on the channel addressed in the Event Block Request. After data readout, in order to perform a new random readout, it is necessary a new Event Block Request, otherwise Bus Error is signalled. In order to empty the buffers, it is

necessary a write access to the Buffer Free register (see § 4.16): the datum written is the

number of buffers in sequence to be emptied.

Fig. 3.24: Example of random readout

3.12.3. Event Polling

A read access to Event Size register (see § 4.33) allows “polling” the number of 32 bit words composing the next event to be read: this permits to perform a properly sized (according to the Event Size information) BLT readout from the Memory Event Buffer.

3.13. Optical Link

The board houses a daisy chainable Optical Link able to transfer data at 80 MB/s, therefore it is possible to connect up to eight V1724 (64 ADC channels) to a single Optical Link Controller: a standard PC equipped with the PCI card CAEN Mod. A2818. The A2818 is a 32-bit 33 MHz PCI card; the communication path uses optical fiber cables as physical transmission line (Mod. AY2705, AY2720, AI2705, AI2720). The Optical Link allows to perform VME read (Single data transfer and Block transfers) and write (Single data transfer) operations. The parameters for read/write accesses via optical link are the same used by VME cycles (Address Modifier, Base Address, data Width, etc); wrong parameter settings cause Bus Error. VME Control Register bit 3 (see § 4.34) allows to enable the module to broadcast an interrupt request on the Optical Link; an 8 bit mask (see § 3.13.12 and § 3.13.13) allows to enable the corresponding A2818’s to propagate the interrupt on the PCI bus as a request from the Optical Link is sensed. VME and Optical Link accesses take place on independent paths and are handled by board internal controller, with VME having higher priority; anyway it is better to avoid accessing the board via VME and Optical Link simoultaneously.

N.B.: Optical Link is not available on the Mod. V1724LC

The following diagram shows how to connect V1724 modules to the Optical Link:

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Link:

PC side

A2818

crate side

V17XX

BdNum

PC side

A2818

V17XX

Fig. 3.25: Optical Link daisy chain

The Optical Link can be operated through the CAENVMELib library: a set of ANSI C functions which permits an user program the use and the configuration of the modules. The present description refers to CAENVMELib, available in the following formats:

− Win32 DLL (CAEN provides the CAENVMELib.lib stub for Microsoft Visual C++ 6.0)

− Linux dynamic library

CAENVMELib is logically located between an application like the samples provided and the device driver. The following sections describe the CAENVMELib library and its implemented functions.

3.13.1. CAENVME_Init

Parameters: [in] BdType : The model of the board (V2718). [in] Link : The index of the A2818 (see figure above). [in] BdNum : The board number in the link (see figure above). [out] Handle : The handle that identifies the device.

Returns: An error code about the execution of the function.

Description:

The function generates an opaque handle to identify the module

attached to the PC. It must be specified only the module index (BdNum) because the link is PCI.

CAENVME_API CAENVME_Init(CVBoardTypes BdType, short Link, short BdNum, long *Handle);

3.13.2. CAENVME_End

Parameters: [in] Handle: The handle that identifies the module.

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Returns: An error code about the execution of the function.

Description: Notifies the library about the end of work and free the allocated resources.

CAENVME_API CAENVME_End(long Handle);

3.13.3. CAENVME_ReadCycle

Parameters: [in] Handle : The handle that identifies the device. [in] Address : The VME bus address [out] Data : The data read from the VME bus. [in] AM : The address modifier . [in] DW : The data width.

Returns: An error code about the execution of the function. Description: The function performs a single VME read cycle.

CAENVME_API CAENVME_ReadCycle(long Handle, unsigned long Address, void *Data, CVAddressModifier AM, CVDataWidth DW);

3.13.4. CAENVME_WriteCycle

Parameters: [in] Handle : The handle that identifies the device. [in] Address : The VME bus address. [in] Data : The data written to the VME bus. [in] AM : The address modifier. [in] DW : The data width.

Returns: An error code about the execution of the function.

Description: The function performs a single VME write cycle.

CAENVME_API CAENVME_WriteCycle(long Handle, unsigned long Address, void *Data, CVAddressModifier AM, CVDataWidth DW);

3.13.5. CAENVME_MultiRead

Parameters: [in] Handle : The handle that identifies the device.

The Board base address set via rotary switches (see § 2.6)

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[in] Address : An array of VME bus addresses. [out] Data : An array of data read from the VME bus.

[in] AM : An array of address modifiers.

[in] DW : An array of data widths.

Returns: An array of error codes about the execution of the function. Description:

The function performs a sequence of VME read cycles.

CAENVME_API CAENVME_MultiRead(long Handle, unsigned long Address, void *Data, CVAddressModifier AM, CVDataWidth DW);

3.13.6. CAENVME_MultiWrite

Parameters: [in] Handle : The handle that identifies the device. [in] Address : An array of VME bus addresses. [in] Data : An array of data written to the VME bus.

[in] AM : An array of address modifiers.

[in] DW : An array of data widths.

Returns: An array of error codes about the execution of the function. Description:

The function performs a sequence of VME write cycles.

CAENVME_API CAENVME_ReadCycle(long Handle, unsigned long Address, void *Data, CVAddressModifier AM, CVDataWidth DW);

3.13.7. CAENVME_BLTReadCycle

Parameters: [in] Handle : The handle that identifies the device. [in] Address : The VME bus address. [out] Buffer : The data read from the VME bus. [in] Size : The size of the transfer in bytes. [in] AM : The address modifier. [in] DW : The data width. [out] count : The number of bytes transferred.

Returns: An error code about the execution of the function.

Description: The function performs a VME block transfer read cycle. It can be used to perform MBLT transfers using 64 bit data width.

CAENVME_API CAENVME_BLTReadCycle(long Handle, unsigned long Address, unsigned char *Buffer, int Size, CVAddressModifier AM, CVDataWidth DW, int *count);

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3.13.8. CAENVME_FIFOBLTReadCycle

Parameters: [in] Handle : The handle that identifies the device. [in] Address : The VME bus address. [out] Buffer : The data read from the VME bus. [in] Size : The size of the transfer in bytes. [in] AM : The address modifier [in] DW : The data width. [out] count : The number of bytes transferred.

Returns: An error code about the execution of the function. Description: The function performs a VME block transfer read cycle. It can be used to perform MBLT transfers using 64 bit data width. The Address is not incremented on the VMEBus during the cycle.

CAENVME_API CAENVME_FIFOBLTReadCycle(int32_t Handle, uint32_t Address, void *Buffer, int Size, CVAddressModifier AM, CVDataWidth DW, int *count);

3.13.9. CAENVME_MBLTReadCycle

Returns: An error code about the execution of the function.

Description: The function performs a VME multiplexed block transfer read cycle.

CAENVME_API CAENVME_MBLTReadCycle(long Handle, unsigned long Address, unsigned char *Buffer, int Size, CVAddressModifier AM, int *count);

3.13.10. CAENVME_FIFOMBLTReadCycle

Returns: An error code about the execution of the function.

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Description: The function performs a VME multiplexed block transfer read cycle. The Address is not incremented on the VMEBus during the cycle.

CAENVME_API CAENVME_FIFOMBLTReadCycle(int32_t Handle, uint32_t Address, void *Buffer, int Size, CVAddressModifier AM, int *count);

3.13.11. CAENVME_IRQCheck

Parameters: [in] Handle : The handle that identifies the device. [out] Mask : A bit-mask

Returns: An error code about the execution of the function.

Description: The function returns a bit mask indicating the active IRQ lines.

CAENVME_API CAENVME_IRQCheck(long Handle, byte *Mask);

indicating the active IRQ lines

3.13.12. CAENVME_IRQEnable

Parameters:

[in] Handle : The handle that identifies the device. [in] Mask : A bit-mask indicating the IRQ lines.

Returns: An error code about the execution of the function.

Description: The function enables the IRQ lines specified by Mask.

CAENVME_API CAENVME_IRQEnable(long dev, unsigned long Mask);

3.13.13. CAENVME_IRQDisable

Parameters:

[in] Handle : The handle that identifies the device.

[in] Mask : A bit-mask indicating the IRQ lines.

Returns:

An error code about the execution of the function.

Description:

The function disables the IRQ lines specified by Mask.

Actually only bit 0 in the mask is meaningful

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CAENVME_API CAENVME_IRQDisable(long dev, unsigned long Mask);

3.13.14. CAENVME_IRQWait

Parameters:

[in] Handle : The handle that identifies the device. [in] Mask : A bit-mask indicating the IRQ lines. [in] Timeout : Timeout in milliseconds.

Returns: An error code about the execution of the function.

Description:

The function waits the IRQ lines specified by Mask until one of them raise or timeout expires.

CAENVME_API CAENVME_IRQWait(long dev, unsigned long Mask, unsigned long Timeout);

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4. VME Interface

The following sections will describe in detail the board’s VME-accessible registers content.

4.1. Registers address map

Table 4.1: Address Map for the Model V1724

EVENT READOUT BUFFER 0x0000-0x0FFC A24/A32/A64 D32 R X X X Channel n ZS_THRES 0x1n24 A24/A32 D32 R/W X X Channel n ZS_NSAMP 0x1n28 A24/A32 D32 R/W X X Channel n THRESHOLD 0x1n80 A24/A32 D32 R/W X X Channel n TIME OVER/UNDER THRESHOLD 0x1n84 A24/A32 D32 R/W X X Channel n STATUS 0x1n88 A24/A32 D32 R X X

Channel n AMC FPGA FIRMWARE REVISION 0x1n8C A24/A32 D32 R

Channel n BUFFER OCCUPANCY 0x1n94 A24/A32 D32 R X X X Channel n DAC 0x1n98 A24/A32 D32 R/W X X Channel n ADC CONFIGURATION 0x1n9C A24/A32 D32 R/W X X CHANNEL CONFIGURATION 0x8000 A24/A32 D32 R/W X X CHANNEL CONFIGURATION BIT SET 0x8004 A24/A32 D32 W X X CHANNEL CONFIGURATION BIT CLEAR 0x8008 A24/A32 D32 W X X BUFFER ORGANIZATION 0x800C A24/A32 D32 R/W X X BUFFER FREE 0x8010 A24/A32 D32 R/W X X CUSTOM SIZE 0x8020 A24/A32 D32 R/W X X ACQUISITION CONTROL 0x8100 A24/A32 D32 R/W X X

ACQUISITION STATUS 0x8104 A24/A32 D32 R

SW TRIGGER 0x8108 A24/A32 D32 W

TRIGGER SOURCE ENABLE MASK 0x810C A24/A32 D32 R/W X X FRONT PANEL TRIGGER OUT ENABLE MASK 0x8110 A24/A32 D32 R/W X X POST TRIGGER SETTING 0x8114 A24/A32 D32 R/W X X FRONT PANEL I/O DATA 0x8118 A24/A32 D32 R/W X X FRONT PANEL I/O CONTROL 0x811C A24/A32 D32 R/W X X CHANNEL ENABLE MASK 0x8120 A24/A32 D32 R/W X X

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ROC FPGA FIRMWARE REVISION 0x8124 A24/A32 D32 R

DOWNSAMPLE FACTOR 0x8128 A24/A32 D32 R/W X X EVENT STORED 0x812C A24/A32 D32 R X X X SET MONITOR DAC 0x8138 A24/A32 D32 R/W X X

BOARD INFO 0x8140 A24/A32 D32 R

MONITOR MODE 0x8144 A24/A32 D32 R/W X X EVENT SIZE 0x814C A24/A32 D32 R X X X ANALOG MONITOR 0x8150 A24/A32 D32 R/W X X

VME CONTROL 0xEF00 A24/A32 D32 R/W X

VME STATUS 0xEF04 A24/A32 D32 R

BOARD ID 0xEF08 A24/A32 D32 R/W X X MULTICAST BASE ADDRESS & CONTROL 0xEF0C A24/A32 D32 R/W X RELOCATION ADDRESS 0xEF10 A24/A32 D32 R/W X INTERRUPT STATUS ID 0xEF14 A24/A32 D32 R/W X INTERRUPT EVENT NUMBER 0xEF18 A24/A32 D32 R/W X X BLT EVENT NUMBER 0xEF1C A24/A32 D32 R/W X X SCRATCH 0xEF20 A24/A32 D32 R/W X X

SW RESET 0xEF24 A24/A32 D32 W

SW CLEAR 0xEF28 A24/A32 D32 W

FLASH ENABLE 0xEF2C A24/A32 D32 R/W X FLASH DATA 0xEF30 A24/A32 D32 R/W X

CONFIGURATION RELOAD 0xEF34 A24/A32 D32 W

CONFIGURATION ROM 0xF000-0xF3FC A24/A32 D32 R

4.2. Configuration ROM (0xF000-0xF084; r)

The following registers contain some module’s information, they are D32 accessible (read only):

▪ OUI: manufacturer identifier (IEEE OUI) ▪ Version: purchased version ▪ Board ID: Board identifier ▪ Revision: hardware revision identifier ▪ Serial MSB: serial number (MSB) ▪ Serial LSB: serial number (LSB)

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Table 4.2: ROM Address Map for the Model V1724

Description Address Content

checksum 0xF000 checksum_length2 0xF004 0x00 checksum_length1 0xF008 0x00 checksum_length0 0xF00C 0x20 constant2 0xF010 0x83 constant1 0xF014 0x84 constant0 0xF018 0x01 c_code 0xF01C 0x43 r_code 0xF020 0x52 oui2 0xF024 0x00 oui1 0xF028 0x40 oui0 0xF02C 0xE6

vers 0xF030

board2 0xF034

board1 0xF038 0x06 board0 0xF03C 0xBC revis3 0xF040 revis2 0xF044 revis1 0xF048 revis0 0xF04C sernum1 0xF080 sernum0 0xF084

0xA4

V1724LC : 0x10 V1724, VX1724: 0x11 V1724B, VX1724B: 0x40 V1724C, VX1724C: 0x12 V1724D, VX1724D: 0x41 V1724E, VX1724E: 0x42 V1724F, VX1724F: 0x43 V1724: 0x00 VX1724: 0x01

0x00 0x00 0x00 0x01 0x00 0x16

These data are written into one Flash page; at Power ON the Flash content is loaded into the Configuration RAM, where it is available for readout.

4.3. Channel n ZS_THRES (0x1n24; r/w)

Bit Function

0 = Positive Logic

[31]

1 = Negative Logic Threshold Weight (used in “Full Suppression based on the integral” only)

[30]

0 = Fine threshold step (Threshold = ZS_THRES[29:0]) 1 = Coarse threshold step (Threshold = ZS_THRES[29:0] * 64) With “Full Suppression based on the integral”, the 30 LSB value represents the value (depending on bit 30) to be compared with sum of the samples which compose the event, and see if it is over/under threshold (depending on the used logic).

[29:0]

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With “Full Suppression based on the amplitude”, the 14 LSB represent the value to be compared with each sample of the event; and see if it is over/unedr threshold (depending on the used logic). With “Zero Length Encoding”, the 14 LSB represent the value to be compared with each sample of the event, and see if it is “good” or “skip” type. (see § 3.4 and § 4.12)

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4.4. Channel n ZS_NSAMP (0x1n28; r/w)

Bit Function

With “Full Suppression based on the amplitude” (ZS AMP), bits [20:0] allow to set the number Ns of subsequent samples which must be found over/under threshold (depending on the used logic) necessary to validate the event; if this field is set to 0, it is considered “1”.

[31:0]

With “Zero length encoding” (ZLE) bit [15:0] allows to set/read N number of data to be stored before the signal crosses the threshold. bit [31:16] allows to set/read N after the signal crosses the threshold (see § 3.4 and § 4.12)

: the number of data to be stored

LFWD

LBK

: the

4.5. Channel n Threshold (0x1n80; r/w)

Bit Function

[13:0] Threshold Value for Trigger Generation

Each channel can generate a local trigger as the digitised signal exceeds the Vth threshold, and remains under or over threshold for Nth couples of samples at least; local trigger is delayed of Nth “quartets” of samples with respect to input signal. This register allows to set Vth (LSB=input range/14bit); see also § 3.5.3.

4.6. Channel n Over/Under Threshold (0x1n84; r/w)

Bit Function

[11:0] Number of Data under/over Threshold

Each channel can generate a local trigger as the digitised signal exceeds the Vth threshold, and remains under or over threshold for Nth “quartets” of samples at least; local trigger is delayed of Nth “quartets” with respect to input signal. This register allows to set Nth; see also § 3.5.3.

4.7. Channel n Status (0x1n88; r)

Bit Function

Buffer free error:

[5]

1 = trying to free a number of buffers too large

[4]

CHn+1 enabled

[3] CHn enabled

Channel n DAC (see § 4.10) Busy

[2]

1 = Busy

0 = DC offset updated [1] Memory empty [0] Memory full

4.8. Channel n AMC FPGA Firmware (0x1n8C; r)

Bit Function

[31:16] Revision date in Y/M/DD format

[15:8] Firmware Revision (X)

[7:0] Firmware Revision (Y)

Bits [31:16] contain the Revision date in Y/M/DD format.

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Bits [15:0] contain the firmware revision number coded on 16 bit (X.Y format). Example: revision 1.3 of 12

June 2007 is: 0x760C0103

4.9. Channel n Buffer Occupancy (0x1n94; r)

Bit Function

[10:0] Occupied buffers (0..1024)

4.10. Channel n DAC Register (0x1n98; r/w)

Bit Function

[15:0] DAC Data

Bits [15:0] allow to define a DC offset to be added the input signal in the -1.125V ÷ +1.125V range (low range) or in the -1V ÷ +8V range (high range), see also § 3.1.1. When Channel n Status bit 2 is set to 0, DC offset is updated (see § 4.7).

4.11. Channel n ADC Configuration (0x1n9C; r/w)

Bit Function

[31:0] Reserved

4.12. Channel Configuration (0x8000; r/w)

Bit Function

Allows to select Zero Suppression algorithm:

0000 = no zero suppression (default);

[19-16]

0001 = full suppression based on the integral

0010 = zero length encoding (ZLE);

0011 = full suppression based on the amplitude

0 = Analog monitor disabled [7]

1 = Analog monitor disabled

0 = Trigger Output on Input Over Threshold

1 = Trigger Output on Input Under Threshold [6]

allows to generate local trigger either on channel over or under

threshold (see § 4.3 and § 4.6)

0 = Memory Random Access [4]

1 = Memory Sequential Access

0 = Test Pattern Generation Disabled [3]

1 = Test Pattern Generation Enabled

0 = Trigger Overlapping Not Enabled [1]

1 = Trigger Overlapping Enabled

Allows to handle trigger overlap (see § 3.3.4)

0 = "Window" Gate [0]

1 = "Single Shot" Gate

Allows to handle samples validation (see § 3.3.1)

This register allows to perform settings which apply to all channels. It is possible to perform selective set/clear of the Channel Configuration register bits writing to 1 the corresponding set and clear bit at address 0x8004 (set) or 0x8008 (clear) see the following § 4.13 and § 4.14. Default value is 0x10.

(ZS INT);

(ZS AMP)

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4.13. Channel Configuration Bit Set (0x8004; w)

Bit Function

[7..0]

Bits set to 1 means that the corresponding bits in the Channel

Configuration register are set to 1.

4.14. Channel Configuration Bit Clear (0x8008; w)

Bit Function

[7..0]

Bits set to 1 means that the corresponding bits in the Channel

Configuration register are set to 0.

4.15. Buffer Organization (0x800C; r/w)

Bit Function

[3:0] BUFFER CODE

The BUFFER CODE allows to divide the available Output Buffer Memory into a certain number of

blocks, according to the following table:

Table 4.3: Output Buffer Memory block division

CODE Nr. of blocks Mem. Locations (max) Block_size Samples/block (max)

0000 1 262144 1024K 512K 0001 2 131072 512K 256K 0010 4 65536 256K 128K 0011 8 32768 128K 64K 0100 16 16384 64K 32K 0101 32 8192 32K 16K 0110 64 4096 16K 8K 0111 128 2048 8K 4K 1000 256 1024 4K 2K 1001 512 512 2K 1K 1010 1024 256 1K 512

A write access to this register causes a Software Clear, see § 3.9. This register must not be written while acquisition is running. The number of Memory Locations depends on Custom size register setting (see § 4.17)

4.16. Buffer Free (0x8010; r/w)

Bit Function

[11:0] N = Frees the first N Output Buffer Memory Blocks, see § 4.15

4.17. Custom Size (0x8020; r/w)

Bit Function

0= Custom Size disabled

[31:0]

(≠0) = Number of memory locations per event (1 location = 2

LOC

samples)

This register must not be written while acquisition is running.

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4.18. Acquisition Control (0x8100; r/w)

Bit Function

0 = Normal Mode (default): board becomes full, whenever all buffers

are full (see § 4.15) [5]

1 = Always keep one buffer free: board becomes full, whenever

N-1buffers are full; N = nr. of blocks (see § 4.15)

0 = DOWNSAMPLE DISABLED

1 = DOWNSAMPLE ENABLED [4]

allows to enable/disable downsampling, whose factor is set via

Downsample Factor register (see § 4.28)

0 = COUNT ACCEPTED TRIGGERS

1 = COUNT ALL TRIGGERS

[3]

allows to reject overlapping triggers (see § 3.3.4)

0 = Acquisition STOP [2]

1 = Acquisition RUN

allows to RUN/STOP Acquisition

00 = REGISTER-CONTROLLED RUN MODE

[1:0]

Bits [1:0] descritpion: 00 = REGISTER-CONTROLLED RUN MODE: multiboard synchronisation via S_IN front panel signal

− RUN control: start/stop via set/clear of bit[2]

− GATE always active (Continuous Gate Mode) or Downsample Mode

− Continuous Gate Mode can be used only if Channel gate mode (see § 4.12) is set in

− Downsample Mode can be used prior DOWNSAMPLE FACTOR register (see

01 = S-IN CONTROLLED RUN MODE: Multiboard synchronisation via S-IN front panel signal

− S-IN works both as SYNC and RUN_START command

− GATE always active (Continuous Gate Mode) or Downsample mode:

10 = S-IN GATE MODE

− Multiboard synchronisation is disabled

− S-IN works as Gate signal set/clear of RUN/STOP bit

11 = MULTI-BOARD SYNC MODE

− Used only for Multiboard synchronisation

01 = S-IN CONTROLLED RUN MODE

10 = S-IN GATE MODE

11 = MULTI-BOARD SYNC MODE

Window Mode

§ 4.28) valid setting (≠0)

− Continuous Gate Mode: Gate always active; to be used only if Channel Gate Mode (CHANNEL Configuration Register) is set to Window Mode

− Downsample Mode: it is set via DOWNSAMPLE ENABLE and a value ≠0 at DOWNSAMPLE FACTOR register

4.19. Acquisition Status (0x8104; r)

Bit Function

PLL Status Flag (see § 2.5.1): 0 = PLL loss of lock

[7]

1 = no PLL loss of lock NOTE: flag can be restored to 1 via read access to Status Register (see § 4.36) PLL Bypass mode (see § 2.5.1): 0 = No bypass mode

[6]

1 = Bypass mode

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Clock source (see § 2.6): 0 = Internal

[5]

1 = External EVENT FULL: it is set to 1 as the maximum nr. of events to be read

[4]

is reached EVENT READY: it is set to 1 as at least one event is available to

[3]

readout 0 = RUN off

[2]

1 = RUN on [1] reserved [0] reserved

4.20. Software Trigger (0x8108; w)

Bit Function

[31:0] A write access to this location generates a trigger via software

4.21. Trigger Source Enable Mask (0x810C; r/w)

Bit Function

0 = Software Trigger Disabled

[31]

1 = Software Trigger Enabled

0 = External Trigger Disabled

[30]

1 = External Trigger Enabled

0 = Channel 7 trigger disabled [7]

1 = Channel 7 trigger enabled

0 = Channel 6 trigger disabled [6]

1 = Channel 6 trigger enabled

0 = Channel 5 trigger disabled [5]

1 = Channel 5 trigger enabled

0 = Channel 4 trigger disabled [4]

1 = Channel 4 trigger enabled

0 = Channel 3 trigger disabled [3]

1 = Channel 3 trigger enabled

0 = Channel 2 trigger disabled [2]

1 = Channel 2 trigger enabled

0 = Channel 1 trigger disabled [1]

1 = Channel 1 trigger enabled

0 = Channel 0 trigger disabled [0]

1 = Channel 0 trigger enabled

This register bits[0,7] enable the channels to generate a local trigger as the digitised signal exceeds the Vth threshold (see § 3.5.3). Bit0 enables Ch0 to generate the trigger, bit1 enables Ch1 to generate the trigger and so on. EXTERNAL TRIGGER ENABLE (bit30) enables the board to sense TRG-IN signals SW TRIGGER ENABLE (bit 31) enables the board to sense software trigger (see § 4.20).

4.22. Front Panel Trigger Out Enable Mask (0x8110; r/w)

Bit Function

0 = Software Trigger Disabled

[31]

1 = Software Trigger Enabled

0 = External Trigger Disabled

[30]

1 = External Trigger Enabled

0 = Channel 7 trigger disabled [7]

1 = Channel 7 trigger enabled [6] 0 = Channel 6 trigger disabled

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Bit Function

1 = Channel 6 trigger enabled

0 = Channel 5 trigger disabled [5]

1 = Channel 5 trigger enabled

0 = Channel 4 trigger disabled [4]

1 = Channel 4 trigger enabled

0 = Channel 3 trigger disabled [3]

1 = Channel 3 trigger enabled

0 = Channel 2 trigger disabled [2]

1 = Channel 2 trigger enabled

0 = Channel 1 trigger disabled [1]

1 = Channel 1 trigger enabled

0 = Channel 0 trigger disabled [0]

1 = Channel 0 trigger enabled

This register bits[0,7] enable the channels to generate a TRG_OUT front panel signal as the digitised signal exceeds the Vth threshold (see § 3.5.3). Bit0 enables Ch0 to generate the TRG_OUT, bit1 enables Ch1 to generate the TRG_OUT and so on. EXTERNAL TRIGGER ENABLE (bit30) enables the board to generate the TRG_OUT SW TRIGGER ENABLE (bit 31) enables the board to generate TRG_OUT (see § 4.20).

4.23. Post Trigger Setting (0x8114; r/w)

Bit Function

[31:0] Post trigger value

The number written in this register corresponds to Nsamples*2+Offset (t.b.d.), with Nsamples = number of post-trigger samples.

4.24. Front Panel I/O Data (0x8118; r/w)

Bit Function

[15:0] Front Panel I/O Data

Allows to Readout the logic level of LVDS I/Os and set the logic level of LVDS Outputs.

4.25. Front Panel I/O Control (0x811C; r/w)

Bit Function

0 = I/O Normal operations

[15]

1= I/O Test Mode

[14] 1=TRIGGER OUT Value set to test mode

00 = General Purpose I/O

[7:6]

01 = Programmed I/O

10 = Pattern mode: LVDS signals are input and their value is written

into header TTT field (see § 3.3.5)

0 = LVDS I/O 15..12 are inputs [5]

1 = LVDS I/O 15..12 are outputs

0 = LVDS I/O 11..8 are inputs [4]

1 = LVDS I/O 11..8 are outputs

0 = LVDS I/O 7..4 are inputs [3]

1 = LVDS I/O 7..4 are outputs

0 = LVDS I/O 3..0 are inputs [2]

1 = LVDS I/O 3..0 are outputs

0= panel output signals (TRG-OUT/CLKOUT) enabled

1= panel output signals (TRG-OUT/CLKOUT) enabled in high

[1]

impedance

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Bit Function

0 = TRG/CLK are NIM I/O Levels [0]

1 = TRG/CLK are TTL I/O Levels

4.26. Channel Enable Mask (0x8120; r/w)

Bit Function

0 = Channel 7 disabled

[7]

1 = Channel 7 enabled 0 = Channel 6 disabled

[6]

1 = Channel 6 enabled 0 = Channel 5 disabled

[5]

1 = Channel 5 enabled 0 = Channel 4 disabled

[4]

1 = Channel 4 enabled 0 = Channel 3 disabled

[3]

1 = Channel 3 enabled 0 = Channel 2 disabled

[2]

1 = Channel 2 enabled 0 = Channel 1 disabled

[1]

1 = Channel 1 enabled 0 = Channel 0 disabled

[0]

1 = Channel 0 enabled

Enabled channels provide the samples which are stored into the events (and not erased). The mask cannot be changed while acquisition is running.

4.27. ROC FPGA Firmware Revision (0x8124; r)

Bit Function

[31:16] Revision date in Y/M/DD format

[15:8] Firmware Revision (X)

[7:0] Firmware Revision (Y)

Bits [31:16] contain the Revision date in Y/M/DD format. Bits [15:0] contain the firmware revision number coded on 16 bit (X.Y format).

4.28. Downsample Factor (0x8128; r/w)

Bit Function

This register allows to set N: sampling frequency will be divided by

[31:0]

N+1.

Downsampling is enabled via Acquisition Control register; see § 4.17

4.29. Event Stored (0x812C; r)

Bit Function

[31:0]

This register value cannot exceed the maximum number of available buffers according to setting of buffer size register.

This register contains the number of events currently stored in the

Output Buffer

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4.30. Set Monitor DAC (0x8138; r/w)

Bit Function

[11:0] This register allows to set the DAC value (12bit)

This register allows to set the DAC value in Voltage level mode (see § 2.7). LSB = 0.244 mV, terminated on 50 Ohm.

4.31. Board Info (0x8140; r)

Bit Function

[15:8] Memory size (Mbyte/channel)

[7:0]

Board Type:

0 = V1724

4.32. Monitor Mode (0x8144; r/w)

Bit Function

This register allows to encode the Analog Monitor (see § 3.7) operation: 000 = Trigger Majority Mode

[2:0]

001 = Test Mode 010 = Analog Monitor/Inspection Mode 011 = Buffer Occupancy Mode 100 = Voltage Level Mode

4.33. Event Size (0x814C; r)

Bit Function

[31:0] Nr. of 32 bit words in the next event

4.34. Analog Monitor (0x8150; r/w)

Bit Function

Magnify factor: 00 = 1x

[21,20]

[19] Offset sign (0=positive; 1=negative)

[18:8] Offset Value

01 = 2x 10 = 4x 11 = 8x

0 = Channel 7 disabled

[7]

1 = Channel 7 enabled 0 = Channel 6 disabled

[6]

1 = Channel 6 enabled 0 = Channel 5 disabled

[5]

1 = Channel 5 enabled 0 = Channel 4 disabled

[4]

1 = Channel 4 enabled 0 = Channel 3 disabled

[3]

1 = Channel 3 enabled 0 = Channel 2 disabled

[2]

1 = Channel 2 enabled 0 = Channel 1 disabled

[1]

1 = Channel 1 enabled

[0] 0 = Channel 0 disabled

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1 = Channel 0 enabled

4.35. VME Control (0xEF00; r/w)

Bit Function

0 = RELOC Disabled (BA is selected via Rotary Switch; see § 2.6)

[6]

1 = RELOC Enabled (BA is selected via RELOC register; see § 4.39) 0 = ALIGN64 Disabled

[5]

1 = ALIGN64 Enabled (see § 3.12.1.2) 0 = BERR Not Enabled; the module does not send a Bus Error as the last datum is readout, when aligned data readout is enabled , see

§3.12.1

[4]

1 = BERR Enabled; the module is enabled either to generate a Bus error to finish a block transfer or during the empty buffer read out in D32 0 = Optical Link interrupt disabled

[3]

1 = Optical Link interrupt enabled

[2 :0] Interrupt level (0= interrupt disabled)

4.36. VME Status (0xEF04; r)

Bit Function

0 = BERR FLAG: no Bus Error has occurred [2]

1 = BERR FLAG: a Bus Error has occurred (this bit is re-set after a

status register read out) [1] Reserved

0 = No Data Ready; [0]

1 = Event Ready

4.37. Board ID (0xEF08; r/w)

Bit Function

[4 :0] GEO

− VME64X versions: this register can be accessed in read mode only and contains the GEO address of the module picked from the backplane connectors; when CBLT is performed, the GEO address will be contained in the EVENT HEADER Board ID field (see § 3.3.5).

− Other versions: this register can be accessed both in read and write mode; it allows to write the correct GEO address (default setting = 0) of the module before CBLT operation. GEO address will be contained in the EVENT HEADER Board ID field (see § 3.3.5)

4.38. MCST Base Address and Control (0xEF0C; r/w)

Bit Function

These bits contain the most significant bits of the MCST/CBLT

[7:0]

[9:8]

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address of the module set via VME, i.e. the address used in MCST/CBLT operations. Allows to set up the board for daisy chaining: 00 = disabled board 01 = last board 10 = first board

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11 = intermediate

4.39. Relocation Address (0xEF10; r/w)

Bit Function

These bits contains the A31...A16 bits of the address of the module:

[15..0]

it can be set via VME for a relocation of the Base Address of the module.

4.40. Interrupt Status ID (0xEF14; r/w)

Bit Function

[31..0]

This register contains the STATUS/ID that the module places on the VME data bus during the Interrupt Acknowledge cycle

4.41. Interrupt Event Number (0xEF18; r/w)

Bit Function

[9..0] INTERRUPT EVENT NUMBER

If interrupts are enabled, the module generates a request whenever it has stored in memory a Number of events > INTERRUPT EVENT NUMBER

4.42. BLT Event Number (0xEF1C; r/w)

Bit Function

[7:0]

This register contains the number of complete events which has to be transferred via BLT/CBLT (see § 3.12.1.2).

4.43. Scratch (0xEF20; r/w)

Bit Function

[31:0] Scratch (to be used to write/read words for VME test purposes)

4.44. Software Reset (0xEF24; w)

Bit Function

[31:0] A write access to this location allows to perform a software reset

4.45. Software Clear (0xEF28; w)

Bit Function

[31:0] A write access to this location clears all the memories

4.46. Flash Enable (0xEF2C; r/w)

Bit Function

0 0 = Flash write ENABLED

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1 = Flash write DISABLED

This register is handled by the Firmware upgrade tool.

4.47. Flash Data (0xEF30; r/w)

Bit Function

[7:0] Data to be serialized towards the SPI On board Flash

This register is handled by the Firmware upgrade tool.

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5. Installation

− The Mod. V1724 fits into all 6U VME crates.

− VX1724 versions require VME64X compliant crates

− Turn the crate OFF before board insertion/removal

− Remove all cables connected to the front panel before board insertion/removal

CAUTION

ALL CABLES MUST BE REMOVED FROM THE FRONT PANEL

BEFORE EXTRACTING THE BOARD FROM THE CRATE!

5.1. Power ON sequence

To power ON the board follow this procedure:

1. insert the V1724 board into the crate

2. power up the crate

5.2. Power ON status

At power ON the module is in the following status:

• the Output Buffer is cleared;

• registers are set to their default configuration (see § 4)

5.3. Firmware upgrade

The board can store two firmware versions, called STD and BKP respectively; at Power On, a microcontroller reads the Flash Memory and programs the module with the firmware version selected via the JP2 jumper (see § 2.6), which can be placed either on the STD position (left), or in the BKP position (right). It is possible to upgrade the board firmware via VME, by writing the Flash; for this purpose, download the software package available at:

http://www.caen.it/nuclear/product.php?mod=V1724

The package includes the new firmware release file:

• v1724_rN_revX.Y_W.Z..rbf

and the V1724 firmware upgrade tool:

• CAENDigitizerUpgrade.exe (windows executable)

• CAENDigitizerUpgrade tool (source code and VC++ project)

For upgrading the firmware, utilizing CAENDigitizerUpgrade.exe, open a DOS shell, then launch

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CAENDigitizerUpgrade FileName BaseAdd [image] [/fast] [/nover]

where:

 FileName is the RBF file  BaseAdd is the Base Address (Hex 32 bit) of the V1724  image is '/standard' (default) or '/backup'  '/fast' enables fast programming (MultiRead/Write with CAEN Bridge)'  '/nover' disables programming check

N.B.: it is strongly suggested to upgrade ONLY one of the stored firmware revisions (generally the STD one): if both revision are simultaneously updated, and a failure occurs, it will not be possible to upload the firmware via VME again!

IMPORTANT NOTE: all modules featuring PCB Rev.0 do not support firmware release v1724_rN_revX1.2_0.4.rbf and later. PCB revision (Revision Field) can be read at Configuration ROM (see § 4.2). Contact support.nuclear@caen.it

in order to

upgrade firmware of modules featuring PCB Rev.0.

5.3.1. V1724 Upgrade files description

The board hosts one FPGA on the mainboard and one FPGA for each of the eight channels. The channel FPGAs firmware is identical. A unique file is provided that will updated all the FPGA at the same time.

ROC FPGA MAINBOARD FPGA (Readout Controller + VME interface)

There is one FPGA Altera Cyclone EP1C20.

AMC FPGA CHANNEL FPGA (ADC readout/Memory Controller):

There is one FPGA Altera Cyclone EP1C4

(EP1C20 in V1724E/VX1724E/V1724F/VX1724F version).

All FPGAs can be upgraded via VMEBUS;

CAENDigitizerUpgrade utility program must be used for this purpose.

The programming file has the extension RBF and its name follows this general scheme:

v1724_rN_revX.Y_W.Z.RBF

where:

• N is the mainboard board PCB revision number. This information can be read:

• from the Configuration ROM (see User's Manual)

• from the silkscreen on the mainboard bottom side (BVV17240512AA Rev. 0

is an example of PCB revision number 0)

• X.Y is the major/minor revision number of the mainboard FPGA

• W.Z is the major/minor revision number of the channel FPGA

WARNING: you can restore the previous FW revision in case there is a failure when you run the upgrading program. There is a jumper on the mainboard that allows to select the "backup" copy of the firmware. You must upgrade all the FPGAs and keep the revisions

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aligned; it is not guaranteed that the latest revision of one FPGA is compatible with an older revision.

Upgrade examples:

1) Upgrade to Rev 1.0(main FPGA)/Rev 0.2 (channel FPGA) of the standard page of the

V1724:

CAENDigitizerUpgrade v1724_r1_rev1.0_0.2.rbf 32100000 /standard

2) Upgrade to Rev 1.0(main FPGA)/Rev 0.2 (channel FPGA) of the backup page of the

V1724:

CAENDigitizerUpgrade v1724_r1_rev1.0_0.2.rbf 32100000 /backup

3) Upgrade to Rev 1.0(main FPGA)/Rev 1.1 (channel FPGA) of the standard page of the

V1724:

CAENDigitizerUpgrade v1724_r1_rev1.0_1.1.rbf 32100000 /standard

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Caen V1724 Series, V1724B, V1724LC, V1724E, V1724C Technical Information Manual

Specifications and Main Features

Frequently Asked Questions

User Manual