Cadence POWER RAIL VERIFICATION, VOLTAGESTORM POWER, VoltageStorm Power Verification, VoltageStorm Power Rail Verification Datasheet
DATASHEET
VOLTAGESTORM POWER AND
POWER RAIL VERIFICATION
The complexities associated with today’s power-sensitive
designs increases the risk that IR drop will be a cause of silicon
failure. Design teams require comprehensive power and power
rail analysis solutions that can accurately validate on-chip
power delivery networks, from initial power planning through
final signoff prior to tapeout. Within the Cadence® Encounter®
digital IC design platform, VoltageStorm® power verification
helps you quickly validate and optimize your power networks
using both static and dynamic analysis approaches.
ENCOUNTER PLATFORM
To release innovative products in
narrow market windows, companies
need to focus precious engineering
resources on where they add the most
value—differentiating their designs.
The Cadence® Encounter® digital IC
design platform offers a full spectrum of
technologies for nanometer-scale SoC
design, helping both logic design www.
cadence.com/solutions/logic_design/
index.aspx and physical implementation
www.cadence.com/solutions/digital_
implementation/index.aspx teams
achieve high-quality silicon quickly.
As an integrated RTL-to-GDSII design
environment, the Encounter platform
provides a complete flow—from RTL
synthesis and test design through silicon
virtual prototyping and partitioning to
final timing and manufacturing closure.
It delivers the highest quality of silicon
(timing, area, and power with wires),
accurate verification, signal-integrity—
aware routing, and the latest yield and
low-power design capabilities that are
critical for advanced 65nm designs. With
Encounter technology, you can boost
your productivity, manage complexity,
and get your products to market
faster. Encounter platform products are
available in L, XL, and GXL offerings.
VOLTAGESTORM POWER
AND POWER RAIL
VERIFICATION
Delivering the accuracy, capacity,
and performance to handle the most
complex multi-million gate designs,
the VoltageStorm hierarchical solution
gives design teams the confidence
that IR (voltage) drop and power rail
electromigration are managed effectively.
VoltageStorm power verification has been
proven to validate IR drop and power
electromigration (EM) on thousands
of designs. Initially used as an IR drop
and power EM signoff solution prior to
tapeout, VoltageStorm technology has
evolved to become an integral component
of design creation, which requires early
and up-front power rail analysis to help
create robust power networks during
power planning. Employing parasitic
extraction that is manufacturing aware,
and using patented static and dynamic
algorithms, VoltageStorm technology
continues to deliver power estimation
and power rail analysis functionality and
automation that you can depend on to
both analyze and optimize your power
networks throughout the design flow.
BENEFITS
Static Power
DSPF
SPEF
TWF
SLEW SDC
TFC/
VCD
1
Dynamic Power
Instance-based
Static Current
cell
mA
cell
Instance-based
Dynamic Current
Waveform
DSPF
SPEF
TWF
SLEW SDC VCD
2
.lib
DEF
1. Optional VCD input used
to seed activity
2. VCD required for vector-based
analysis or to seed vectorless
analysis
PowerMeter PowerMeter
• Enables efficient creation of on-chip
power networks
− Power routing sizes
− De-coupling capacitance size and
location
• Minimizes risk of power-related silicon
failures
− Outputs comprehensive static and
dynamic IR drop reports
− Enables IR drop-aware timing and
SI noise analysis (requires Cadence
Encounter Timing System or CeltIC®
NDC)
• Optimizes low-power designs
− Reports on-chip power density
− Allows tradeoff between de-coupling
capacitance and leakage
− Validates power-switch sizes
and power-up time
− Verifies impact of power-up rush
current on surrounding logic
• Delivers an efficient, hierarchical
analysis solution
− Uses power grid views to maximize
accuracy, performance, and capacity
− Accurately models IP, custom digital,
analog, and mixed-signal blocks
Figure 1: Example VoltageStorm plots (from left to right: IR drop, current density, and recommended
de-coupling capacitance)
FEATURES
VoltageStorm power and power rail
verification provides a comprehensive
solution for power analysis and contains
the functionality to accurately address
the requirements associated with multiple
design styles, including SoC, low-power,
ASIC, and custom digital designs.
Employing a combination of static
and dynamic analysis approaches,
VoltageStorm solutions can be used for
power rail verification during the complete
physical design creation flow, from early
power planning through signoff prior to
tapeout. To enable this comprehensive
support, the VoltageStorm solution
contains the functionality to calculate
static and dynamic power consumption
plus the functionality to perform both
static and dynamic power rail analysis.
POWER-DRIVEN DESIGN
REQUIREMENTS
For design teams to manage power
consumption effectively, they must understand the source of the power, typically
either active power or leakage power.
For design teams to create robust power
networks, in addition to understanding
the details of power consumption, they
must understand how to optimize power
rail routing and sizes and the size and
location of power switches (low-power
designs) and de-coupling capacitors.
VoltageStorm technology contains all of
the functionality required to help you with
these power-driven design requirements.
POWERMETER POWER ESTIMATION
PowerMeter is the power estimation
functionality within the hierarchical,
cell-based VoltageStorm solution.
PowerMeter allows you to calculate static
power consumption and dynamic power
• Supported by major reference flows,
ASIC and IP vendors, and IDMs
− Recommended by TSMC 7.0
Reference Flow
− Recommended by Starc ZD 3.0 Flow
− Library power grid views available
directly from ARM and TSMC
www.c a den c e.c om
Figure 2: PowerMeter data flow and usage
VOLTA GEST ORM
2
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