Cadence PCB SIGNAL AND POWER INTEGRITY, PCB SIGNAL, POWER INTEGRITY Datasheet

DATASHEET

CADENCE PCB SIGNAL AND
POWER INTEGRITY

The Cadence integrated high-speed design and analysis
environment streamlines creation of high-speed interconnect
on digital printed circuit board (PCB) systems. A range of
capabilities—from simple to advanced—enable electrical
engineers to explore, optimize, and resolve issues related
to electrical performance at all stages of the design cycle.
By enabling a constraint-driven design flow, this unique
environment accelerates the time to first-pass design success
while reducing the overall cost of end products.

Cadence PCB SI and PI technologies
are available in the following
product offerings:

• Cadence Allegro PCB SI L, XL,

and GXL

• Cadence OrCAD® Signal Explorer

CADENCE PCB SIGNAL
AND POWER INTEGRITY

Cadence® PCB signal integrity (SI) and
power integrity (PI) technologies provide
a scalable, cost-effective pre- and post­layout system interconnect design and
analysis environment. They deliver
advanced analysis at the board and
system levels. Cadence PCB SI and PI
products integrate tightly with Cadence
PCB editors, Cadence Allegro
Router, Allegro Design Entry HDL, and
Allegro System Architect—enabling
end-to-end, constraint-driven,
high-speed PCB system design.

Cadence PCB SI addresses the design
challenges presented by increasing design
density, faster data throughput, and
shrinking product design schedules, by
enabling designers to deal with high­speed issues throughout the design pro­cess. This approach allows design teams

®

PCB

to eliminate time-consuming iterations at
the back-end of a design process. It also
lets them maximize electrical performance
while minimizing cost of the overall
product. In addition, topology exploration
with models representing manufacturing
tolerances allows engineers to improve
production yields.

Cadence PCB SI eliminates the need to
translate design databases to run simula­tions by providing a highly integrated
design and analysis environment.
Designers can also accurately address
shrinking timing budgets by considering
the effects of package design on the
overall performance of the signal from
die to die. The integrated flow is of great
value to the designers, who now can
easily perform pre- and post-layout
extraction and verification of complex
high-speed PCB systems.

KEY CAPABILITIES

Design implementation

Solution space
exploration

Power delivery
network strategy

Model development
and verification

Constraint-driven
place and route

Post-layout verification
of signal and power
integrity

Constraint-driven
floor planning

Specifications

Logic and

timing design

Optimal

constraints

Constraint-

driven physical

implementation

• Highlyintegrateddesignandanalysis

environment removes the need for
error-prone and time-consuming
design translation.

• Pre-routeanalysisdesignmethodology

streamlines post-route design verifica­tion through a consistent front-to-back
constraint management system.

• Powerstabilityanddeliveryare
optimized through DC and AC
power analysis.

• Seriallinkdesignmethodologyspeeds

the time to perform detailed million-bit
simulations using the latest industry­standard IBIS-AMI–compliant SerDes
models.

• Timingbudgetsofcomplexsource-

synchronous parallel interfaces can
be efficiently validated with optimized
bus analysis solution.

FEATURES

INTEGRATED HIGH-SPEED
DESIGN AND ANALYSIS

To eliminate the risk of design translation
issues, Allegro PCB SI is seamlessly inte­grated with the Allegro PCB Editor and
allows for constraints and models to be
embedded in the board design file. (See
Figure 1.) The integrated design and analy­sis system is aware of multi-net electrical
constructs from logical design authoring
to physical implementation. For example,
differential pairs and extended nets (nets
with a series termination) are recognized,
extracted, and simulated as one electrical
net from either schematic or layout. The
SigXplorer module integrates with logical
or physical design tools and provides a
graphical view of I/O buffers, transmission
lines, and vias such that complex topolo­gies can be modified in a what-if fashion—
without having to change the actual
design. SigXplorer also allows engineers to
sweep various parameters within the topol­ogy to identify a topology solution space,
which can then be captured in the con­straint management system and guide PCB
designers to first-pass electrical compliance.

Figure 1: No translation is required to analyze selected signals from the physical board or extract them into the
SigXplorer module. Analysis results are reported in the same constraint manager used by Allegro PCB Editor.
Coupled differential pairs and nets extended through discrete components (x-nets) are automatically identified,
analyzed, and/or extracted.

Figure 2: An Allegro PCB SI and PCB PI option allows engineers to explore and develop optimum constraints and
power decoupling strategies within a constraint-driven design flow.

CONSTRAINT-DRIVEN
DESIGN METHODOLOGY

Cadence PCB SI technology works seam­lessly with the constraint management
system of the Allegro PCB Design Suite.
Constraints derived through simulation
can be put into an Electrical Constraint Set
(EC Set) from within the topology canvass,
SigXplorer. These EC Sets can then be
applied to other nets in the design through
the constraint management system found
in Allegro PCB SI, Allegro Design Entry
HDL, and Allegro PCB Design. Designers
can use the constraints developed through
simulation and exploration and enable a
front- to back-end constraint-driven
design process. (See Figure 2.)

POWER INTEGRITY

Allegro PCB SI features both DC and AC
power integrity capabilities. Allegro PCB
SI includes static IR drop (DC) analysis
technology that verifies that the power
distribution system can provide sufficient
current to drive signals. The analysis
considers effects due to trace neck-down;
Swiss-cheese planes created by compo­nents with dense pin grid arrays; and
reduction of available copper caused by
trace routing on power and ground
planes. The analysis also takes into
account all vias that connect multiple
ground planes of the same net. Results
can be viewed in a graphical voltage drop

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CADENCE PCB SIGNAL AND POWER INTEGRITY

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