Cadence PALLADIUM XP - TECH BRIEF, PALLADIUM XP User Manual

TECHNICAL BRIEF

CADENCE PA L L A D I U M X P

VERIFICATION COMPUTING PLATFORM

Cadence® Palladium® XP is a state-of-the-art hardware/software
verification computing platform. It unifies best-in-class simulation
acceleration and emulation capabilities in a single environment to
boost verification throughput and productivity. Its processor-based
compute engine and Unified Xccelerator Emulator software runs high­performance verification applications and introduces flexible new
use models that transcend traditional emulation. With unmatched
scalability, advanced debug, hardware/software co-verification, and
support for dynamic power analysis, hard and soft IP, and metric­driven verification, Palladium XP optimizes system design and
verification.

SYSTEM-LEVEL VERIFICATION CHALLENGE

Traditional verification tools have not kept pace with the rapid
rate at which system-on-chip (SoC) design size and complexity
are growing. This widens the hardware/software (HW/SW)
verification gap, limiting reusability and productivity and
increasing the likelihood of re-spins and schedule delays.
Traditional software simulators are ideal for IP or small design
development and verification, and they can simulate cluster- to
chip-level designs. However, as RTL design size increases, these
simulators slow down significantly, which delays HW/SW
(system) integration and prolongs the overall verification cycle.

Figure 1: Palladium XP offers a unified high-performance
verification computing platform

As shown in Figure 2, today’s SoC designs contain one or more
micro-processors (uP), various types of memories, internal and
external encrypted IP, industry-standard I/Os, embedded software,
operating systems, drivers, and software applications that are
interdependent; therefore, both hardware and software must be
verified together.

As systems grow more complex, the risk associated with not
adequately verifying HW/SW interaction also grows. Scalable
performance is critical to eliminating these risks. Traditional
hardware-assisted verification tools are useful for improving
performance, but take you outside of your native simulation
environment with steep learning curves, lengthy setup times,
difficult debug methods, and reuse issues. Furthermore, there is no
easy way to swap among simulation, simulation acceleration, and
emulation environments without re-compilation.

Embedded Software

OS, Driver, Applications

FLASH DDR3 GDRAM

uP uP

uP uP

Graphics

Controller

10G/40G

Ethernet I/F

Memory

Controller

Switch

Scheduler

General Purpose I/O

Figure 2: An example SoC design that
includes hardware and software

Encrypted

IP

IP IP

Wireless

Controller

Architecture

Exploration

Algorithmic
Verification

Simulation

Block/IP

Verification

Chip-Level

Verification

Firmware

Verification

Software

Verification

EmulationSimulation Acceleration

Field

Prototype

Figure 3: Disparate tools and segregated environments for simulation, simulation acceleration, and emulation
create barriers to achieving scalable performance and IP reuse

SYSTEM-LEVEL VERIFICATION SOLUTION

To keep pace with the demands of advanced SoC development and to close the HW/SW verification gap,
Palladium XP offers the industry's most comprehensive verification platform. Palladium XP removes the
barrier to entry in acceleration and emulation by offering a unified environment that leverages the native
simulation environment and allows a Cadence Incisive simulator user to hot-swap among simulation,
simulation acceleration, and emulation environments at runtime without re-compilation. Palladium XP can
be used at various design and verification phases, from early architectural analysis and block-, chip-, and
system-level integration to software development and system verification.

Architecture

Exploration

Algorithmic
Verification

Block/IP

Verification

Chip-Level

Verification

Firmware

Verification

Software

Verification

Field

Prototype

Figure 4: Palladium XP removes barriers to scalable performance with a unified flow and allows users to easily
transition among simulation, simulation acceleration, and emulation

Furthermore, Palladium XP improves verification productivity by offering the fastest bring-up time, an
easy-to-use flow, flexible simulation-like use models, scalable performance, and fast and predictable
compile for the best turnaround time. It is designed to interface with real-world stimulus and enables
hot-swap into the simulation environment while providing early access to HW/SW co-verification and
advanced debug.

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Simulation

EmulationSimulation Acceleration

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Palladium XP offers enhancements above and beyond what traditional acceleration and emulation use
models offer. Palladium XP introduces new use models to improve verification productivity through
metric-driven verification acceleration, hardware verification language-based testbench acceleration,
Open Verification Methodology (OVM) acceleration, and system-level power verification.

Open Verification

Methodology for

Synthesizable

Testbench

Acceleration

STB

OVM

MDV

UXE

Unified Xccelerator

Vector-Based

Acceleration

Transaction-

Based

Acceleration

Assertion-Based

Acceleration

Figure 5: Palladium XP offers comprehensive use models for HW/SW
co-verification and system realization

VBA

TBA

ABA

Signal-Based

Acceleration

Emulator Software

Palladium XP

Hardware XL, GXL

SBA

PSO

Metric-Driven
Verification for

Acceleration

ICE

Debug

VIP

DPA

Power Shutoff
Verification

In-Circuit
Emulation

Advanced

Debug

Verification
Intellectual
Property

Dynamic Power
Analysis

PALLADIUM XP BENEFITS

• Highest scalability and flexibility

– Enables centralized or locally distributed verification computing with scalable resources to serve a

single user or as many as 512 simultaneous users for up to 2 billion gates capacity

– Supports flexible executable functional models at various abstraction levels (C/C++, SystemC®,

instruction set or cycle accurate, silicon, RTL, gates)

– Offers flexible use models and flexible resource allocation

• Unparalleled verification computing productivity

– Integrates seamlessly with the simulation environment for multi-user productivity

– Facilitates best turnaround time with efficient compile, runtime performance of up to 4MHz, and

simplified but superior at-speed and offline debug capabilities

– Reduces the learning curve with an easy-to-use flow, from simulation to acceleration to emulation, by

leveraging the existing simulation environment

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• Better design bring-up predictability

– Enables quick bring-up with its fast, automated, intelligent compiler that includes a rich set of

behavior construct support and congruent (match) behavior between simulation and hardware

– Boosts runtime predictability with “hot-swap” to acceleration or emulation and the most flexible

use models

– Enables quick system-level bring-up with comprehensive and proven Cadence SpeedBridge® portfolio

(comprising hardware rate adapters for external targets)

• Platform extension

– Supports metric-driven verification for acceleration with coverage and advancements in hardware

verification/hardware design languages

– Supports the most comprehensive hard or soft verification IP for standard protocols

– Enhances system-level low-power analysis with Dynamic Power Analysis option and power verification

techniques such as power shutoff

PALLADIUM XP FEATURES

COMPREHENSIVE VERIFICATION COMPUTING PLATFORM

The Palladium XP verification computing platform is state-of-the art for its advancements in hardware,
software (compilation, debug, runtime, flexibility), and use models. The Palladium XP compute engine
comprises an advanced custom processor grid. Each processor includes multi-million transistors embedded
in multi-chip modules (MCMs). This processor grid allows Palladium XP to support up to 2 billion ASIC
gates of design capacity, supporting a single user or up to 512 simultaneous users, and it runs up to
4MHz. Its unique architecture enables high-performance verification for both small and large designs.
Engineers can run their hardware and software verification tasks in parallel with cycle-accurate models
while effortlessly migrating from a simulation environment to an acceleration/emulation environment.

The Unified Xccelerator Emulator (UXE) software component of Palladium XP integrates simulation and
acceleration in a single environment, thereby enabling fast bring-up, superior debug, hot-swap capability,
and fast, fully automated, predictable design compile on a single workstation. It is designed to support a
large subset of behavioral RTL and enables efficient debug, thus increasing verification throughput and
flexibility. For ease-of-use, UXE software makes the first-time user experience very similar to that of the
simulation environment but with the speed of emulation.

FLEXIBLE RESOURCE ALLOCATION

Palladium XP offers verification computing resources with best-in class flexibility for an enterprise. It can
be utilized for multiple projects/tests as it can support multiple concurrent jobs—including those with a
mixture of acceleration and emulation—without affecting other jobs. Users can set up jobs queuing for
regression or interactive use and can relocate jobs to other available symmetrically configured resources
(MCMs, memories, I/Os) without re-compilation. Furthermore, users can respond to on-demand resource
allocation requirements as projects needs evolve. Palladium XP offers the flexibility to make tradeoffs
between maximizing runtime performance or maximizing capacity and the number of users.

FLEXIBLE MODEL SUPPORT

To assemble the SoC rapidly, at any given design phase, teams need to utilize the most accurate and
highest performing models available. Therefore, a highly flexible verification platform is critical. The
Palladium XP platform allows rapid integration of various abstracted IP models on the basis of perfor­mance, accuracy, availability, reuse, hard/soft IP, or legacy environment support requirements.

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An ideal platform must also be able to leverage system behavior during emulation or acceleration to

Wireless Adapter

Link and Compile

ensure models can be swapped in and out. To achieve these objectives, the platform must: (a) link to and
co-execute with a high-performance “software-based” model (i.e., untimed functional models), and (b)
link to and co-execute with a system-level interface and system-level components that are external (i.e.,
PCI Express or USB, program code running under diagnostic/firmware).

Wireless

Tester

Hot-Swap

Incisive Enterprise Simulator

SoC Design and

Memory IP

Ethernet SpeedBridge

Network

Traffic

Generator

Ethernet 10G/40G

Live Network

Connect

Figure 6: Palladium XP compiles/links to software models running on workstations and models compiled
in hardware, and connects to real-world applications such as wireless testers and 10/40G Ethernet

Palladium XP simplifies the creation of system-level modeling by allowing different abstracted models to
be compiled, linked, and operated upon. This unique capability enables users to rapidly create system­level models during the various design stages. By reusing models that are available in various abstracted
levels (such as C/C++, SystemC, transaction-level models (TLMs), RTL, gate-level, and silicon-based IP),
users can maximize reuse while balancing the need to verify the SoC model in a system-level context. In
addition, Palladium XP supports industry interface standards such as the Standard Co-Emulation Modeling
Interface (SCE-MI) or SystemVerilog DPI, which provides even more flexibility in expanding the system­level verification environment.

Since Palladium XP supports concurrent use of different types of IP, testers, debuggers, and test stimulus
generators, it significantly reduces the development schedule. Users can comprehensively verify system
interactions with a real-world environment and/or a testbench for a directed, constrained-random, or
metric-driven verification environment while significantly improving verification throughput.

Multi-Language

Testbench

Verification IP

Portfolio

Memory IP

Portfolio

Third-Party

Testers

Emulation

Figure 7: Palladium XP allows concurrent use of different types of models

SpeedBridge

Rate Adapters

Simulation/Simulation
Acceleration

Third-Party Processor
Models and Software
Debuggers

Hardware/Software
Debug

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