Cadence LITHO PHYSICAL ANALYZER, Litho Physical Analyze Datasheet

DATASHEET

CADENCE LITHO
PHYSICAL ANALYZER

Full-Chip, Model-Based Design Manufacturability Checking
and Contour Shape Prediction

A comprehensive model-based design manufacturability
checker, Cadence® Litho Physical Analyzer detects
manufacturability issues missed by traditional DRC check
in a fraction of the time required by solutions based
on OPC and lithography simulation. Silicon-proven and
foundry-endorsed, it quickly and accurately accounts for
systematic manufacturing variations on all critical layers,
helping designers improve yield during physical design
implementation.

CADENCE LITHO
PHYSICAL ANALYZER

At 65 nanometers and below, lithography,
etch, and mask systematic manufacturing
variations surpass random variations as
the prime limiters to catastrophic and
parametric yield loss. The interaction
of manufacturing shapes within the
optical proximity halo and the spatially
partially-coherent lithography projection
systems creates highly non-linear
systematic variations at different process
conditions that cannot be captured
by rules or pattern matching. These
systematic shape variations, dependent
on specific layout shape context, result
in predictable catastrophic errors such
as necking (opens) and bridging (shorts).
Furthermore, the litho-induced systematic
shape variations of interconnect and gate
have a non-linear impact on electrical
parameters such as timing, leakage
power, and signal integrity.

Figure 1: Cadence Litho Physical Analyzer use model

Cadence Litho Physical Analyzer helps
designers solve these systematic design­for-manufacturing (DFM) challenges.
It is a full-chip, model-based design
manufacturability checker that designers
can use to detect lithography hotspots
based on fast and accurate silicon contour
prediction across the process window. It
creates fixing guidelines to help designers
or design tools correct these hotspots.
These predicted silicon contours can be
used for further electrical DFM analysis
with Cadence Litho Electrical Analyzer,
enabling designers to improve parametric
yield and chip performance by accurately
determining the impact of systematic
manufacturing variations during design.

BENEFITS

• Detects yield-limiting variability
hotspots based on foundry-certified
technology files

• Helps designers improve printability and
yield with fixing guidelines

• Checks cells in seconds / full chips in
hours with proprietary formulation that
allows fast and accurate silicon contour
prediction across the process window

• Integrates with most commonly used
design flows

• Offers fast runtimes and a
designer-friendly use model

• Compatible with existing design farms
for easy adoption by design teams

• Integrates with Cadence Litho
Electrical Analyzer

FEATURES

MODEL-BASED MANUFACTURING
SHAPE PREDICTION

Traditional approaches to deal with
manufacturing variations are no longer
adequate. Design rule checking (DRC)
alone does not prevent catastrophic yield
loss due to systematic shape variations;
additionally, DRC rules to address growing
DFM issues become prohibitive in number
and complexity. Post-GDSII OPC uncovers
printability problems that frequently

Figure 2: Litho Physical Analyzer hotspot browser Layout Editor

require actual design changes when there
is limited freedom after tapeout, making
design closure unpredictable. Running
post-GDSII OPC tools during layout is not
feasible, because it takes days for every
layer to run a typical design through OPC.

Designers can restrict their design style
in an attempt to improve yield, but
this method limits the use of leading­edge processes that optimize area
and performance. Only model-based
predictive approaches (that are not based
on moving post-GDSII OPC tools to the
designer’s desk) are fast enough to let
designers uncover hotspots during design
implementation and make real-time
design adjustments to eliminate them.

Cadence Litho Physical Analyzer is a
full-chip, model-based design manufac­turability checker—silicon-proven and
endorsed by all major foundry platforms—
that designers can use to find and fix
hotspots and predict contours across
process conditions. It uses a patent­pending, model-based, non-linear optical
transformation algorithm that allows
designers to quickly and accurately detect

potential manufacturing failures during
physical design that would otherwise be
found after tapeout in mask or silicon.
The compact models encapsulate all
necessary RET, OPC, mask, etch, and
lithography effects on both device and
interconnect, and predict accurate
contours for the entire chip from drawn
layout in a matter of hours. Cadence
Litho Physical Analyzer is typically an
order of magnitude faster than other
model-based tools.

SOPHISTICATED HOTSPOT
DETECTION AND CORRECTION
GUIDELINES

Litho Physical Analyzer identifies hotspots
based on fab-designated criteria or litho
yield sensitivity (LYS) metrics. It sorts
hotpots by type and criticality, and pre­checked blocks can be excluded by name,
area, or marker layer. The non-linear
optical transformation algorithm also
allows generation of automatic fixing
guidelines that are input into the user’s
choice of physical design tools, such as
Cadence Virtuoso® Layout Suite and

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