Cadence INCISIVE PALLADIUM III DYNAMIC POWER ANALYSIS, Incisive Palladium Dynamic Power Analysis Datasheet

DATASHEET

INCISIVE PALLADIUM III
DYNAMIC POWER ANALYSIS

Cadence® Incisive® Palladium® Dynamic Power Analysis (DPA)
enables System on Chip (SoC) designers to intelligently
identify, capture, and analyze power switching activity for
peak and average power analysis. The DPA solution uniquely
enables engineers using Palladium III for emulation to also
analyze software within the system-level SoC architecture,
and perform trade-offs between power and performance
in a realistic system-level environment.

SYSTEM-LEVEL DYNAMIC
POWER ANALYSIS

Palladium Dynamic Power Analysis offers
“What-if” analysis of power consumption
based on logic switching activities, with
respect to different architecture variations,
design implementations, or application
scenarios. It allows users to select course­grained analysis over millions of design
cycles to generate a power profi le, or
chose fi ne-grained analysis to increase
accuracy for examining power peaks.

At the system-level, the solution’s ability
to run various design or implemen­tation scenarios--and determine their
impact on power dissipation under a
realistic application environment—is vital
to striking a balance between power
budget and expected performance.

While the Palladium system
has traditionally been used for
high-performance functional verifi cation,
the new DPA solution extends its
emulation computation by generating

Cell.lib (Tech)

Memory.lib

Macro.lib

RTL/Gates

Optional

Design/Power

Constraints

Power
Estimation

DPA Engine

DPA Processing and Filtering GUI

• View peak and average power consumption

• Instance-based power navigation

• Data processing and filtering through

Figure1: Palladium Dynamic Power Analysis user fl ow

Analysis

• Power profile and signal
view in one window

• Analysis based on instance and
signal information in SimVision

dynamic power profi les at the
system-level. DPA allows system-level
engineers to analyze deep sequences
for system-level scenarios typically not
practical in a pure software simulation
environment.

Additionally, Palladium Dynamic
Power Analysis delivers offl ine power
calculation by capturing the necessary
power activities in a common DPA power
database. This capability further enables
the sharing of verifi cation resources
while DPA is computing the power
profi le offl ine.

POWER ANALYSIS FLOW

Palladium Dynamic Power Analysis
users input RTL or Gate level netlist,
along with technology library, memory
and macro libraries. The solution also
gives them the ability to generate the
power profi le for a given test. The DPA
processing and fi ltering GUI can be used
for identifying a window of interest for
further detailed analysis.

BENEFITS

• Enables system-level power estimation

– Higher-performance engine

– Identify peaks

– Calculate average over long run

• Realistic environment reduces risk

– Run in-circuit in real environment,

full chip or system-level

– Run with embedded software

– Estimates power under real

operating conditions

• Detailed analysis on identifi ed windows

– Identifi es where detailed analysis

is needed

– Enables software and/or RTL

optimization to reduce power

• Enables relative compare of IP at
RTL phase

– Identify architectural issues

– Enables hardware/software

architectural trade-offs

• Reduces risk and packaging cost

– Adequately select package

– Avoid re-spins/lost opportunities

FEATURES

• Peak identifi cation

– Identifi es top N (numbers of) peaks.

Each peak is identifi ed by an instance
name and time

• Average power calculation

– Calculates realistic average power

based on long simulation runs

• Supports both RTL and gate-level
power estimation

– RTL based power estimation can be

used for relative IP comparison

– Gate-level power estimation can be

used for more accurate analysis

• Weighted toggle count

– Weights can be assigned to scale

the power consumptions in different
elements to the toggle activities.
For example, embedded memories
consume more power than standard
cells for the same number of I/O
transitions. Therefore, memories get
assigned a higher weight compared
to standard cells. This enables more
realistic representation of a dynamic
power profi le.

• Toggle Count Analysis (TCA) GUI

– Enhancements to Palladium Debug

GUI for Toggle Count Analysis
include various data processing
and fi ltering capabilities

• Data processing:

– Ability to process data in

various ways such as toggle
count, high count, time average
and peak values

• Filtering:

– Interval Average: This fi lter will

split raw data into intervals of
the same size. (Helps reduce the
number of windows)

– Running Average: This fi lter

calculates an average number for
the selected window. (Helps with
a smoother waveform)

• Supports the Common Power
Format (CPF)

– Allows user to specify advanced

power reduction techniques such
as power shutofff

• Leverages SimVision for comprehensive
analysis

– Histogram and fi ltered data can

be viewed along with instance
and signals

SPECIFICATIONS

• Requires Palladium III hardware

• Palladium III supported OS and
Workstations

– Solaris (32-bit, 64-bit)

– Linux (32-bit, 64-bit)

• Includes capabilities of SimVision

• Leverages RTL Compiler technology for
power estimation

• User needs to provide technology,
memory, and macro libraries for
Weighted Toggle Count and Power
Profi le generation

www.cadence.com

INCISIVE PALLADIUM III DYNAMIC POWER ANALYSIS

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