Cadence INCISIVE ENTERPRISE SPECMAN PRODUCTS, Incisive Enterprise Specman ESL Testbench, Incisive Enterprise Specman Elite Testbench Datasheet

DATASHEET

Plan-to-Closure
Methodology

Verification Environment

Interface Specification and
Functional Testbench

Legacy Code (C, HDL)
Verification Environment
Reference Models and Tests

vPlan
Executable
Specification

Planning and
Management

Planning and Management GUI-Based Test Creation Static Analysis and

Methodology Enforcement

Incisive
Acceleration
and Emulation

High-Throughput
Connection to
Acceleration
and Emulation

Include
Embedded
Software in the
Simulation

HDLs Assertions CPF spec. C, C++,

SystemC

Embedded
Software

Multi-Language
Automation
and Reuse

Assertion­Based
Verification

Full
System
Verification

Plan- and
Metric-Driven
Closure

Methodology
Libraries

Verification Builder Scenario Builder

TBA Specman

ESL Testbench

Incisive
Software
Extensions

Device Under Test

eAnalyzer

Incisive Enterprise Specman Elite Testbench

Constraint-Driven Test Generation

Functional Coverage Analysis

Single-Run Data and Assertion Checking

INCISIVE ENTERPRISE
SPECMAN PRODUCTS

Part of the Cadence® Incisive® functional verification platform,
Incisive Enterprise Specman products blend leading-edge
process automation technology with the comprehensive
Plan-to-Closure Methodology to simplify and speed verification.
Specman® products automate the entire verification process,
from individual blocks to full chips to the project level. With
Specman technology, designers benefit from increased
productivity and a predictable path to high-quality silicon.

Figure 1: Incisive Enterprise Specman Elite Testbench helps drive the entire process of verification at block, chip,
system, and project levels. The Verification Builder, Scenario Builder, and eAnalzyer components automate the
creation and configuration of reusable, scalable, eRM-compliant environments and stimuli. The Specman ESL
option offers a high-throughput channel between the testbench and the DUT, and enables access to embedded
software as if it were another part of the DUT.

INCISIVE ENTERPRISE
SPECMAN ELITE
TESTBENCH

Successful verification of today’s multimillion­gate designs requires optimal speed and
efficiency. But verification teams often
struggle to squeeze in enough cycles to
ensure that functional bugs won’t surface
in silicon. Incisive Enterprise Specman Elite®
Testbench is a comprehensive environment
that accelerates and simplifies all aspects
of verification (automatic generation of
functional tests, data and assertion
checking, and functional coverage analysis)
in addition to supporting the production­proven Plan-to-Closure Methodology.

Verification teams can extend the
functionality of Specman technology with
Incisive Enterprise Specman ESL Testbench
(Specman ESL), which provides a high­throughput channel between the testbench
and the device under test (DUT), and enables
Plan-to-Closure verification automation
of embedded software exactly as if it
were another part of the DUT. With other
elements from the Incisive platform,
including verification IP, hardware accelera­tion and emulation, analog/mixed-signal/RF
verification, and formal assertion verification,
Specman products support any testbench,
HDL, software, or assertion IP.

Many engineers already create testbenches
in C, VHDL, Verilog®, and SystemVeriog,
and may have invested time and effort in
internal solutions. But, realistically, these
tools are rewritten project to project
without allowing for significant reuse.
Nor do they contain the engines and
aspect-oriented programming (AOP)
support already built into Specman products,
such as the patented constraint solver
that generates stimulus automatically.

With Specman products, engineers can
use the powerful e verification language
to capture rules from executable
specifications and use the information
to automate verification. The Specman
methodology finds even the most subtle,
corner-case bugs because it eliminates
misrepresentations of specifications.

Figure 2: Specman “IntelliGen” technology simultaneously increases performance, scalability, and control over
stimuli. The Generation Debugger (shown above) confirms that constraints are set to drive Specman toward
suspected corner cases.

BENEFITS

• Captures executable specifications and
eliminates misrepresentations

• Leverages the
AOP capabilities

• “IntelliGen” constraint solvers automate
test generation with up to 5x faster
runtime, unprecenteded distribution
control, and scalability

• Speeds debugging via automatic data
and assertion checking

• Increases predictability with functional
coverage analysis

• Supports all IEEE-standard languages
including e, SystemC®, C, C++, VHDL,
Verilog, and SystemVerilog

• Supports built-in IP reuse to leverage
existing investments in verification IP

• Works with all major simulators

e language’s unique

FEATURES

CONSTRAINT-DRIVEN
STIMULUS GENERATION

Specman products provide constraint-driven
test generation that automates the process
of generating functional verification tests.
By specifying constraints, engineers can
target the generator quickly and easily
to create any test in their functional
test plan. They can even generate tests
on-the-fly based on the current design
state, making it possible to detect
hard-to-reach corner cases.

DATA AND ASSERTION CHECKING

Powerful temporal constructs allow
verification specialists and designers to
capture complex protocols for assertion
checking. On-the-fly data checking and
generation provides context-specific
expected values. With Specman products,
verification engineers can use any
combination of gray-, black-, or white-box
checking to speed debugging.

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FUNCTIONAL COVERAGE ANALYSIS

An executable functional test plan
measures the progress of verification,
and functional analysis automatically
identifies holes in the test coverage.
Since functional coverage is a meaningful
and direct measure of the completeness
of verification, functional coverage
analysis increases predictability in
verification schedules.

RAPID CREATION OF LIBRARIES
OF REUSABLE TESTS

Specman products fully support the
testbench reuse component of the
Plan-to-Closure Methodology, which
describes how to create reusable verification
components in any IEEE-standard language,
and provides guidelines for setting up
multi-language interfaces to existing IP
for maximum operational flexibility.
The process is based on the time-tested
e Reuse Methodology (eRM) and System
Verification Methodology (SVM).

With the Specman Verification Builder
component, users can quickly create
and configure reusable verification
components in
Verification Builder also supports plug-ins
that help users automatically connect the
DUT to the testbench. A similar plug-in
for the Specman ESL option (see below)
supports rapid binding of the testbench
to the processor model(s).

The Specman Scenario Builder component
helps designers create test cases in a
fraction of the time it would take to write
them in a hardware verification language,
eliminating the need to learn a verification
language and object-oriented programming.
Users simply drag-and-drop randomized
verification elements and adjust their
constraints to build a scenario. Scenario
Builder makes it just as easy to build
complex system-level test cases: users
define stimuli for each interface that
can be synchronized on existing or
user-defined events.

When combined with the “sequence”
feature of the Plan-to-Closure Methodology,
stimuli that exercise corner-case scenarios at
the block level can be reused at the system

eRM-compliant format.

level to verify how the entire chip behaves
in that corner case. Furthermore, users
can graphically create these sequences
as easily as test cases, which they can use
in other tests hierarchically or in other
sequences by dragging and dropping in
a new scenario. All scenarios are written
out into a reusable format, supporting
the creation of portable libraries of
protocol checkers and other structured
behaviors for reuse on future projects,
or system-level verification of the
same project.

TESTBENCH STATIC ANALYSIS

Static analysis catches testbench bugs and
coding surprises early in the verification
cycle. It performs more than 200 checks
to flag syntactic, semantic, and functional
errors. A flow that includes testbench
analysis before simulation will check the
code for reusability per eRM-compliance
rules, testbench performance issues, race
conditions, pre-defined coding style rules,
generation constraints, and semantic
ambiguities. These rules can be expanded
to include corporate style guidelines. The
result: with the powerful rule-definition
GUIs and graphical analysis tools,
engineers write working code correctly
the first time.

HDL SIMULATOR INTERFACES

Specman products integrate with all
leading HDL simulators and support a
high-performance, direct kernel interface
to all Incisive simulators. Users can sample
and drive internal signals of the DUT. With
100% controllability and observability of
otherwise inaccessible internal signals, all
Specman engines have full access to signal
values during simulation.

TRANSACTION-LEVEL MODELING
AND SYSTEMC SUPPORT

Specman products provide SystemC
interface mechanisms to drive and
monitor transaction-level models (TLMs)
as well as signal-level models. You can
apply Specman verification methodologies
to the verification of SystemC architectural
models using TLMs and reference

models including mixed SystemC/RTL
environments, and co-verify SystemC
models used for software development.

In addition to supporting Incisive simulators,
Specman products provide interface
adaptors for SystemC simulators including
OSCI® and CoWare ConvergenSC. With
Specman technology, engineers can
create a single verification environment
to verify their SystemC model and then
reuse it throughout the entire downstream
flow, from RTL simulation to acceleration
and emulation.

HW/SW CO-VERIFICATION

Specman products support all leading
hardware/software co-verification tools.
They also integrate seamlessly with Incisive
Software Extensions (“ISX”) in the Specman
ESL co-verification environment to enable
functional testing of both hardware and
software. Early integration and debugging
of HW/SW systems eliminates errors
and shortens time to market for the
combined system.

PLAN-TO-CLOSURE
METHODOLOGY

The Plan-to-Closure Methodology provides a
system of best-known principles, guidelines,
and procedures that increase project
productivity and predictability, and ensure
overall system-level quality. It includes
documented best practices, golden
examples that serve as templates to help
engineers learn and apply the methodology,
and libraries (code building blocks and
utilities) that automate the process
and eliminate many redundant
verification-coding tasks.

In addition, unlike any other commercially
available methodology, the Plan-to-Closure
“Knowledge System” (a web-based portal
technology) allows you to easily research
topics of interest, and then customize the
methodology to your specific needs. The
Plan-to-Closure Methodology spans
verification planning and management,
assertion-based verification, testbench
automation and reuse, and
system-level verification.

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INCISIVE ENTERPRISE
SPECMAN ESL
TESTBENCH

Traditionally, the “ESL” acronym has been
used to describe the need for scalability
and increased abstraction to accommodate
growing HDL designs. Incisive Enterprise
Specman ESL Testbench (Specman ESL)
builds on this traditional flow to enable
systems engineers, logic designers, software
engineers, verification engineers, and system
validation teams to do ”in-system”
verification at the block, chip, and full
system levels.

This is all made possible by using the
components in Specman ESL to leverage
the metric-driven Plan-to-Closure
Methodology to span design and
verification—from an initial system
specification and system verification plan
to full system-level integration and closure.
The result: rapid discovery of deeply buried,
cross-domain bugs that are impossible to
find otherwise.

INCISIVE SOFTWARE
EXTENSIONS (“ISX”)

ISX gives your testbench access to embed­ded software exactly as if it were another
part of the HDL DUT. Using extensions to
the familiar Incisive SimVision debug tool,
engineers can simultaneously control and
verify software methods, procedures,
variables, registers, and other elements
with a traditional hardware-centric DUT
using the same time-tested coverage-driven
verification (CDV) process described in the
Plan-to-Closure Methodology. Furthermore,
ISX rises above past hardware/software
co-verification limitations by supporting
processor models in any form: workstation­based host-code execution, Instruction
Set Simulator (ISS), full RTL CPU models,
hardware acceleration and emulation, and
even prototype silicon.

TRANSACTION-BASED
ACCELERATED (TBA)

Transaction-based acceleration (TBA)
technology utilizes message-level
communication between the Specman
testbench and the acceleration/emulation
hardware. By communicating at the
message level instead of the signal level,
“TBA Specman” significantly reduces the
amount of testbench-DUT communication,
greatly increasing overall throughput over
simulation alone (up to 100x when used in
combination with the Incisive Palladium®
or Xtreme
and emulators). This level of performance
enables full system-level validation
that includes embedded and application
layer software.

When TBA Specman and ISX are
combined with the verification plan
(“vPlan”)-driven Plan-to-Closure flow,
the result is a predictable, metric-driven
process for both hardware and software
development based on an executable plan
that enforces adherence to the system
specification. In short, this real-time,
automatic annotation of metrics against
the specification gives engineers the
information they need to confidently
argue for additional time to explore
more high-risk corner cases, or to ask for
a new pen to autograph the signoff form.

®

series of hardware accelerators

SPECIFICATIONS

LANGUAGE SUPPORT

• Testbench

–

e (IEEE 1647)

– Interface to SystemVerilog (IEEE 1800)

testbenches (this is a high-performance,
direct kernel interface when using
Incisive platform simulators)

• Device under test

– Verilog (IEEE 1364-1995 and IEEE

1364-2001 extensions)

– VHDL (IEEE 1076-1987, IEEE 1076-1993,

IEEE 1076.4-2000 (VITAL 2000))

– SystemC (OSCI SystemC v2.2,

IEEE 1666)

– PSL (IEEE 1850)

– SVA (IEEE 1800)

– C and C++ models

– Matlab models

– Analog models in Verilog-A, VHDL-A,

or SPICE formats

– Post-silicon hardware

– Specman ESL supports embedded

software and high-throughput
connections to accelerated and
emulated DUTs

TESTBENCH ANALYSIS

• 200+ checks to lint and analyze
code for:

– Code reusability as per

Methodology (eRM) compliance rules

– Performance analysis

– Race conditions

– Pre-defined coding style rules

– Generated constraints

• Graphical interface to sort, filter, and
analyze messages with source code

e Reuse

VERIFICATION BUILDER

• GUI support for configuration of
Plan-to-Closure universal verification
components (UVCs)

• Outputs
(IEEE 1800) Plan-to-Closure UVCs

e (IEEE 1647) or SystemVerilog

SCENARIO BUILDER

• Outputs stimulus conforming to the
“sequences” capability defined in
the IEEE 1647-based

eRM

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– SystemVerilog (IEEE 1800)

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SUPPORT FOR
CADENCE IP

• Design IP

– SoC Functional Verification Kit

• Verification IP

– Supports all simulation-based universal

verification components (UVCs),
transaction-based VIP, assertion-based
VIP, and SpeedBridge® rate adapters
used in emulation

– Supports the full portfolio of

Cadence UVCs: PCI Express, AHB, AXI,
AMBA®, USB, and Ethernet, PCI, SATA,
and OCP

– UVCs are designed to use all

elements of the Incisive platform and
feature a comprehensive Compliance
Management System that leverages
“vPlans” to exhaustively verify
protocol compliance

THIRD-PARTY SUPPORT

• Models

– Third-party model support through

the Cadence Verification IP
Partner program

• Software

– Third-party software support through

the Connections® program with more
than 30 verification company partners

INTERFACES

• Direct kernel interface to all Incisive
platform simulators

• Direct C language interface

• Socket interface

• PLI (IEEE 1364)

• DPI (IEEE 1800)

• VPI (PLI 2.0, IEEE 1364)

• VHPI

PLATFORMS

• Sun Solaris

CADENCE SERVICES
AND SUPPORT

• Cadence application engineers can
answer your technical questions by
telephone, email, or Internet—they can
also provide technical assistance and
custom training

• Cadence certified instructors teach
more than 70 courses and bring
their real-world experience into
the classroom

• More than 25 Internet Learning Series
(iLS) online courses allow you the
flexibility of training at your own
computer via the Internet

• SourceLink
gives you answers to your technical
questions—24 hours a day, 7 days a
week—including the latest in quarterly
software rollups, product change
release information, technical
documentation, solutions, software
updates, and more

®

online customer support

• HP-UX

• Linux

For more information,
Email us at

[e-mail]

or visit

www.cadence.com

© 2007 Cadence Design Systems, Inc. All rights reserved. Connections, Palladium , SourceL ink, and Xtreme ar e registe red trademarks and the Cadence
logo is a trademark of Cadence Design Systems, Inc. ARM and AMBA are r egistered trademar ks of ARM , Ltd. ar e registe red trademarks of Open SystemC
Initiative, Inc. in the United States and other countries and are used with per mission. All other s are pro perties o f their respective holders.

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