Cadence ENCOUNTER DIGITAL IMPLEMENTATION SYSTEM Datasheet

DATASHEET

ENCOUNTER DIGITAL
IMPLEMENTATION SYSTEM

Cadence® Encounter® Digital Implementation System refines
and redefines digital implementation, helping customers deliver
differentiated products to their end market, achieve predictable time
to market with the highest quality silicon, and reduce development
and production costs. It extends the production-proven Encounter
technologies that designers trust to deliver truly scalable, ultra­efficient core memory architecture and end-to-end multi-core
parallel processing for the ultimate in capacity and performance. A
comprehensive solution for mainstream and advanced node flat and
hierarchical designs, it addresses the requirements for design closure,
signoff, low power, mixed signal, and manufacturability and yield
optimization.

ENCOUNTER DIGITAL
IMPLEMENTATION
SYSTEM

Encounter Digital Implementation System
provides a focused, high-performance,
advanced design closure solution for both
flat and hierarchical designs while also
addressing the latest requirements for
low-power, mixed-signal, and advanced
node design. By supporting RTL synthesis,
enabling rapid design exploration
and accurate chip feasibility analysis,
full-chip virtual prototyping, and full-chip
digital implementation and signoff in a
single environment, Encounter Digital
Implementation System gives engineers an
early, accurate view of design feasibility
and allows them to progress immediately
to full-scale implementation and final
signoff for large-scale, complex designs—
without ever leaving the solution
environment.

Encounter Digital Implementation System
combines advanced RTL and physical
synthesis, early design exploration

and analysis using black blobs and
automated floorplan synthesis, clock
tree and clock mesh synthesis, advanced
nanometer routing, mixed-signal support,
advanced low-power implementation,
and a complete suite of design-for­manufacturability, variation, and yield
optimization technologies required for
advanced node designs. These and other
capabilities enable Encounter Digital
Implementation System to deliver the
highest quality of silicon for timing, signal
integrity, area, power, and yield, including
integrated statistical-based analyses and
optimizations.

BENEFITS

• Predictabilityandconvergence

- Combines the power of RTL
synthesis, early design explo­ration, full-chip prototyping and
design implementation, and final
signoff analysis in a single unified
environment

- Enables design exploration and
accurate chip feasibility analysis,
including automated floorplan
synthesis and ranking, for a
flexible and predictable path to
design closure

- Supports location-based on-chip­variation technologies and the latest
statistical methodologies including
integrated analysis and optimization
for statistical timing and leakage

• Productivityandfastertimetomarket

- Provides robust and flexible solutions
for hierarchical methodologies,
including bottom-up block-based
flows, top-down black-box flows,
and hybrid flows with partitioning,
time budgeting, and innovative
top-level assembly and optimization
technologies

- Delivers signoff-driven implemen­tation and intuitive and visual global
timing, power, and clock debug and
diagnostics features

• Scalabilityinperformance

- Delivers industry-leading performance
and capacity for large, complex chips

- Offers a complete, end-to-end, multi­core parallel processing backplane
and infrastructure

• Differentiatedproductdevelopment

with lower production costs

- Provides a comprehensive and
tapeout-proven solution for complex
design closure, low-power, mixed­signal, and advanced node design
implementation and optimization

- Supports comprehensive
multi-mode/multi-corner analysis
and optimization in all steps across
the design flow

- Enables concurrent chip/package
design and optimization with
integrated capabilities such as
automatic area and peripheral I/O
placement and optimization, and
flip-chip RDL routing

- Allows floorplanning, implemen­tation, and analysis of stacked die
in 3D IC

DESIGN CLOSURE

Encounter Digital Implementation System
supports all implementation styles—from
flat or hierarchical to single or multi­VDD. The fast power-grid design and
optimization, global routing, in-place
optimization, and global timing debug
capabilities provide a robust infrastructure
to implement any methodology.

EARLY DESIGN EXPLORATION

Today’s physical design teams start
physical implementation and design
planning very early in the design cycle—
with early and multiple versions of the
design netlist—to determine design
feasibility. Among the questions needing
answers are the following: Can the design
be implemented in the required area? Can
the design operate at the desired speed?
Does it meet power requirements?

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Figure 1: Encounter Digital Implementation System delivers a comprehensive solution

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Design

Closure

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Encounter Digital Implementation System
addresses these challenges:

• Production-provenautomatedoorplan

synthesis of Cadence First Encounter®
technology closes the gap between
the architecture and implementation
by enabling timing, power, area, and
congestion-aware placement coupled
with fast global routing and in-place
optimization; helps designers quickly
generate prototype floorplans

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Large Chip Design Closure

Low-Power Design

Advanced Node Design

Mixed-Signal Design

Encounter Silicon Virtual Prototyping to
bring physical predictability into their
estimations

SILICON VIRTUAL PROTOTYPING
AND HIERARCHICAL CAPABILITIES

Full-chip flat prototyping delivers the
complete physical, timing, clock, and
power data, thereby eliminating the
guesswork associated with traditional
block-based approaches. Hierarchical
support helps physical designers assess

• Built-inexibilityandeditingcapabilities

such as relative floorplan (specifying
relationships for pre-routes, resizable
objects, multiple relations, datapath
stacking, and integrated analysis tools)
and resize floorplan; enable designers
to quickly and accurately reach an
optimal final floorplan

• Floorplanrankingsystemautomatically

generates multiple floorplan scenarios
in parallel and analyzes them based on
pre-defined quality-of-results criteria;
allows designers to explore as much of
the physical solution space as possible
and make the most informed tradeoff
for design feasibility

• Uniqueabstractionmodels(black

blobs) enable very early and fast
design planning for huge designs;
allows designers to start the design
planning process even when no netlist
is available; also enables a path where
system designers can use Cadence
InCyte Chip Estimator and link it to First

how best to partition the logical hierarchy
into physical modules. With hierarchical
support, designers can analyze the
optimal pin assignments, budget time
quickly, accurately predict the clock
distribution networks, analyze the power
grids, and eventually generate complete
timing and physical constraints for each of
the physical modules.

ADVANCED TIMING CLOSURE

Encounter Digital Implementation
System’s global physical synthesis
capability optimizes multiple paths
simultaneously while performing multi­dimensional and concurrent optimization
for timing, signal integrity, power, area,
congestion, wire length, and yield using
native signoff engines in the process.
Additionally, significant improvements in
performance, accuracy, and throughput
can be achieved using robust end-to-end
multi-mode/multi-corner (MMMC) analysis
and optimization technologies.

Signoff Analysis

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ENC OU NTER DI GI TAL I MPLE MEN TAT ION S YSTE M

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