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Test & Diagnostics
Power & SI Analysis
Constraint
Management
& Equivalence
Checking
Silicon Virtual Prototyping
Nanometer Routing
Manufacturing
RTL Synthesis
Global Physical Synthesis
ENCOUNTER DIAGNOSTICS
Yield loss is one of the biggest challenges with sub-90nm
designs. Traditional in-line inspection techniques cannot keep
with pace with the increasing number of subtle design-process
variations. Cadence® Encounter® Diagnostics is the industry’s
first yield diagnostics technology proven to accelerate yield
ramp in manufacturing environments. It rapidly analyzes
thousands of failures, identifies the source of systematic yield
loss, and accurately pinpoints defect location in the netlist
and layout—prior to silicon.
ENCOUNTER TEST
Encounter Test, a key technology in the
Cadence Encounter digital IC design platform, delivers the industry’s most advanced
test solution from RTL to silicon. It includes
three component technologies: Encounter
Test Architect, to minimize cost of test;
Encounter True-Time Test, to ensure quality of shipped silicon; and Encounter
Diagnostics, to accelerate yield ramp.
ENCOUNTER
DIAGNOSTICS
Encounter Diagnostics is the industry’s
first yield diagnostics technology proven
to accelerate yield ramp in nanometerscale ICs. It supports volume and precision
operating modes, static and dynamic
diagnostics, patented pattern fault modeling, schematic cross-probing between
logic and physical models, and all industry-standard ATPG test vector formats.
In volume mode, Encounter Diagnostics
uses features such as logic-cone defect
partitioning, automated fault selection,
parallel runtime support, SQL-compatible
Figure 1: Encounter digital IC design platform
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for initial silicon debug, yield ramp, yield
Logic design
Test infrastructure
• Minimize cost and
time to market
Delay test generation
• Maximize product
quality
Diagnostics
• Maximize yield
and ramp
Encounter Test Architect
• Full-chip test infrastructure compilation
• Specify-compile-verify methodology
Encounter True-Time Test
• Stuck-at, at-speed, and faster-than-at-speed
• Uses design timing to drive test timing
Encounter Diagnostics
• Volume mode finds critical yield limiters
• Precision mode locates root cause
Physical design
Silicon
manufacturing
RTL
Silicon
Netlist
GDSII
Vectors
learning, and even diagnosing customer
field returns.
Encounter Diagnostics XL achieves a
proven 80% accuracy through its advanced
features such as scan-chain diagnostics,
transition diagnostics, logic-cone defect
partitioning, pattern fault modeling, and
diagnostics ATPG. Scan-chain diagnostics
uses special algorithms to identify problems
within the scan chains themselves.
Transition diagnostics identifies faults
that cause delay test failures. Logic-cone
defect partitioning helps separate faults
in ICs that have multiple defects. All
three cases are increasingly common in
nanometer ICs.
Figure 2: Encounter Diagnostics
database, and failsafe termination to
identify the biggest yield-limiting issues.
In precision mode, it pinpoints nanometer
defects using capabilities such as scanchain diagnostics, advanced callout analysis,
diagnostics test pattern generation,
invariant analysis, and an advanced
integrated GUI analysis environment
that supports schematic cross-probing
between logic and physical models. The
result is an industry-leading 80% defect
identification rate as verified by physical
failure analysis.
Encounter Diagnostics is available in
two offerings: Encounter Diagnostics XL
volume and precision diagnostics, which
offers four diagnostics engines and the
Encounter Diagnostics XL environment,
which offers four diagnostics engines,
and the Encounter Diagnostics XL
environment, which adds volume analysis
and enhanced navigation capabilities.
BENEFITS
• Identifies the most critical yield-limiting
design process issues
• Consistently locates root cause defects
with up to 80% accuracy
• Isolates faults efficiently with bidirectional cross-probing between
logical and physical models
• X-Y location reporting of suspected
defects maximizes the effectiveness of
physical failure analysis lab equipment
• Analyzes thousands of failed devices
quickly
• Universal ATPG vector support enables
easy integration with any flow
• Patented pattern fault modeling makes
it ideal for 65nm and 45nm defect
identification
• Increases value of existing automated
yield learning system
• Offers a scalable solution that uses
multiple processors or multiple servers
and robust SQL-compatible database
• Identifies scan-chain defects
• Locates failures in customer field returns
FEATURES
ENCOUNTER DIAGNOSTICS
XL VOLUME AND PRECISION
DIAGNOSTICS
Encounter Diagnostics XL offers volume
and precision diagnostics capability via its
four pack (four diagnostics engines). In
precision mode, Encounter Diagnostics XL
precisely locates the root cause defects
in a given silicon die. This mode is useful
Encounter Diagnostics XL includes
patented pattern fault modeling, which
allows you to define powerful customized
fault models to target virtually any logical
or physical (bridging) defect. If the existing
test vectors cannot produce a discernable
isolated fault, Encounter Diagnostics XL
can create additional test vectors that will
target each potential fault independently
and run in an optimized fashion on
probing equipment.
ENCOUNTER DIAGNOSTICS XL
ENVIRONMENT
The Encounter Diagnostics XL environment adds volume analysis capabilities
to support volume diagnostics using the
Encounter Diagnostics XL four pack. Volume
diagnostics is a rapidly emerging application for systematically identifying the most
critical systemic yield issues. The Encounter
Diagnostics XL environment uniquely
supports this application with a number
of advanced features including a fully
SQL-compatible database, failset analysis,
parallel runtime support, failsafe termination, automated fault selection, and a data
extraction programming interface.
Failset analysis saves significant computation time by eliminating the need to
run diagnostics on failsets for dies that
are either guaranteed or highly likely to
have identical diagnostics results. Parallel
runtime support enables simultaneous
execution across multiple processors or
servers to maximize throughput. Failsafe
www.c a den c e.c om
ENC OU NTER DI AG NOST ICS
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Time
Yield
Silicon debug
Production yield
Yield learning
Yield ramp
Field returns
Figure 3: Encounter Diagnostics greatly increases yield ramp and yield learning
• More than 25 Internet Learning
Series (iLS) online courses allow you
the flexibility of training at your own
computer via the Internet
• SourceLink
®
online customer support
gives you answers to your technical questions—24 hours a day, 7
days a week—including the latest in
quarterly software rollups, product
change release information, technical
documentation, solutions, software
updates, and more
termination and automated fault selection ensure efficient execution. Volume
diagnostics can run in standalone batch
mode (wherein you select the failsets to
analyze) or integrated as a subsystem in
an automated yield learning environment.
In the latter case, the main points of integration are automatic failset selection and
automatic results analysis using the data
extraction interface for detailed analysis
of results.
IMPROVED NAVIGATION
The Encounter Diagnostics XL
environment has been enhanced with
a full-function, highly efficient physical
layout browsing capability to quickly
identify physical structures causing
failures. The layout browser integrates
with existing Encounter Diagnostics
analysis capabilities. This makes it possible
to bi-directionally cross-probe between the
logical schematic viewer and the physical
layout browser, and also to uni-directionally
cross-probe from the View Callout List
function to the layout browser when
localizing a failure. The layout browser
reads layout information stored in an
OpenAccess database (version 2.2 or
higher).
PLATFORMS
• Sun Solaris (64-bit)
• HP-UX (64-bit)
• Linux (32-bit, 64-bit)
• IBM AIX (32-bit, 64-bit)
CADENCE SERVICES
AND SUPPORT
• Cadence application engineers can
answer your technical questions by
telephone, email, or Internet—they
can also provide technical assistance
and custom training
• Cadence certified instructors teach
more than 70 courses and bring
their real-world experience into
the classroom
For more information, email us
at info@cadence.com or visit
www.cadence.com
© 2007 Cadence Design Systems, Inc. All rights reserved. Cadence and Encounter are registered trademarks and
the Cadence logo is a trademark of Cadence Design Systems, Inc. All others are properties of their respective holders.
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