Cadence ENCOUNTER CONFORMAL LOW POWER Datasheet

DATASHEET

ENCOUNTER

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Test & Diagnostics

Power & SI Analysis

Constraint
Management
& Equivalence
Checking

Silicon Virtual Prototyping

Nanometer Routing

Manufacturing

RTL Synthesis

Global Physical Synthesis

G0001

ENCOUNTER CONFORMAL
LOW POWER

Cadence® Encounter® Conformal® Low Power, a key technology
of the Cadence Encounter digital IC design platform, enables
designers to verify and debug multimillion-gate designs optimized
for low power, without simulating test vectors. It combines
low power structural and functional checks with world-class
equivalence checking to provide superior performance, capacity,
and ease of use.

ENCOUNTER PLATFORM

To release innovative products in narrow
market windows, companies need to
focus precious engineering resources
on where they add the most value—
differentiating their designs. The Cadence
Encounter digital IC design platform
offers a full spectrum of technologies for
nanometer-scale SoC design, helping both
Logic Design and physical implementation
teams achieve high-quality silicon quickly.
As an integrated RTL-to-GDSII design
environment, the Encounter platform
provides a complete flow—from RTL
synthesis and test design, through silicon
virtual prototyping and partitioning, to
final timing and manufacturing closure.
It delivers the highest quality of silicon
(timing, area, and power with wires),
accurate verification, signal-integrity—
aware routing, and the latest yield and
low-power design capabilities that are
critical for advanced 65nm designs. With
Encounter technology, you can boost your
productivity, manage complexity, and get
your products to market faster.

Encounter platform products are available
in L, XL, and GXL offerings.

Figure 1: Encounter digital IC design platform

Logic synthesis (area,
power, timing, yield)

RTL

Datapath and
test synthesis

Floorplanning and
physical synthesis

Place-and-route

ECO’s

Final layout

Custom memory design

Encounter
Conformal
Low Power XL

Encounter
Conformal
Low Power GXL

Custom circuit design

Logic equivalence checking
for low power design

Extended functional checks
Clock domain crossing checks
Semantic checks
Structural checks
Reachability and FSM checks

Equivalence checking support
for complex datapath and
final LVS netlist (SPICE)

Low power structural
and functional checks for
logical and power aware
design netlist

Equivalence checking
support for digital custom
logic, cell libraries, IO, and
embedded memories

Electrical verification of low
power transistor netlist

Figure 2: Encounter Conformal Low Power offers a complete solution—from RTL to final layout

ENCOUNTER CONFORMAL
LOW POWER

Consumers increasingly expect longer
battery life and higher performance in

their mobile devices. As these sometimes
conflicting demands force chips to
move into nanometer-scale processes,
power management becomes one of
the most critical design issues. Due to
increased leakage, devices created using
90-nanometer and smaller process nodes
consume as much power when they are
not in use as when they are being used.

Optimizing for leakage and dynamic power
helps designers reduce energy use and
lower cooling and packaging costs. While
advanced low power methods—such
as static and dynamic voltage/frequency
scaling, power gating, and state
retention—offer additional power savings,
they also complicate the verification task.

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ENC OU NTER CO NF ORMA L L OW POW ER

Verification complexity is amplified by
the fact that the majority of the low
power function is introduced into the
gate netlist during synthesis and physical
implementation. Full-chip, gate-level
simulation is not a practical or scalable
methodology for verifying the logic
function of the today’s designs due to their
size and complexity.

Encounter Conformal Low Power, which
combines proven equivalence checking and
functional checks, uses formal techniques
to address this challenge, enabling full-chip
low power verification.

Encounter Conformal Low Power is
available in XL and GXL offerings.

BENEFITS

• Minimizes silicon re-spin risk by providing
complete verification coverage

• Detects low power implementation
errors early in the design cycle

• Reduces verification time significantly by
verifying multimillion gate designs faster
(by orders of magnitude) than traditional
gate-level simulation

• Closes the RTL-to-layout verification gap

• Decreases risk of missing critical bugs
through independent verification
technology

FEATURES

ENCOUNTER CONFORMAL
LOW POWER XL

It combines logic equivalence checking
for the most complex low power SoC and
datapath-intensive designs, with functional
and structural checks for low power
designs, clock domain synchronization and
semantics.

EQUIVALENCE CHECKING FOR LOW
POWER DESIGN

During development, a low power design
undergoes numerous iterations prior to
final layout, and each step in this process
has the potential to introduce logical bugs.

Encounter Conformal Low Power XL checks
the functional equivalence of different
versions of a low power design at these
various stages and enables you to identify
and correct errors as soon as they are
introduced. It supports advanced dynamic
and static power synthesis optimizations
such as clock gating and signal gating,
Multi Vt libraries, as well as de-cloning and
re-cloning of gated clocks during clock tree
synthesis and optimization.

Encounter Conformal Low Power XL
supports the Common Power Format
(CPF) specification language. It uses CPF
as guidance to independently insert and
connect low-power cells—level shifters,
isolation, and state retention registers—into
an RTL design, thus enabling true low
power RTL to gate equivalence checking.
The tool can also model level shifters and
isolation cells as domain anchor points
during equivalence checking to detect
whether logic gates have erroneously
crossed domain boundaries from one
version of the netlist to another.