Cadence ENCOUNTER CONFORMAL EQUIVALENCE CHECKER Datasheet

DATASHEET

ENCOUNTER

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Test & Diagnostics

Power & SI Analysis

Constraint
Management
& Equivalence
Checking

Silicon Virtual Prototyping

Nanometer Routing

Manufacturing

RTL Synthesis

Global Physical Synthesis

G0001

ENCOUNTER CONFORMAL
EQUIVALENCE CHECKER

Cadence® Encounter® Conformal® Equivalence Checker (EC),
makes it possible to verify and debug multi-million-gate designs
without using test vectors. It offers the only complete equivalence
checking solution available for verifying SoC designs—from RTL
to final LVS netlist (SPICE)—as well as FPGA designs. Encounter
Conformal EC enables designers to verify the widest variety of
circuits, including complex arithmetic logic, datapaths, memories,
and custom logic.

ENCOUNTER CONFORMAL
EQUIVALENCE CHECKER

Already proven in thousands of tapeouts,
Encounter Conformal EC is the industry’s
most widely supported equivalence
checking product. In addition, it is
production-proven on more physical
design closure products, advanced
synthesis software, ASIC libraries, and IP
cores than any other formal verification
technology.

Encounter Conformal EC is available in L,
XL, and GXL offerings.

BENEFITS

• Exhaustively verifies multimillion-gate
ASICs and FPGAs—several times faster
than traditional gate-level simulation

• Decreases the risk of missing critical
bugs with independent verification
technology

• Enables faster, more accurate bug
detection and correction throughout
the entire design flow

Figure 1: Encounter digital IC design platform

RTL

Synthesis

Place and route

Physical synthesis

ECOs

Final layout

Datapath synthesis

Custom circuit design

Custom memory design

Encounter
Conformal EC L

Logic equivalence checking
Dual language support
Semantic checks
Structural checks
Clock domain crossing check

Extends equivalence checking
to digital custom logic and
memories

Encounter
Conformal EC XL

Encounter
Conformal EC GXL

Extends equivalence
checking to datapath
and layout vs. schematic
(LVS) reference SPICE netlist

Figure 2: Encounter Conformal EC offers a complete solution—from RTL to final layout

• Eliminates functional clock domain
crossing problems early in the design
cycle

• Extends equivalence checking capability
to complex datapaths, and closes the
RTL-to-layout verification gap (with
Encounter Conformal EC XL)

• Ensures RTL models perform the same
functions as the corresponding transistor
circuits implemented on silicon (with
Encounter Conformal EC GXL)

FEATURES

ENCOUNTER CONFORMAL

EQUIVALENCE CHECKER L

Encounter Conformal EC L combines
extended functional checks with core
equivalence checking technology.

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ENC OU NTER CO NF ORMA L E QU IVA LEN CE CHE CKE R

Equivalence Checking

During the development of a design, it
undergoes numerous iterations prior to
final layout, and each step in this process
has the potential to introduce logical bugs.
Encounter Conformal EC L checks the
functional equivalence of different versions
of a design at these various stages and
enables designers to identify and correct
errors as soon as they are introduced.

Design Flow Independence

Encounter Conformal EC L provides
an independent audit of the design
process to eliminate the risks associated
with sharing technologies across design
implementation and design verification
products. The tool includes technologies
developed independently from the design
flow, including production-proven HDL
parsing, synthesis, mapping, optimization,
and datapath algorithms. Using Encounter
Conformal EC L ensures that the maximum
number of design bugs will be caught.

Integrated Environment

An intuitive graphical user interface (GUI)
provides for setup and debugging. It allows
users to work more productively and
quickly pinpoint the cause of mismatches.
The environment includes:

• Graphical debugging via an integrated
schematic viewer that shows logic values
for each error vector

• Full cross-highlighting between RTL
model and circuit

• Automatic error candidate identification
with assigned and weighted percentages

• Logic-cone pruning to focus debugging
on relevant information

FPGA Equivalence Checking
Support

As FPGA devices continue to grow in
size and complexity, FPGA designers are
facing design closure challenges similar
to those encountered by their ASIC
counterparts. Equivalence checking has
become a necessity in the FPGA design
implementation flow. Encounter Conformal
EC L supports Synplify Pro synthesis, as
well as the Xilinx ISE and Altera Quartus II
implementation flows.

Clock Domain Crossing (CDC) and
Extended Functional Checks

Encounter Conformal EC L enables designers
to perform verification of the asynchronous
clock domain crossings and other intrinsic
properties of their designs. These checks
complement equivalence checking by verifying
areas previously not validated by traditional
equivalence checkers and by finding difficult
implementation bugs early in the design cycle.
The end result is a safer verification solution.

• Clock domain crossing checks

– Recognize FIFO synchronizers

automatically

– Validate synchronization structure

– Verify data stability

• Semantic checks—Verify synthesis
assumptions and find conditions that
may create mismatches between RTL
and gate-level simulations