Cadence ALLEGRO FPGA SYSTEM PLANNER System Planner Manual

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ALLEGRO FPGA
SYSTEM PLANNER

The Cadence® Allegro® FPGA System Planner addresses the
challenges that engineers encounter when designing one or
more large-pin-count FPGAs on the PCB board—which includes
creating the initial pin assignment, integrating with the sche­matic, and ensuring that the device is routable on the board.
It delivers a complete, scalable technology for FPGA-PCB
co-design that automates creation of optimum “device-rules­accurate” pin assignment. By replacing manual, error-prone
processes with automatic pin assignment synthesis, this unique
placement-aware solution eliminates unnecessary physical
design iterations while shortening the time required to create
optimum pin assignment.

Cadence FPGA System Planner
technologies are available in the
following product offerings:

• Allegro FPGA System Planner L,

XL, and GXL

• Allegro FPGA System Planner Two

FPGA Option L

• Cadence OrCAD FPGA System

Planner

User IO

Configurable

Clock

Capable

Figure 1: Color-coded map of the I/Os of a multi-bank FPGA with different types of configurable pins

Differential

Power

DESIGNING LARGE-PIN­COUNT FPGAS ON PCBS

Integrating today’s FPGAs—with their
many different types of assignment rules
and user-configurable pins—on PCBs is
time consuming and extends design cycles.
Often the pin assignment for these FPGAs
is done manually at a pin-by-pin level in
an environment that is unaware of the
placement of critical PCB components
that are connected to FPGAs. Without
understanding the impact to PCB routing,
FPGA-based design projects are forced to
choose between two poor options: live
with suboptimal pin assignment, which
can increase the number of layers on a PCB
design; or deal with several unnecessary
iterations at the tail end of the design cycle.
Even with several iterations, this manual
and error-prone approach can result in
unnecessary PCB design re-spins.

With the added time required to generate
pin assignments for FPGAs using manual
approaches, users are unable to do trade­offs between the different FPGA devices
available and the cost of devices used
in an FPGA sub-system. This is because
performing the trade-offs would mean
that users would have to do two projects
in parallel with no design reuse of any
kind between the two.

With a way to quickly synthesize optimum
pin assignment using user-specified design
intent at a high-level, the Allegro FPGA
System Planner enables designers to explore
their FPGA-based architecture and to create
an optimum correct-by-construction pin
assignment for either production or
prototype designs that use FPGAs.

The Allegro FPGA System Planner is
integrated with the Cadence design
creation tools: Cadence OrCAD
and Cadence Allegro Design Entry (CIS
and HDL). It reads and creates schematic
symbols for both OrCAD Capture and
Allegro Design Entry HDL. In addition,
a floorplan view uses existing footprint
libraries for OrCAD PCB Designer and
Allegro PCB Editor. Should placement
change during layout, pin optimization
using the Allegro FPGA System Planner
can be accessed directly from the Allegro
PCB Editor.

®

Capture

BENEFITS

• Scalable,cost-effectiveFPGA-PCB

co-design solution from OrCAD Capture
to Allegro GXL

• Shortenstimeforoptimuminitialpin

assignment, accelerating PCB design
schedules

• AcceleratesintegrationofFPGAswith

Cadence PCB design creation
environments

• Eliminatesunnecessary,frustrating

design iterations during the PCB layout
process

• Eliminatesunnecessaryphysical

prototype iterations due to FPGA pin
assignment errors

• ReducesPCBlayercountthrough

placement aware pin assignment and
optimization

FEATURES

ALLEGRO FPGA SYSTEM PLANNER
TECHNOLOGY

An FPGA system is defined as a subset of
the PCB design that includes one or more
FPGA and non-FPGA components that are
connected to FPGAs.

Traditional approaches to pin assignment
are typically manual and often based on
a spreadsheet. Tools such as these require
users to do pin assignment without
taking into consideration the placement
of other components and routability
of the interfaces and signals. Above
all, there is no online rules-checking to
ensure that the right pin types are being

The Allegro FPGA System Planner
provides a complete, scalable solution
for FPGA-PCB co-design that allows
users to create an optimum correct-by­construction pin assignment. FPGA pin
assignment is synthesized automatically
based on user-specified, interface-based
connectivity (design intent), as well as
FPGA pin assignment rules (FPGA-rules),
and actual placement of FPGAs on PCB
(relative placement). With automatic pin
assignment synthesis, users avoid manual
error-prone processes while shortening
the time to create initial pin assignment
that accounts for FPGA placement on the
PCB (placement-aware pin assignment
synthesis). This unique placement-aware
pin assignment approach eliminates
unnecessary physical design iterations that
are inherent in manual approaches.

Figure 2: Placement/Floorplan view of the Allegro FPGA System Planner provides users relative placement of
critical components for optimum pin assignment synthesis

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CAD EN CE A LLE GR O FP GA SY STEM PL AN NER

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