Manual P/N 454-44000 BVM Limited,
Hobb Lane,
Hedge End,
Southampton,
SO30 0GH, UK.
TEL: +44 (0)1489 780144
FAX: +44 (0)1489 783589
E-MAIL: sales@bvmltd.co.uk
WEB: http://www.bvmltd.co.uk
User's Manual
BVME4000/6000
MC68040/68060 SINGLE BOARD
COMPUTER
Board Revision F
Manual Revision I 21 February 2001
This material contains information of proprietary interest to BVM Ltd. It has been supplied in
confidence and the recipient, by accepting this material, agrees that the subject matter will not be
copied or reproduced, in whole or in part, nor its contents revealed in any manner or to any person
except to meet the purposes for which it was delivered.
This page is intentionally left blank.
i
DISCLAIMER
The information in this document has been checked and
is believed to be entirely reliable, however no
responsibility is assumed for inaccuracies. BVM Ltd.
reserves the right to mak e changes and/or im provements
in both the product and the product documentat ion without
notice. BVM Ltd. does not assum e any liability arising out
of the application or use of any produc t described herein;
neither does it convey any licenc e under its patent rights
or the rights of others.
USE OF PRODUCT
This product has been designed to operate in a VMEbus
and IndustryPack compatible electrical environment.
Insertion of the board into any s lot which is not VMEbus
compatible is likely to cause serious damage. Insertion
and removal of the board from the backplane or
IndustryPack(s) or cable(s) from the board must not be
done whilst in a powered condition.
Do not lever out any devices from the produc t, whic h us es
surface-mounted devices extensively, as these can be
fractured by excessive force.
This product uses devices sensitive to static electricity.
Ensure adequate static electricity precautions are
observed when handling the product and associated
devices.
RF. INTERFERENCE
This product complies with European Council Directive
89/336/EEC (EMC directive), and conforms to
EN55022:1995 Class B (Limits and methods of
measurement of radio interference characteristics of
information technology equipment) and EN50082-1:1992
(Electromagnetic compatibility - Generic immunity
standard, Part 1: residential, commercial and light
industry) when used in accordance with the BVM EMC
Guidelines Manual part number 454-77000 (available on
request from BVM Ltd.).
GENERAL NOTICES
UNPACKING AND INSPECT I ON
This product contains c omponents which are suscept ible
to static discharge, and should be handled with
appropriate caution.
Upon receipt of this product, visually inspec t the board for
missing, broken or dam aged com ponents and for phys ical
damage to the printed circuit board or connectors. This
product was shipped in perfect physical condition. Any
physical damage to the product is the responsibility of the
shipping carrier and should be reported to the carrier's
agent immediately.
RETURN OF GOODS
Before returning a product for repair, verify as well as
possible that the suspect ed unit is at f ault. Then call BVM
Ltd. for a Customer Return (CR) number. Carefully
package the unit, in the original shipping cart on if this is
available, and ship prepaid and insured, preferably by
courier, with the CR number written on the outside of the
package.
Include a return address and the telephone num ber of a
technical contact, and a detailed description of the
observed fault. For out-of-warranty repairs, a purchase
order for repair charges must accom pany the return. BVM
Ltd. will not be responsible for damage due to improper
packaging of returned items. Out of warranty repairs can
be arranged, and will be charged on a material and labour
basis, subject to a minimum repair charge. Return
transportation and insurance will be charged as part of t he
repair and is in addition to the minimum charge.
SOFTWARE LICENCE NOTICE
Any software that is provided as Copyright BVM Ltd. is
proprietary and confidential property of BVM Ltd., and
each single copy is given on the agreed understanding
that it is licensed for use on product combinations
supplied by BVM Ltd. or their appointed dist ributors only.
The software product may not be copied (except for
backup purposes), given away, rented, loaned,
reproduced, distributed or trans mitted in any way or form,
in whole or in part, without written permiss i on of BVM Ltd.
This applies to any merged, m odified or derivative version
of the software including, but not limited to, versions
produced by customising, translating, reverse
engineering, decompiling or disassem bly.
This licence may be automatically terminated without
notice if any of its provisions are breached. Reasonable
legal costs may be awarded to the prevailing party in
connection with this licence agreement. Use of, or
accepted delivery of these products shall constitute your
acceptance of the provisi ons of this licence agreement.
WARRANTY
A) BVM Ltd. warrants that the articles furnis hed hereunder
are free from defects in material and workm anship for one
year after the date of shipment.
B) All warranties and conditions, express and implied,
statutory and otherwise, as to the qualit y of the goods or
their fitness for any purpose are hereby excluded and with
the exception of liability for death or personal injury
caused by negligence as defined in the Unfair Contract
Terms Act 1977 the s eller shall not be liable for any loss,
injury or damage arising directly or indirectly f rom the us e,
application or storage of such goods.
C) Subclause (B) above shall not apply where the buyer
deals as a consumer as thi s expression is defined in the
Unfair Contract Terms A ct 1977.
D) The liability of BVM Ltd. hereunder shall be limited to
repair or replacement at the manufacturers discretion of
any defective unit. Equipm ent or parts which have been
subject to abuse, misuse, accident, alteration, neglect,
unauthorised repair or installat ion are not covered by this
warranty. BVM Ltd. shall have t he right of determination
as to the existence and cause of any def ect.
E) The warranty period of the replacement or a repaired
product or part shall term inate with the termination of the
warranty period with respect to the original product or part
for all replacement parts supplied or repairs made during
the warranty period.
F) Although BVM Ltd. offer a high level of technical
support and advice, due to the com plex nature and wide
application of product configurations it is the responsibility
of the purchaser to be satis fied at the time of purchase
that the products are suitable for the final applicati on.
G) The term 'Software' used herein is defined as 'any
program data or code in sourc e or binary format recorded
in or on any readable device or media'.
H) BVM Ltd. will effect all reasonable effort to resolve
accepted reproducible soft ware errors reported within 12
months of purchase. Acceptance of an error shall solely
be based on conformance to supporting specifications.
Proper operation of earlier releases is not guaranteed.
NOTICES
Copyright 1993,1995,1998,2001 by BVM Ltd.
OS-9 is a registered trademark of Microware Systems
Corporation.
VxWorks is a regi stered trademark of Wind River Systems
Inc.
IndustryPack is a registered trademark of Greenspring
Computers.
ii
WARNINGS
Do not lever out the EPROM's from the BVME4000/6000. The board
uses surface-mounted devices extensively, which can be fractured by
excessive force. Use proper EPROM extraction and insertion tools.
Damage may result if users attempt to remove or fit EPROM's
incorrectly.
Do not lever out the IP's from the BVME4000/6000. The board uses
surface-mounted devices extensively, which can be fractured by
excessive force. Damage may result if users attempt to remove or fit
IP's incorrectly.
Do not lever out memory modules from the BVME4000/6000. The
board uses surface-mounted devices extensively, which can be
fractured by excessive force. Memory modules are not a field-fit option.
Damage may result if users attempt to remove or fit memory
modules incorrectly.
Do not fit/remove the 68040/68060 device to/from the
BVME4000/6000. Special tools are required to fit and remove these
devices and the correct voltage settings must be selected. Return the
board to the factory if the 68040/68060 device requires changing.
Damage may result if users attempt to fit or remove the
68040/68060 device.
The BVME4000/6000 uses devices sensitive to static electricity.
Ensure adequate static electricity precautions are observed when
handling the BVME4000/6000, EPROM's, IP's and memory modules.
Ensure the correct polarity of connections to the BVME4000/6000.
In particular ensure the correct polarity of connections to the P2 I/O
connector, incorporating the SCSI connections. Damage may result if
users fail to observe correct connection polarity to the
BVME4000/6000.
iii
Table Of Contents
Contents Page
1. Introduction.......................................................................................................................................1
1.1 Scope.........................................................................................................................................1
1.2 BVME4000 Part Numbers..........................................................................................................1
1.3 BVME6000 Part Numbers..........................................................................................................1
1.4 Memory Module Part Numbers ..................................................................................................1
2. Overview...........................................................................................................................................2
2.1 Board Layout..............................................................................................................................2
2.2 Features.....................................................................................................................................3
2.3 Applications................................................................................................................................3
3. Description........................................................................................................................................4
3.1 Block Diagram............................................................................................................................4
3.2 Processor...................................................................................................................................5
3.3 Memory ......................................................................................................................................5
3.4 Real Time Clock.........................................................................................................................5
3.5 Serial Communications ..............................................................................................................6
3.6 Parallel Port................................................................................................................................6
3.7 SCSI Interface............................................................................................................................6
3.8 Ethernet Interface.......................................................................................................................6
3.9 IP I/O..........................................................................................................................................6
3.10 VMEbus Interface.....................................................................................................................7
3.10.1 VMEbus Master ................................................................................................................... 7
3.10.2 VMEbus Slave...................................................................................................................... 7
3.11 Interrupts ..................................................................................................................................8
3.11.1 VMEbus Interrupt Handler ...................................................................................................8
3.11.2 Internal Interrupts.................................................................................................................8
3.11.3 VMEbus Interrupter..............................................................................................................8
3.12 VMEbus System Controller Functions......................................................................................9
3.13 Power Supply Monitor/Watchdog .............................................................................................9
3.14 Local Bus Monitor.....................................................................................................................9
3.15 Configuration Switch.................................................................................................................9
3.16 EEPROM..................................................................................................................................9
4. Installation.......................................................................................................................................10
5. Configuration ..................................................................................................................................11
5.1 PCB Layout..............................................................................................................................11
5.2 Link and Switch Definitions ......................................................................................................12
5.2.1 LK1 Abort Switch Enable......................................................................................................12
5.2.2 LK2 Reset Switch Enable.....................................................................................................12
5.2.3 LK3 VMEbus Reset Out Enable...........................................................................................13
5.2.4 LK4 VMEbus Reset In Enable.............................................................................................. 13
5.2.5 LK5 CPU Cache Inhibit.........................................................................................................14
5.2.6 LK6 Cheapernet Heart Beat Enable.....................................................................................14
5.2.7 LK7,8,9 Ethernet AUI/Cheapernet Select ............................................................................15
5.2.8 LK10,11,12,14,15 EPROM Size & Type Select...................................................................15
5.2.9 LK13 SCSI Termination Disable...........................................................................................16
5.2.10 LK18,19 CPU 5/3.3V Selection.......................................................................................... 16
iv
5.2.11 LK21 SRAM Backup Selection.......................................................................................... 17
5.2.12 LK22 VMEbus System Controller Enable..........................................................................17
5.2.13 Configuration Switch.......................................................................................................... 18
5.3 Indicators..................................................................................................................................18
5.3.1 Green LED - RUNNING........................................................................................................18
5.3.2 Red LED - VMEbus Master Access ..................................................................................... 18
6. Connector Pinouts ..........................................................................................................................19
6.1 JP1 & JP2 Serial Port Connections..........................................................................................19
6.2 JP3 Parallel Port Connections..................................................................................................19
6.3 JP4 Cheapernet Connector......................................................................................................20
6.4 JP4 Optional 10BaseT Connector............................................................................................20
6.5 JP5A/B IP A/B Connections.....................................................................................................21
6.6 JP7 CPU Fan Power................................................................................................................22
6.7 JP8 JTAG Connector ...............................................................................................................22
6.8 J1 SCSI Connections...............................................................................................................22
6.9 J14 SCSI Peripheral Power Connections.................................................................................23
6.10 P2 I/O Connections ................................................................................................................23
6.11 Protection Fuses.....................................................................................................................24
7. Programming..................................................................................................................................25
7.1 Address Map............................................................................................................................25
7.1.1 I/O Address Map................................................................................................................... 26
7.2 Memory Module........................................................................................................................26
7.3 VMEbus Master Access...........................................................................................................27
7.3.1 A16:D16 (D08EO).................................................................................................................27
7.3.2 A16:D32................................................................................................................................27
7.3.3 A24:D16 (D08EO)................................................................................................................. 27
7.3.4 A24:D32................................................................................................................................28
7.3.5 A32:D16................................................................................................................................28
7.3.6 A32:D32................................................................................................................................28
7.4 SRAM.......................................................................................................................................29
7.5 EPROM....................................................................................................................................29
7.6 SCSI Controller ........................................................................................................................30
7.6.1 Overview...............................................................................................................................30
7.6.2 Programming ........................................................................................................................30
7.6.3 Hardware Specific Considerations .......................................................................................30
7.6.4 SCSI Controller Registers.....................................................................................................31
7.6.5 SCSI Electrical Interface....................................................................................................... 32
7.7 Ethernet Controller...................................................................................................................33
7.7.1 Overview...............................................................................................................................33
7.7.2 Programming ........................................................................................................................33
7.7.3 PORT Access .......................................................................................................................33
7.7.4 Channel Attention Access ....................................................................................................34
7.7.5 Bus Error Handling................................................................................................................34
7.7.6 SYSBUS Byte Requirements ............................................................................................... 34
7.7.7 Electrical Interface ................................................................................................................34
7.8 Interrupt Controller ...................................................................................................................35
7.8.1 Overview...............................................................................................................................35
7.8.2 Processor Interrupter............................................................................................................35
7.8.3 VMEbus interrupter............................................................................................................... 36
v
7.8.4 Interrupt Controller Registers ............................................................................................... 36
7.8.4.1 VMEIRQ Enable Register ...................................................................................36
7.8.4.2 VMEIRQ Vector Register ....................................................................................36
7.8.4.3 VMEIRQ Level Register......................................................................................37
7.8.4.4 LOCIRQ Enable Register....................................................................................37
7.8.4.5 ETHIRQ Enable Register....................................................................................37
7.8.4.6 Local IRQ Status Register ..................................................................................38
7.9 IP Controller .............................................................................................................................39
7.9.1 Overview...............................................................................................................................39
7.9.2 IP Expansion Interface.......................................................................................................... 39
7.9.3 IP Interrupts...........................................................................................................................39
7.9.4 Memory Space Address Map...............................................................................................40
7.9.5 I/O & ID Space Address Map ...............................................................................................41
7.9.6 IP Controller Registers..........................................................................................................42
7.9.6.1 IRQ Level A0 Register ........................................................................................42
7.9.6.2 IRQ Level A1 Register ........................................................................................42
7.9.6.3 IRQ Level B0 Register ........................................................................................42
7.9.6.4 IRQ Level B1 Register ........................................................................................43
7.9.6.5 IP Clock Speed Select Register..........................................................................43
7.9.6.6 IP SYNC Clock Select Register ..........................................................................43
7.10 VMEbus Slave Access Controller...........................................................................................45
7.10.1 Overview ............................................................................................................................45
7.10.2 Standard (A24) & Extended (A32) Accesses.................................................................... 45
7.10.3 Short I/O (A16) Accesses..................................................................................................46
7.10.4 Controlling The Window Size ............................................................................................46
7.10.5 Local Address Generation.................................................................................................46
7.10.6 Address Control Registers.................................................................................................47
7.10.6.1 A32VBA - A32 VMEbus Base Address Register ................................................47
7.10.6.2 A32MSK - A32 VMEbus Address Mask Register ...............................................47
7.10.6.3 A24VBA - A24 VMEbus Base Address Register ................................................47
7.10.6.4 A24MSK - A24 VMEbus Address Mask Register ...............................................47
7.10.6.5 A16VBA - A16 VMEbus Base Address Register ................................................47
7.10.6.6 A32LBA - A32 Local Base Address Register......................................................47
7.10.6.7 A24LBA - A24 Local Base Address Register......................................................48
7.10.6.8 ADDRCTL - Address Control Register................................................................48
7.11 Configuration Switch...............................................................................................................49
7.11.1 Configuration Switch Layout.............................................................................................. 49
7.11.2 Configuration Switch Register ...........................................................................................49
7.12 Real Time Clock/Timers.........................................................................................................50
7.12.1 Overview ............................................................................................................................50
7.12.2 Hardware Specific Considerations ....................................................................................50
7.12.3 Programming .....................................................................................................................51
7.13 Parallel Port/Timer..................................................................................................................52
7.13.1 Overview ............................................................................................................................52
7.13.2 Port A Usage...................................................................................................................... 52
7.13.3 Port B Usage...................................................................................................................... 52
7.13.4 Port C Usage......................................................................................................................54
7.13.5 Handshake Pin Usage.......................................................................................................55
7.13.6 MC68230 PI/T Registers ................................................................................................... 55
7.14 Serial Communications Controller..........................................................................................56
vi
7.14.1 Overview ............................................................................................................................56
7.14.2 Serial Clock Sources..........................................................................................................56
7.14.3 Programming .....................................................................................................................57
8. Specifications..................................................................................................................................58
8.1 On-Board Functions.................................................................................................................58
8.2 VMEbus Master........................................................................................................................58
8.3 VMEbus Slave..........................................................................................................................58
8.4 VMEbus System Controller Functions......................................................................................58
8.5 VMEbus Interrupts....................................................................................................................59
8.6 IP Functions .............................................................................................................................59
8.7 Board Configuration .................................................................................................................59
8.8 Operating Environment ............................................................................................................59
Appendix A Data Sheet & Manual References .....................................................................................60
A.1 MC68040/68LC040/68EC040 User's Manual..........................................................................60
A.2 MC68060/68LC060/68EC060 User's Manual..........................................................................60
A.3 82596CA User's Manual ..........................................................................................................60
A.4 53C710 Data Manual & Programmers Guide ..........................................................................60
A.5 DP8570A Data Sheet...............................................................................................................60
A.6 Z85230 User's Manual.............................................................................................................60
A.7 MC68230 Data Sheet...............................................................................................................60
A.8 VMEbus Specification ..............................................................................................................60
A.9 RS422/485 Interface Module User's Manual............................................................................60
A.10 AM29F040 Data Book ............................................................................................................60
A.11 NMC24C02 Data Sheet..........................................................................................................61
A.12 MEM390 Memory Module User's Manual...............................................................................61
A.13 MEM400 Memory Module User's Manual...............................................................................61
A.14 MEM480 Memory Module User's Guide.................................................................................61
A.15 MEM4SD Memory Module User's Guide................................................................................61
A.16 EXP100 Quad IP Expansion User's Manual...........................................................................61
Appendix B CPU Cache Coherency and Bus Snooping.......................................................................62
B.1 BVME4000 (MC68040)............................................................................................................62
B.2 BVME6000 (MC68060)............................................................................................................64
Appendix C Memory Module Pinout......................................................................................................66
Appendix D IP Expansion Interface Pinout ...........................................................................................67
Appendix E Thermal Management .......................................................................................................68
Appendix F Circuit Diagrams................................................................................................................69
vii
List of Figures
Figure Page
Figure 1 Board Layout.............................................................................................................................2
Figure 2 Block Diagram...........................................................................................................................4
Figure 3 PCB Layout.............................................................................................................................11
Figure 4 LK1 Abort Switch Enable Location..........................................................................................12
Figure 5 LK2 Reset Switch Enable Location.........................................................................................12
Figure 6 LK3 VMEbus Reset Out Enable Location ...............................................................................13
Figure 7 LK4 VMEbus Reset In Enable Location..................................................................................13
Figure 8 LK5 CPU Cache Inhibit Location.............................................................................................14
Figure 9 LK6 Cheapernet Heart Beat Enable Location.........................................................................14
Figure 10 LK7,8,9 Ethernet AUI/Cheapernet Select Location...............................................................15
Figure 11 LK10,11,12,14,15 EPROM Size & Type Select Location......................................................15
Figure 12 LK13 SCSI Termination Disable Location.............................................................................16
Figure 13 LK18,19 CPU 5/3.3V Selection Location ..............................................................................16
Figure 14 LK21 SRAM Backup Selection Location...............................................................................17
Figure 15 LK22 VMEbus System Controller Enable Location...............................................................17
Figure 16 Configuration Switch Location...............................................................................................18
Figure 17 JP1 & JP2 Serial Port Connections.......................................................................................19
Figure 18 JP3 Parallel Port Connections ..............................................................................................19
Figure 19 JP4 Optional 10BaseT Connector ........................................................................................20
Figure 20 IP Connector Pin Numbering Viewed from solder side of BVME4000/6000.........................21
Figure 21 Flat Cable Connector Pin Numbering Viewed from front of JP5...........................................21
Figure 22 JP7 CPU Fan Power.............................................................................................................22
Figure 23 JP8 JTAG Connector............................................................................................................22
Figure 24 J1 SCSI Connections............................................................................................................22
Figure 25 J14 SCSI Peripheral Power Connections .............................................................................23
Figure 26 Protection Fuse Positions .....................................................................................................24
Figure 27 Configuration Switch Layout..................................................................................................49
viii
This page is intentionally left blank.
1 BVME4000/6000
1. Introduction
1.1 Scope
This manual provides :-
A getting started guide.
Configuration details.
A user reference guide.
A memory map.
A map of all register locations.
A detailed description of all dedicated registers.
Details of implementation specific considerations for major devices.
General hardware description.
This manual does not provide:-
Detailed data on the operation of the major devices.
Details of VMEbus & IndustryPack™ Specifications.
Information is provided to allow the module to be integrated into a system and configured by the
system software. This User Manual is intended for use by system integrators, service personnel,
software engineers and end users.
Unless otherwise stated, address information is in hexadecimal notation.
The term "IP" is used as an abbreviation for "IndustryPack™" throughout this manual.
1.2 BVME4000 Part Numbers
452-40231/40331 MC68EC040 25/33MHz, VMEbus I/F, ETHERNET, SCSI, IP I/F, 2Mb SRAM
452-42231/42331 MC68040 25/33MHz, VMEbus I/F, ETHERNET, SCSI, IP I/F, 2Mb SRAM
Other versions of the BVME4000 are available to special order, where any of the VMEbus I/F,
ETHERNET, SCSI & IP I/F may be omitted or 512Kb SRAM fitted. Contact your supplier for details.
1.3 BVME6000 Part Numbers
452-40631 MC68EC060 66MHz, VMEbus I/F, ETHERNET, SCSI, IP I/F, 2Mb SRAM
452-42531 MC68060 50MHz, VMEbus I/F, ETHERNET, SCSI, IP I/F, 2Mb SRAM
Other versions of the BVME6000 are available to special order, where any of the VMEbus I/F,
ETHERNET, SCSI & IP I/F may be omitted or 512Kb SRAM fitted. Contact your supplier for details.
1.4 Memory Module Part Numbers
453-82390/83390 MEM390 25(50)/33(66)MHz 4Mbyte DRAM *
453-82403/83403 MEM400 25(50)/33(66)MHz 16Mby te DRAM & 4Mbyte FLASH
453-82404/83404 MEM400 25(50)/33(66)MHz 16Mby te DRAM & 8Mbyte FLASH
453-82482/83482 MEM480 25(50)/33(66)MHz 48Mbyte DRAM *
453-85016/86016 MEM4SD 25(50)/33(66)MHz 16Mbyte SDRAM
453-87064/88064 MEM4SD 25(50)/33(66)MHz 64Mbyte SDRAM
453-87128/88128 MEM4SD 25(50)/33(66)MHz 128Mbyte SDRAM
453-89256/90256 MEM4SD 25(50)/33(66)MHz 256Mbyte SDRAM
Other Memory Module types and options are available, * denotes type not recommended for new
designs. Some Memory Module types can also be "stacked" two high, to increase capacity or mix
memory types. Contact your supplier for details.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 2
2. Overview
2.1 Board Layout
ABORT
RESET
STATUS LEDs
SERIAL
CH. B
SERIAL
CH. A
CHEAPER
NET
68040
or
68060
PRINTER
CONN.
LOW
PROM
MEMORY
MODULE
INTERFACE
VMEbus
P1 CONN.
HIGH
PROM
IP I/O CONN.
2 X 50 WAY
IndustryPack
Site A
IndustryPack
Site B
Figure 1 Board Layout
VMEbus
P2 CONN.
Copyright 1993,1995,1998,2001 BVM Ltd.
3 BVME4000/6000
2.2 Features
! BVME4000 - MC68040 CPU (MC68EC040/68LC040 options).
" 25 MHz and 33 MHz clock speed variants.
" 4096 byte data and instruction caches.
! BVME6000 - MC68060 CPU (MC68EC060/68LC060 options).
" 50 MHz and 66 MHz clock speed variants (25 MHz or 33 MHz bus).
" 8192 byte data and instruction caches.
! 32-bit wide burst fill Dual Ported (with Bus Snooping) memory module interface with NO
capacity limitations allowing many options, for example:
" 8Mbytes of FLASH EPROM (Erasable, Programmable non-volatile storage).
256Mbytes DRAM.
"
! 2Mbyte EPROM pair (16-bit wide), supports 5V FLASH (1Mbyte).
512K/2Mbyte Non-volatile (battery backed) SRAM (32-bit wide).
!
! 2Kbit EEPROM (NMC24C02).
! High Performance DMA driven 5Mbyte/sec SCSI Interface (NCR53C710).
!
! Two 16-bit IP Compatible Sites (Double height 32-bit access supported).
!
!
! Bi-directional Parallel port including one further 24-bit interrupting Counter/timer (MC68230).
!
! VMEbus System Controller Functions.
!
! Available built as a single solution disc based module.
!
High Performance DMA driven Ethernet/Cheapernet (10BaseT option) (82596CA).
" Expansion Connector allowing 4 IP Compatible Site daughter board.
" 8MHz, 32MHz and proprietary high speed 'Source Synchronous Modes' supported.
Two Interrupt driven serial I/O ports - RS232, RS422 and RS485 options (Z85230).
Real Time Clock (Battery backed) Including Tick timer, 2 16-bit timers and non-volatile
configuration RAM (DP8570).
Optimised A32,A24,A16:D32,D16,D08 master/slave VMEbus interface.
VMEbus Interrupter.
"
VMEbus Interrupt handler.
"
" Location monitor - Mailbox Interrupts.
Four level Arbiter (programmable ROR, RWD and SGL).
"
" RESET, SYSCLK generator.
Single slot, 6U form factor.
OS-9, VxWorks, Linux & debug monitor software support.
! Fully compatible to VMEbus specification revision C.1.
2.3 Applications
! VMEbus Main System Processor.
!
!
VMEbus Intelligent I/O Processor.
High Performance Embedded Processor.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 4
&
3. Description
3.1 Block Diagram
50 way
Direct
Connector
SCSI
Controller
68040
or
68060
Memory
Module
P2
SCSI
EPROM
2Mb
16 Bit Wide
Front Panel
BNC or
RJ45
Cheapernet
or 10BaseT
Interface
Ethernet
Controller
Internal Bus
Arbiter
SRAM
512Kb/2Mb
32 Bit Wide
P2
AUI I/F
Dual Serial
Comms
Controller
VMEbus
SYSCON
VMEbus
Interrupter
VMEbus
Slave
VMEbus
Interrupt
Handler
VMEbus
Master
R.T.C.
2 x Timers
IP A IP B
Front Panel
50 way I/O
IP
Interface
Front Panel
50 way I/O
Serial
Buffers
WatchDog
Bus Timers
EEPROM
IP
Expansion
Interface
Parallel I/O
& Timer
Centronics
Buffers
Figure 2 Block Diagram
P2
Serial
14 way
Connector
JP1
14 way
Connector
JP2
P2
Parallel I/O
26 way
Connector
JP3
Copyright 1993,1995,1998,2001 BVM Ltd.
5 BVME4000/6000
3.2 Processor
The BVME4000 is based on the MC68040 32-bit processor from Motorola running at 25 or 33MHz.
This virtual memory processor provides a MC68030 compatible integer processor running
concurrently with an IEEE754 compatible floating-point unit (FPU). In addition two f ully independent
data and instruction demand page m emory management units (MMU's ) and two independent 4Kbyte
caches provide efficient bus interface with a high degree of instruction execution parallelism.
The BVME6000 is similar to the BVME4000, but is based on the MC68060 32-bit processor from
Motorola running at 50MHz with a 25MHz bus. The MC68060 provides a MC68040 compatible integer
processor running concurrently with a MC68040 IEEE754 compatible floating-point unit (FPU). In
addition two fully independent data and instruction MC68040 compatible demand page memory
management units (MMU's) and two independent 8Kbyte caches.
The BVME4000 and BVME6000 are also available in lower cost versions with the
MC68LC040/68LC060, which provide the same functionality as the MC68040/68060, but without the
FPU, and with the MC68EC040/68EC060 which provide the same functionality, but without the MMU
or FPU. The MC68LC060/68EC060 can run at 50 or 66MHz with a 25 or 33MHz bus respectively.
3.3 Memory
The BVME4000/6000 may be fitted with a large variety of 32-bit wide, burst fill m emory devices. The
BVME4000/6000 uses the BVM memory module interface which provides a full 32-bit MC68040/68060
bus, and supports 2/1/1/1 (no wait state) accesses to a variety of standard BVM mem ory modules,
allowing use of memory modules which currently include:
! 8 to 48Mbytes DRAM (5/3/3/3 access at 33MHz bus clock).
! 16 to 512Mbytes DRAM (4/1/1/1 read, 3/2/2/2 write at 25 & 33MHz bus clock).
! 16Mbytes DRAM plus 8Mbyte FLASH EPROM (4/2/2/2 DRAM, 5/2/2/2 FLASH access).
This memory can be dual ported allowing concurrent accesses by both the processor and other
VMEbus masters. These acc esses may be 'snooped' by the processor to maintain cac he coherency.
This, together with the onboard 'location monitor' allows full multipr ocessor comm unication with other
CPU (and DMA) VMEbus cards.
The BVME4000/6000 also provides 2Mbytes (512Kbytes to special order) of battery-backed 32-bit
wide Static RAM, providing a 5 CPU clock cycle access at 25MHz or 33MHz bus clock . This SRAM
may be used for non-volatile storage applications, or as main system mem ory in applications where a
memory module is not fitted. The SRAM can also be dual ported to the VMEbus.
A pair of 32-pin JEDEC pinout sockets provide up to 2Mbytes of 16-bit wide EPROM providing a 10
CPU clock cycle access at 25MHz or 33MHz bus clock. These sockets can support 512K, 1M, 2M, 4M
and 8Mbit EPROM devices, and up to 4Mbit 5V FLASH devices.
3.4 Real Time Clock
The BVME4000/6000 provides a battery backed Real Time Clock using the DP8570 device. This
device is battery backed, and maintains date and time data. The DP8570 can also generate an
interrupt from it's per iodic tim er f rom 1m S to 1 s econd, or f rom two other independent 16-bit tim er s on
chip. The timers offer a resolution of up to 500nS, and can be used in one-shot or periodic interrupt
mode. A small amount of non-volatile storage is also provided for system conf iguration purposes . The
DP8570 is battery backed using a lithium battery giving typically 10 years of non-volatile operation.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 6
3.5 Serial Communications
Two serial communications interfaces ar e provided from a Z85230 SCC device. T he Z85230 provides
both synchronous (SDLC/HDLC) and asynchronous protocols. Asynchronous baud rates of up to
115.2Kbit/s (using the on-board crystal) are supported. Field changeable buff er m odules allow RS232,
RS422 or RS485 electrical interfaces to be selected for either (or both) channels. The two serial
interfaces are available on the front panel, or via the rear P2 connector. The synchronous clock
signals are also available via the P2 connector.
3.6 Parallel Port
An 8-bit, bi-directional I/O port with interrupt driven handshake is provided allowing direct connection to
Centronics devices. This is im plem ented in a 68230 which includes a fur ther 24- bit tim er with interr upt
capability. This device also provides part of the board control functions, and is used to control the
software watchdog function. The parallel port is connected to a dedicated connector near the front
panel, or via the P2 connector.
3.7 SCSI Interface
A SCSI interface is provided built around the NCR53C710. This provides asynchronous transfers of up
to 5Mbytes per second. The 32-bit DMA driven interface allows direct acc ess to the entire memory
map of the BVME4000/6000. The burst mode interface stacks up 16 bytes at a time and transfers
them as a line transfer at up to 4/2/2/2 access speeds at 25MHz bus clock. At 5Mbyte/s this gives a
400nS burst every 3.2µS or 12.5% bus bandwidth requirement. The 53C710 is an intelligent proces s or
in its own right, running SCSI SCRIPTS software. This enables very high level commands to be issued
to the SCSI interface further m inimising processor overhead. The SCSI interface is connected to a
dedicated 50-way connector and is also available via the P2 connector.
3.8 Ethernet Interface
An Ethernet Interface is provided built around the Intel 82596CA. T his provides a 32-bit DMA driven
interface to both Ethernet (via the AUI interface on the P2 connector) and either Cheapernet (via a
front panel BNC) or optionally 10BaseT (via a front panel RJ45). The 32-bit DMA driven interface
allows direct access to the entire memory map of the BVME4000/6000 allowing full packet
management by the 82596CA. Each 32-bit transfer requires 320nS m axim um ( including ar bitration) to
execute the cycle. A transfer will occur no more frequently than every 4µS (4 bytes at 1Mbyte per
second). Thus worst case bus bandwidth requirement is 8% at 25MHz bus clock.
3.9 IP I/O
Two standard IP compatible sites are provided. The IP interface complies fully with the IP
specification. The two sites may be used individually for single IP's which are ac ces s ed as 16-bit wide,
or as a pair for double IP's, which are accessed as 32-bit wide. IP
32MHz, and CPU synchronous speeds. The IP DMA function is not supported by these two sites , but
may be supported on an IP daughter board (see below). The IP ID and I/O s pac es ar e 256bytes each,
and the memory spaces are 8Mbytes. IP vectored interrupts are fully supported and the interrupt levels
may be individually programmed.
An IP expansion bus connector is provided to allow additional IP's to be supported. A further 4 IP's
may be added on a daughter board connected to this expansion interf ace. Two 'virtual IP' sites are
also available for controlling the daughter board IP interfac e. The daughter board m ay include a local
DMA controller and RAM which is accessed thr ough one of the 'virtual IP' s ites, thus s upporting the IP
DMA function.
operation is supported at 8MHz,
Copyright 1993,1995,1998,2001 BVM Ltd.
7 BVME4000/6000
3.10 VMEbus Interface
Full VMEbus system controller functions are provided including SYSCLK drive, Bus tim e out monitor,
SYSRESET drive and an efficient 4 level bus arbiter working in prioritised (PRI), s ingle level (SGL), or
round robin (RRS) arbitration modes.
3.10.1 VMEbus Master
Byte or Word Master accesses may be made to the Standard (A24) and Short I/O (A16) address
spaces, Byte, Word and Longword Master accesses may be made to the Extended (A32) address
space. BVME4000/6000 Longword accesses to the A24 or A16 address space m ay be converted to
two Word cycles, or proceed as a Longword cycle dependant upon the BVME4000/6000 address
space accessed. Read Modify Write (RMW) cycles are supported for all of these accesses.
VMEbus arbitration is normally configured to be Release On Request (ROR) method. This may be
changed to Release When Done (RW D) with a PLD change. Both schemes use FAIR requesting,
ensuring each master has an equal chance of obtaining the bus. Digital bus busy filtering and
arbitration interleaving is used to ensure premium arbitration performance.
3.10.2 VMEbus Slave
The memory module and on-board SRAM are dual ported onto the VMEbus. The VMEbus base
address, size of window and local base address are programmable for the A24 and A32 address
spaces. The BVME4000/6000 responds to Byte and W ord and Longword Slave ac cesses to the A32,
A24 and A16 address spaces.
The BVME4000/6000 can snoop VMEbus slave acces ses if enabled to do so. T hus although the CPU
uses extensive caching, full c oherency is maintained by the CPU providing any data that is 'stale' in
the accessed memory - refer to "Appendix B CPU Cache Coherency and Bus Snooping (on page 62)".
A VMEbus location monitor is also supported in the A16 address space. This is a fixed 256byte
window size, and the VMEbus base address is programm able. A local interrupt can be enabled when
the A16 VMEbus window is accessed.
The BVME4000/6000 is compatible with VMEbus address pipelining and RMW cycles.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 8
3.11 Interrupts
3.11.1 VMEbus Interrupt Handler
The BVME4000/6000 may be configured to respond to VMEbus interrupts on any of the 7 VMEbus
interrupt levels. Each interrupt level may be programmed to be enabled or disabled individually.
A User vectored VMEbus interrupt causes the CPU to reply with a VMEbus Master interrupt
acknowledge cycle. This cycle uses only the that is broadcast in a similar way to the addresses. The
A1,2,3 address lines indicate the address level being handled.
The interrupting device returns an ID vector on the odd data byte. This is used as the us er vector by
the CPU.
3.11.2 Internal Interrupts
Internal CPU interrupts are generated from a variety of sources, as detailed in the table below:
Source Level Type
VMEIRQ7:1 IRQ7:1 Vectored
ACFAIL 7 Auto
ABORT 7 Auto
8570 RTC 6 Auto
68230 TIMER 5 Vectored
MEMORY MODULE 4 Auto
85230 SCC 3 Vectored
53C710 SCSI 3 Auto
68230 PARALLEL 2 Vectored
82596CA ETHERNET 2 Auto
LOCATION MONITOR 1 Auto
IPA, IPB INT0 & INT1 Programmable Vectored
IP EXPANSION I/F Programmable Vectored
3.11.3 VMEbus Interrupter
The BVME4000/6000 may generate VMEbus interrupts on any programmable single level 1-7 and
responds with a software programmable ID to the subsequent interrupt acknowledge cycle. Writing the
ID to the a vector register causes a VMEbus interrupt to be generated on the selected level. The
BVME4000/6000 VMEbus interrupt ID vector may be programmed to suit the application.
Copyright 1993,1995,1998,2001 BVM Ltd.
9 BVME4000/6000
3.12 VMEbus System Controller Functions
The BVME4000/6000 provides a number of system controller functions that may be enabled by
programming the relevant registers, or by link selection.
RESET
Asserted if +5V falls below 4.65V and when a link is installed. VMEbus RESET has a minimum
asserted period of 200mS.
ARBITRATION
The BVME4000/6000 can be programmed/link selected to provide SGL, PRI or RRS arbitration.
SYSCLK
The BVME4000/6000 can be programmed/link selected to provide a 16MHz VMEbus SYSCLK.
BUS TIMER
The BVME4000/6000 can be programmed/link selected to provide a 128µS Bus Timeout BERR
signal.
3.13 Power Supply Monitor/Watchdog
A MAX791 provides power up/power down control for the battery switching for the non-volatile RAM
and processor RESET. It also provides a processor watchdog capability controlled via the Board
Control Register. If enabled, the processor will be reset if the software fails to m aintain pulses to the
watchdog circuit.
3.14 Local Bus Monitor
All bus cycles (including VMEbus arbitration requests) are timed by an on-board timer. If any cycle
takes longer than 64 CPU clock cycles a Transfer Error Abort signal and bus error exception vector
are generated. Thus the processor cannot simply hang-up as a result of invalid addresses being
generated from software. The exception to this is for VMEbus accesses - these are timed by the
VMEbus Timeout monitor.
3.15 Configuration Switch
A 4-bit configuration switch is provided for soft ware bootstrap detection. This switch does not affect
the hardware directly, but is normally used by the software to set up the BVME4000/6000's
configuration registers.
3.16 EEPROM
An NM24C02 serial I2C EEPROM device provides 2Kbits of EEPROM storage for configuration
settings. The NMC24C02 is accessed on the I
2
C serial bus via the Board Control Register.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 10
4. Installation
The BVME4000/6000 module is inserted into a vacant VMEbus slot. If it is to function as the system
controller, then it should be positioned in slot 1. It passes thr ough all VMEbus dais y chained ar bitr ation
signals.
IACK should be jumpered to IAKIN on the backplane at slot 1. All interrupt IAKIN to IAKOUT and BGIN
to BGOUT signals should be jumpered across vacant slots to the right of the module.
If it is not the system controller, it may be located in any of the VMEbus slots to the right of the
VMEbus system controller.
To install the BVME4000/6000:
1. Ensure all backplane jumpers associated with the slot for the BVME4000/6000 are removed.
2. Ensure the BVME4000/6000 module is correctly configured for the target system.
3. If the Parallel interface is to be used, plug in the parallel cable to JP3 (if not using the P2
connections).
4. Connect the SCSI cable to the 50 way SCSI connector on the BVME4000/6000 (if not us ing
the P2 connections), ensure the correct polarity.
5. Insert the BVME4000/6000 module into the rack pushing the VMEbus connector fully home.
6. Secure the BVME4000/6000 into the rack with the two fixing screws top and bottom.
7. Plug in serial cables to JP1 and/or JP2 (if not using the P2 connections).
8. If using Cheapernet, connect the Cheapernet BNC-T connec tor to the BVME4000/6000 BNC
connector or if using the optional 10BaseT, connect the RJ45 connector to the
BVME4000/6000 RJ45 connector.
9. Connect the IP I/O connections to the two 50 way front panel connectors.
10. Ensure that the configuration switch is set up correctly for the software installation.
11. Ensure the correct application EPROM's are fitted.
Removal is the reverse of assembly.
If the test or application software fails, ensure that all installation instructions have been correctly
carried out. Some typical reasons for incorrect operation are:-
1. Socketed components may become dis turbed in transit. Push hom e all soc keted com ponents
where suspect.
2. The BVME4000/6000 module uses the VMEbus Address modifier codes to determine address
significance. Ensure the host CPU module produces the correct address modifier codes.
3. Ensure that all links are conf igured to the default set-up or that any alterations to the default
are correctly configured.
4. Ensure that the VMEbus backplane (if used) is correctly configured with regard to the daisychain signal jumpers and the IACK termination jumpers (if any).
The BVME4000/6000 CPU requires adequate airflow across it to ensur e correct oper ation. A heatsink
may need to be fitted to the CPU - refer to "Appendix E Thermal Managem ent (on page 68)" for more
details.
Copyright 1993,1995,1998,2001 BVM Ltd.
5. Configuration
5.1 PCB Layout
ABORT
RESET
LEDS
SERIAL B
SERIAL A
1
1 2
2
Pin1
LK1
LK2
P
R
I
N
T
E
R
MC68040
OR
MC68060
IC 2
1 2 3
1 2 3
11 BVME4000/6000
M4
M3 M2
VME BUS
CONTROLLER
21
LK5
3V5V
XM1
INTERRUPT
CONTROLLER
ADDRESS
MAP
CONTROLLER
M1
CHEAPERNET
CONFIG
SWITCH
IP A
CONNECTOR
IP B
CONNECTOR
3
2
1
LK6
LK7
2 4 6
1 3 5
2 4 6
1 3 5
LK8
2 4 6
1 3 5
LK9
82596
LANC
NCR53C710
SCSI
CONTROLLER
STATIC RAM
PERIPHERAL
CONTROLLER
L
1
1
2
1 1 1
2 2 2
3 3 3
1 2 3
LK14
1 2 3
LK15
BATTERY
INDUSTRY
PACK
CONTROLLER
LL
KKK
1
01
LOW
PROM
HIGH
PROM
LK21
LK22
1 2
1 2
1
21 2
LK3
LK4
DISK POWER
CONNECTOR
LK13
FUSES
1 2
IP EXPANSION
Figure 3 PCB Layout
Copyright 1993,1995,1998,2001 BVM Ltd.
SCSI
BVME4000/6000 12
5.2 Link and Switch Definitions
The following link definitions s how the links grouped in the sam e orientation as the layout drawing on
the previous page, i.e. with the VMEbus connectors to the right. Link positions m arked with a # show
the default configuration.
Some of the link numbers are not described here, these are for factory use only when configuring
different build variants of the BVME4000/6000 and are not available for user's.
5.2.1 LK1 Abort Switch Enable
LK1
ABORT
RESET
1
MC68040
OR
MC68060
2
IC 2
Figure 4 LK1 Abort Switch Enable
Location
Fitting this link enables the ABORT switch to generate interrupts.
LK1 Function
1 & 2 Fitted # ABORT Switch generates Level 7 Auto-vectored IRQ
1 & 2 Omitted NO IRQ generated from switch
5.2.2 LK2 Reset Switch Enable
LK2
ABORT
1 2
RESET
MC68040
OR
MC68060
IC 2
Figure 5 LK2 Reset Switch Enable
Location
Fitting this link enables the RESET switch to generate a local reset and (optionally) a VMEbus RESET.
LK2 Function
1 & 2 Fitted # RESET switch resets BVME4000/6000 (and VMEbus)
1 & 2 Omitted NO RESET generated from switch
Copyright 1993,1995,1998,2001 BVM Ltd.
5.2.3 LK3 VMEbus Reset Out Enable
LK3
13 BVME4000/6000
XM1
ADDRESS
MAP
CONTROLLER
Figure 6 LK3 VMEbus
Reset Out Enable
PERIPHERAL
CONTROLLER
LOW
PROM
HIGH
PROM
1 2
Location
This link enables the VMEbus RESET to be driven by the BVME4000/6000 RESET signal.
LK3 Function
1 & 2 Fitted # BVME4000/6000 RESET resets VMEbus
1 & 2 Omitted NO VMEbus RESET from BVME4000/6000
5.2.4 LK4 VMEbus Reset In Enable
LK4
XM1
PERIPHERAL
CONTROLLER
This link allows the BVME4000/6000 to be reset from the VMEbus RESET signal.
LK4 Function
1 & 2 Fitted
#
VMEbus RESET resets BVME4000/6000
1 & 2 Omitted NO BVME4000/6000 RESET generated from VMEbus
ADDRESS
MAP
CONTROLLER
LOW
PROM
HIGH
PROM
Figure 7 LK4 VMEbus
Reset In Enable
Location
2
1
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 14
S
L
5.2.5 LK5 CPU Cache Inhibit
LK5
ABORT
RESET
LEDS
MC68040
OR
MC68060
IC 2
M3 M2
VME BUS
CONTROLLER
Figure 8 LK5
CPU Cache
Inhibit Location
21
SERIAL B
INTERRUPT
CONTROLLER
This link disables the MC68040/68060's on chip data and instruction caches to allow (for example)
emulators to be used with the BVME4000/6000.
LK5 Function
1 & 2 Fitted MC68040/68060 CACHES DISABLED
1 & 2 Omitted # MC68040/68060 CACHES ENABLED
5.2.6 LK6 Cheapernet Heart Beat Enable
LK6
SERIAL A
CHEAPERNET
CONFIG
SWITCH
3
2
1
XM1
PERIPHERAL
CONTROLLER
This link allows the CHEAPERNET Heartbeat function to be enabled.
LK6 Function
1 & 2 # Normal operation - Heartbeat Disabled
2 & 3 Heartbeat Enabled
Note: this link is not fitted for the optional 10BaseT operation.
ADDRES
MAP
CONTROL
LOW
PROM
Figure 9 LK6 Cheapernet
Heart Beat Enable
Location
Copyright 1993,1995,1998,2001 BVM Ltd.
5.2.7 LK7,8,9 Ethernet AUI/Cheapernet Select
S
L
15 BVME4000/6000
SERIAL A
LK7
LK8
XM1
PERIPHERAL
CONTROLLER
ADDRES
MAP
CONTROL
Figure 10 LK7,8,9 Ethernet
AUI/Cheapernet Select
Location
LK9
CHEAPERNET
CONFIG
SWITCH
2 4 6
1 3 5
2 4 6
1 3 5
2 4 6
1 3 5
LOW
PROM
These links allow selection between CHEAPERNET (via front panel BNC c onnector) and ET HERNET
AUI (via P2 connector). They must all be set in conjunction.
LK7,8,9 Function
1 & 3, 2 & 4
#
CHEAPERNET via front panel BNC
3 & 5, 4 & 6 ETHERNET AUI via P2 connector
Note: these links are not fitted for the optional 10BaseT operation as it is permanently selected.
5.2.8 LK10,11,12,14,15 EPROM Size & Type Select
LK12
SERIAL A
LK14
LK15
CHEAPERNET
CONFIG
SWITCH
LK11
XM1
PERIPHERAL
CONTROLLER
1 1 1
2 2 2
3 3 3
1 2 3
1 2 3
LK10
ADDRESS
MAP
CONTROLLER
Figure 11
LK10,11,12,14,15
EPROM Size & Type
Select Location
LOW
PROM
These links selects the size of EPROM in the IC44/45 32-pin EPROM sockets. A 27C512 (28-pin)
EPROM should be fitted to the lower 28-pins of the socket (pins 1, 2, 31 & 32 unused).
LK10 LK11 LK12 LK14 LK15 Function
1 & 2 1 & 2 1 & 2 1 & 2 1 & 2 27C512 (512Kbit) or 27C010 (1Mbit) devices
2 & 3 1 & 2 1 & 2 1 & 2 1 & 2 27C020 (2Mbit) devices
2 & 3 2 & 3 1 & 2 1 & 2 1 & 2 27C040 (4Mbit) devices
2 & 3 2 & 3 2 & 3 1 & 2 1 & 2 27C080 (8Mbit) devices
2 & 3 2 & 3 2 & 3 2 & 3 2 & 3 AM29F010 / 020 / 040 Write Enable
2 & 3 1 & 2 2 & 3 2 & 3 2 & 3 AM29F010 / 020 / 040 Write Protect
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 16
5.2.9 LK13 SCSI Termination Disable
LK13
PROM PROM
Figure 12 LK13 SCSI
1 2
BATTERY
Termination Disable Location
This link allows the SCSI bus terminators to be enabled on the BVME4000/6000. T his is necessary if
the BVME4000/6000 is at the end of the SCSI bus cable, otherwise the terminators should be
disabled.
LK13 Function
1 & 2 Omitted # SCSI bus terminated on BVME4000/6000
1 & 2 Fitted NO SCSI bus termination on BVME4000/6000
5.2.10 LK18,19 CPU 5/3.3V Selection
LK18
ABORT
RESET
LEDS
MC68040
OR
MC68060
IC 2
M3 M2
VME BUS
CONTROLLER
Figure 13
LK18,19 CPU
5/3.3V Selection
Location
SERIAL B
5V
1 2 3
1 2 3
3V
INTERRUPT
CONTROLLER
LK19
These are factory set links – when a 68040 series CPU is fitted, 5V is s elected, when a 68060 series
CPU is fitted 3.3V is selected. They must all be set in conjunction.
Setting these links incorrectly will cause damage to the CPU device.
LK18,19 (5V/3V) Function
1 & 2 5 VOLTS SELECTED FOR 68040 SERIES
2 & 3 3.3 VOLTS SELECTED FOR 68060 SERIES
Copyright 1993,1995,1998,2001 BVM Ltd.
5.2.11 LK21 SRAM Backup Selection
LK21
17 BVME4000/6000
XM1
ADDRESS
MAP
CONTROLLER
Figure 14 LK21 SRAM
PERIPHERAL
CONTROLLER
LOW
PROM
HIGH
PROM
1
2
Backup Selection
Location
This link enables the SRAM to be back ed up by the on-board battery. The SRAM is always back ed up
by the 0.1F Memory Capacitor and the VMEbus STDBY supply.
LK21 Function
1 & 2 Fitted SRAM is backed up by battery or MEMCAP/VMEbus STDBY
1 & 2 Omitted # SRAM is only backed up by MEMCAP/VMEbus STDBY
5.2.12 LK22 VMEbus System Controller Enable
LK22
XM1
PERIPHERAL
CONTROLLER
This link forces the BVME4000/6000 to be the VMEbus System Controller, so the BVME4000/6000
performs as the VMEbus arbiter, drives VMEbus SYSCLK and VMEbus BCLR. The norm al selection
for this function is in the Board Control Register when not overridden by this link - refer to "7.13.3 Port
B Usage (on page 52)". Omitting this link is typically required to ensure that the VMEbus SYSCLK
signal is driven as the VMEbus RESET signal is de-asserted.
LK22 Function
1 & 2 Omitted BVME4000/6000 VMEbus System Controller ENABLED
1 & 2 Fitted # BVME4000/6000 VMEbus System Controller set in BCR
ADDRESS
MAP
CONTROLLER
LOW
PROM
HIGH
PROM
Figure 15 LK22 VMEbus
System Controller
Enable Location
1 2
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 18
5.2.13 Configuration Switch
PERIPHERAL
CONTROLLER
LOW
CHEAPERNET
CONFIG
SWITCH
1
2
3
4
82596
LANC
PROM
Figure 16 Configuration
Switch Location
This switch can be read by software to indicate system configuration options to the boot strap routines.
A switch ON selects a logical 0 f or a bit and a switch OFF selects a logical 1 for a bit. Switch pole 1
relates to Bit 3, switch pole 2 to Bit 2, switch pole 3 to Bit 1, and switch pole 4 to Bit 0 in the
BVME4000/6000 Configuration Switch Register - refer to "7.11.2 Configuration Switch Register (on
page 49)".
5.3 Indicators
5.3.1 Green LED - RUNNING
The GREEN RUNNING LED indicates that the BVME4000/6000 is running valid code. When
extinguished, the processor is either halted or stopped. The LED will also dim when the pr ocessor is
executing an RTE instruction, stacking an exception frame or doing an MMU table search.
5.3.2 Red LED - VMEbus Master Access
The RED MASTER LED indicates that the BVME4000/6000 is currently an active VMEbus master.
Copyright 1993,1995,1998,2001 BVM Ltd.
19 BVME4000/6000
6. Connector Pinouts
6.1 JP1 & JP2 Serial Port Connections
JP1 and JP2 carry the serial port signals for Serial Channel A and Serial Channel B respectively. JP1
(Serial Channel A) is the lower connector. T he layout is designed to connect dir ec tly to a s tandar d 25way connector as shown:
The pinout numbering conventions are
different for the two styles of connector (see
diagram). However, the pinout is arranged to
give a one to one connection to a 25-way Dtype connector when using Insulation
Displacement Connectors (IDC) and ribbon
cable.
Not all the RS232 signals defined for a 25
way connector are supported by the
BVME4000/6000. The cable assembly
should be built such that pin 1 on the 14 way
connector connects to pin 1 of the 25 way. A
14 way ribbon cable is used leaving pins 8 13 and 21 - 25 unconnected.
N/C
N/C
N/C
N/C
N/C
N/C
N/C
14
12
10
8
6
13
11
9
7
5
34
12
GND
DTR
RTS
CTS
TxD
RxD
GND
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
GND
7
DTR
6
RTS
5
CTS
4
TxD
3
RxD
2
GND
1
Figure 17 JP1 & JP2 Serial Port Connections
The above assumes standard RS232 driver s are fitted to the BVME4000/6000. If RS422 or RS485
interface modules are fitted refer to the RS422/RS485 INT ERFACE MODULE docum entation detailed
in the "A.9 RS422/485 Interface Module (on page 60)" section of this manual .
6.2 JP3 Parallel Port Connections
JP3 carries the parallel port signals, and the layout is designed to connect directly to a standard 36way connector as shown:
The pinout numbering conventions
are different for the two styles of
10
11
12
13
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
connector (see diagram). However,
20
the pinout is arranged to give a one
21
to one connection to a 36-way delta
22
printer connector when using
23
Insulation Displacement
24
Connectors (IDC) and ribbon cable.
25
26
Not all the signals defined for a 36
27
way connector are supported by
28
the BVME4000/6000. The cable
29
assembly should be built such that
30
pin 1 on the 26 way connector
31
connects to pin 1 of the 36 way. A
32
26 way ribbon cable is used leaving
33
pins 14 - 18 and 32 - 36
34
unconnected.
35
36
/STROBE
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
/ACKNOW
BUSY
N/C
N/C
11
13
15
17
19
21
23
25
GND
1
3
5
7
9
2
4
6
8
10
12
14
16
18
20
22
24
26
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N/C
N/C
/STROBE
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
/ACKNOW
BUSY
Figure 18 JP3 Parallel Port Connections
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 20
6.3 JP4 Cheapernet Connector
JP4 provides a 50Ω BNC connection to a 'Cheapernet' (IEEE802.3 10Base2) network.
When connecting to a network it is important that the bus topology is preser ved. The Cheapernet bus
is a multidrop bus with 50Ω terminator s at each end. Ideally each station on the bus has a zero length
stub connecting from the cable to the transceiver in the s tation. In practice, connection to the c able is
made using a BNC T-piece connected to the BNC connector. The cable is broken at the point of
contact and each new end is connected to the T-piece.
If the BVME4000/6000 is to be removed from the network, this is simply accomplished by
disconnecting the BVME4000/6000 BNC connector (JP4) from the T-piece, leaving the T-piece
connected to the cable.
All cheapernet cabling should use RG-58 type cable. It is important to ensure that both ends of the
cable are terminated using 50Ω BNC terminators.
Note: JP4 may be replaced by an optional 10BaseT RJ45 connection.
6.4 JP4 Optional 10BaseT Connector
The BVME4000/6000 may be fitted with an optional 10BaseT (twisted pair) Ethernet m odule. In this
case the 10BaseT connection is permanently selected and the AUI is not available. The JP4 BNC
connection is replaced with an RJ45 connector with the standard IEEE802.3 10BaseT pinout as
shown:
TD+
TD-
RD+
RD-
Figure 19 JP4 Optional 10BaseT Connector
1
2
3
4
5
6
7
8
Copyright 1993,1995,1998,2001 BVM Ltd.
21 BVME4000/6000
6.5 JP5A/B IP A/B Connections
Each of the 50 pins on each I/O connector for the two IP, slots A and B, connects to a lik e-num bered
pin on the two corresponding flat cable connectors, JP5A and JP5B on the BVME4000/6000 front
panel. The IP I/O connector, the BVME4000/6000 flat cable c onnectors, and the wires on the r ibbon
cables are all numbered identically from 1 to 50.
Pin 1 on IP and BVME4000/6000 connectors are marked with a square pad, observable from the
solder side of the respective board. Pin 1 is shown on JP5 by a triangle etched into the connector
body. Pin 1 is typically marked on ribbon cable with a red stripe and on ribbon cable connectors with a
manufacturer's mark, often a moulded textured triangle.
Caution: This consistent pin numbering system is not maintained with many mass-terminated
connectors. Each type of connector has its own intrinsic pin numbering system. Systems
integrators or users making their own cables must be certain which pin corresponds to which
signal.
The pin assignment of the IP I/O connector is f ixed by the connector manufacturer and repeated in the
IP Specification. This assignment is shown below.
25
50
135791113
246810121415161718192021222324
26283032343638
2729313335373940414243444546464849
Figure 20 IP Connector Pin Numbering
Viewed from solder side of BVME4000/6000
The pin assignment of the 50-way flat cable connectors JA and JB are shown below:
29 31 33 35 37 39 41 43 45 47 49
25 27
29 31 33 35 37 39 41 43 45 47 49
25 27
1 3 5 7 9 11 13 15 17 19 21 23
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
2
1 3 5 7 9 11 13 15 17 19 21 23
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
2
Figure 21 Flat Cable Connector Pin Numbering
Viewed from front of JP5
JP5B
JP5A
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 22
6.6 JP7 CPU Fan Power
JP7 is a power connection for a CPU fan (if f itted). Nor mally this will not be required,
THERM1
THERM0
+12V
GND
+5V
but in environments where the air-flow is not sufficient, the airflow can be
supplemented in this way. When a 68060 series CPU is being used, it's thermal
output signals for variable-speed fans are also available on this connec tor. Refer to
"Appendix E Thermal Management (on page 68)" for more details.
Figure 22 JP7 CPU Fan Power
6.7 JP8 JTAG Connector
JP8 is a JTAG connection via a 2 x 5 way header, the pinout matching the
TCK
TDS
TDI
TDO
GND
GND
Vcc
GND
/ENBL/TRST
MACH programming lead. This is for factory use only, to program the
internal BVME4000/6000 logic devices.
Figure 23 JP8 JTAG Connector
6.8 J1 SCSI Connections
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
9
7
5
3
1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N/C
GND
GND
GND
GND
GND
GND
GND11
GND
GND
GND
GND
GND
/REQ
/CD
/SEL
/MSG
/RST
/ACK
/BSY
GND
/ATN
GND
GND
TERM PWR
GND
GND
GND
/DP
/D7
/D6
/D5
/D4
/D3
/D2
/D1
/D0
50/IO
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
J1 carries the SCSI interface signals. The connector pinout allows
a 50 way IDC and ribbon cable assembly to be directly
connected. If necessary a standard 50-pin to 68-pin SCSI-1 to
SCSI-3 adapter may be used to adapt to 68-pin SCSI devices.
Figure 24 J1 SCSI Connections
Copyright 1993,1995,1998,2001 BVM Ltd.
23 BVME4000/6000
6.9 J14 SCSI Peripheral Power Connections
J14 provides a power pick up connection for SCSI devices integrated within
+12V
GND
+5V
GND
+12V+5V
a module with the BVME4000/6000. It can provide up to 2A of +5V and 2A
of +12V. The pinout is arranged to be symmetrical allowing the mating
connector to be plugged either way around.
Figure 25 J14 SCSI Peripheral Power Connections
6.10 P2 I/O Connections
P2 is a 96 way, DIN-41612 connector consisting of 3 rows of 32 pins . The centre row (Row b) ca rries
VMEbus 32-bit extension signals. The other two rows carry BVME4000/6000 specific I/O connections:
P2 Connection
Row a Row c
1 TxDA RxDA
2 RTSA CTSA
3 DTRA DCDA
4 SCLKOUTA SCLKINA
5 TxDB RxDB
6 RTSB CTSB
7 DTRB DCDB
8 SCLKOUTB SCLKINB
9 +12V GND
10 AUI-DO+ AUI-DO11 AUI-DI+ AUI-DI12 AUI-COLL+ AUI-COLL13 GND GND
14 SCSI-IO SCSI-REQ
15 SCSI-CD SCSI-SEL
16 SCSI-MSG SCSI-RES
17 SCSI-ACK SCSI-BSY
18 SCSI-ATN SCSI-TERM
19 GND GND
20 SCSI-DP SCSI-D7
21 SCSI-D6 SCSI-D5
22 SCSI-D4 SCSI-D3
23 SCSI-D2 SCSI-D1
24 SCSI-D0 GND
25 GND +5V
26 PIO-7 PIO-6
27 PIO-5 PIO-4
28 PIO-3 PIO-2
29 PIO-1 PIO-0
30 /PIO-STRB PIO-ACK
31 PIO-BUSY GND
32 N/C N/C
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 24
6.11 Protection Fuses
The connections on the BVME4000/6000 which provide output power are protected with fus es. T hese
are surface-mounted fus es, and the BVME4000/6000 should be returned to factory for repair if any of
these fuses blows. For ref erence, the following is a list of the fuses, their functions, positions, r ating
and type.
Location
(see below)
CHEAPERNET
CONFIG
SWITCH
Function Rating Type
(LittleFuse)
F1 SCSI TERM PWR 1.5A ALF II 42901.5
F2 ETHERNET -9V 200mA ALF II 429.200
F3 J14 +5V 2A ALF II 429002
F4 J14 +12V 2A ALF II 429002
F5 IP A +12V 1A ALF II 429001
F6 IP B +12V 1A ALF II 429001
F7 IP B +5V 2A ALF II 429002
F8 IP A -12V 1A ALF II 429001
F9 IP B -12V 1A ALF II 429001
F10 IP A +5V 2A ALF II 429002
F2 F9 F6 F1 F3 F4 F7 F10 F8 F5
PERIPHERAL
CONTROLLER
LOW
PROM
HIGH
PROM
FUSES
82596
LANC
Figure 26 Protection Fuse Positions
Copyright 1993,1995,1998,2001 BVM Ltd.
25 BVME4000/6000
7. Programming
7.1 Address Map
The Address Map for the BVME4000/6000 is shown below. The BVME4000/6000 is byte addressed;
each location addresses an 8-bit value. The BVME4000/6000 supports full 32-bit addressing for all
four Local Bus Masters (the MC68040/68060 CPU, the 82596CA LANC, the 53C710 SCSI Controller
and the VMEbus Slave Interface).
Some devices (IP memory, EPROM, SRAM, VMEbus A24) are dual mapped. This is to allow the
Transparent Translation registers in the MC68040/68060 to provide alternative cache modes for
accesses to these devices. The Cache Mode column is suggested cache mode, the hardware
provides no implicit cache mode control.
Address Range Device Size Width Cache Mode Notes
00000000 - variable Memory Module or
SRAM
variable - CFFFFFFF VMEbus - A32:D32 up to 3328Mb D32 write through 2
D0000000 - DFFFFFFF VMEbus - A32:D16 256Mb D16 write through
E0000000 - E7FFFFFF IP Memory
(up to 8 IPs)
E8000000 - E8FFFFFF EPROM 16Mb
E9000000 - E9FFFFFF SRAM (alternate) 16Mb
EA000000 - ECFFFFFF Reserved 48Mb
ED000000 - EDFFFFFF VMEbus - A24:D32 16Mb D32 write through 5
EE000000 - EEFFFFFF VMEbus - A24:D16 16Mb D16 write through 5
EF000000 - EFFFFFFF Reserved 16Mb
F0000000 - F7FFFFFF IP Memory
(up to 8 IPs)
F8000000 - F8FFFFFF EPROM 16Mb
F9000000 - F9FFFFFF SRAM (alternate) 16Mb
FA000000 - FCFFFFFF Reserved 48Mb
FD000000 - FDFFFFFF VMEbus - A24:D32 16Mb D32 non-c ac hed serial 5
FE000000 - FEFFFFFF VMEbus - A24:D16 16Mb D16 non-cached serial 5
FF000000 - FFFFFFFF I/O see I/O map 16Mb non-cached serial
variable D32 copyback 1,2,4,6
128Mb D16:D32 write through 5
D16 write through 4,5
(2Mb valid)
D32 write through 3,5
(2Mb valid)
128Mb D16:D32 non-cached serial 5
D16 non-cached serial 4,5
(2Mb valid)
D32 non-cached serial 3,5
(2Mb valid)
NOTES:
1 If 'RAMLO' is set, then accesses to the bottom 512Kb/2Mb of this space access the Battery Backed SRAM.
2 The boundary between these spaces depends on how muc h memory is fitted to the memory module. Any space
3 If no memory module is fitted, this SRAM can be dual mapped, s ee note 1. The SRAM is always ac cessible at t his
4 For the first two accesses after RESET the E PROM is dual mapped at 00000000.
5 These spaces are dual mapped in order to allow different caching modes to be s et up using the MC68040/68060's
6 The caching mode is programmable on 16Mb boundaries. Therefore if the amount of on board memory is not
down here that is not decoded by the SRAM (if 'RAMLO' is s et) or the memory module is decoded as a VMEbus
A32:D32 access. This can be overridden if 'VMELO' is c lear, in which case the bott om 256Mb are decoded as onboard (SRAM or memory modul e) accesses only.
location.
Transparent Translation Registers.
divisible by 16Mb, the bottom bit of the VMEbus A32:D32 space will have to be copy back c ached. THI S MAY GIVE
CACHE COHERENCY PROBLEMS as the processor is unable to s noop VMEbus space. In this case locate t he
VMEbus A32:D32 devices on a 16Mbyte boundary which will allow the transparent translation regist ers to be set up
to give a coherent caching m ode.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 26
7.1.1 I/O Address Map
Address Range Device Size Width
FF000000 - FF0FFFFF SCSI Controller 1Mb D32
FF100000 - FF1FFFFF Ethernet Controller (LANC) 1Mb D32
FF200000 - FF2FFFFF Interrupt Control 1Mb D8(OLW)
FF300000 - FF3FFFFF IP Control 1Mb D8(OLW)
FF400000 - FF4FFFFF VME Slave Access Control 1Mb D8(OLW)
FF500000 - FF5FFFFF Configuration Switch 1Mb D8(OLW)
FF600000 - FF7FFFFF Reserved 2Mb
FF800000 - FF8FFFFF IP I/O/ID space
(up to 8 IP's)
FF900000 - FF9FFFFF RTC 1Mb D8(OLW)
FFA00000 - FFAFFFFF Parallel Port 1Mb D8(OLW)
FFB00000 - FFBFFFFF SCC 1Mb D8(OLW)
FFC00000 - FFDFFFFF Reserved 2Mb
FFE00000 - FFEFFFFF VMEbus A16 1Mb (64K wraps) D32
FFF00000 - FFFFFFFF VMEbus A16 1Mb (64K wraps) D16
1Mb D16:D32
7.2 Memory Module
Base Address : 00000000
Size : Memory Module Dependent.
The BVME4000/6000 provides a site for BVM Memory Modules - refer to "Appendix C Memory
Module Pinout (on page 66)" for details. These modules are available in various configurations
(DRAM, SRAM, FLASH) and sizes and access speeds. Refer to the relevant Memory Module
documentation detailed in the "Appendix A Data Sheet & Manual Referenc es (on page 60)" sec tion of
this manual for details of the configuration.
The Memory Module Interface is 32-bits wide (though byte addressed) and supports Cache LINE
transfers. Thus 'zero wait state' operation is supported; giving the MC68040/68060 optimum
performance of 2/1/1/1 clock cycles per transf er. Thus 16 bytes of data can be transfer red in 5 clock
cycles (80Mbyte/sec @ 25MHz bus clock). Refer to the relevant Memory Module Manual for actual
memory performance.
The Memory Module provides a 'mem ory present' (/MEMO K) signal during the firs t c ycle of an acces s
that it decodes. Thus the BVME4000/6000 address decoder automatically handles different size
Memory Modules. Any accesses (for addresses up to CFFFFFFF) that are not decoded by the
Memory Module, generate a VMEbus A32:D32 master access (except if VMELO is clear, in which
case the bottom 256Mb are decoded as on- board accesses only) - r efer to "7.3.6 A32:D32 ( on page
28)" for more details.
Copyright 1993,1995,1998,2001 BVM Ltd.
27 BVME4000/6000
7.3 VMEbus Master Access
The BVME4000/6000 can access VMEbus as a bus mast er. Depending on the Address Range used,
different types of access are performed.
VMEbus specifies three basic Address Mode schemes - A16 (Short I/O), A24 (Standard) and
A32 (Extended). The BVME4000/6000 supports all of these modes.
VMEbus also specifies three basic Data Transfer schemes - D08(EO), D16 and D32. The
BVME4000/6000 supports all these modes.
The BVME4000/6000 does not support Block transfers or A64:D64.
7.3.1 A16:D16 (D08EO)
Base Address : FFFF0000.
Size : 64Kbyte.
Accesses to this area perf orm a Short I/O access to VMEbus with LW ORD inactive. Line and Long
Word accesses are automatically broken down to Word (D16) cycles. Byte accesses produce a
D08(EO) cycle. These accesses only involve signals available on the P1 VMEbus Connector.
The following Address Modifier (AM) codes are generated:
CPU Supervisor Data Access = $2D
CPU User Data Access = $29
7.3.2 A16:D32
Base Address : FFEF0000.
Size : 64Kbyte.
Accesses to this area perf orm a Short I/O access to VMEbus with LWORD dependent on the acc ess
type. Line and Long Word accesses pr oduce a D32 ( LWORD active) cycle. Word ac ces s es pr oduc e a
D16 (LWORD inactive) cycle. Byte accesses produce a D08(EO) cycle. These accesses involve
signals on both P1 and P2, therefore, a 'P2' Backplane is required.
The following Address Modifier (AM) codes are generated:
CPU Supervisor Data Access = $2D
CPU User Data Access = $29
7.3.3 A24:D16 (D08EO)
Base Address : FE000000 or EE000000.
Size : 16Mbyte.
Accesses to this area perf or m a Standard Address access to VMEbus with LWORD inactive. Line and
Long Word ac cesses are autom atically broken down to W ord (D16) cycles. Byte access es produce a
D08(EO) cycle. These accesses only involve signals available on the P1 VMEbus Connector.
The following Address Modifier (AM) codes are generated:
CPU Supervisor Program Access = $3E
Data Access = $3D
CPU User Program Access = $3A
Data Access = $39
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 28
7.3.4 A24:D32
Base Address : FD000000 or ED000000.
Size : 16Mbyte.
Accesses to this area perf or m a Standard Address access to VMEbus with LWO RD dependent on the
access type. Line and Long Word ac cesses produce a D32 (LW ORD active) cycle. Word accesses
produce a D16 (LW ORD inactive) cycle. Byte accesses produce a D08(EO) cycle. These accesses
involve signals on both P1 and P2, therefore, a 'P2' Backplane is required.
The following Address Modifier (AM) codes are generated:
CPU Supervisor Program Access = $3E
Data Access = $3D
CPU User Program Access = $3A
Data Access = $39
7.3.5 A32:D16
Base Address : D0000000.
Size : 16Mbyte.
Accesses to this area perform an Ex tended Address access to VMEbus with LW ORD inactive. Line
and Long Word accesses are automatically broken down to Word (D16) cycles. Byte accesses
produce a D08(EO) cycle. These accesses involve signals on both P1 and P2, therefore, a 'P2'
Backplane is required.
The following Address Modifier (AM) codes are generated:
CPU Supervisor Program Access = $0E
Data Access = $0D
CPU User Program Access = $0A
Data Access = $09
7.3.6 A32:D32
Base Address : Immediately above the Memory Module, or 10000000 (if VMELO is
clear).
Size : Maximum 3328Mbyte (Memory Module Dependent).
Accesses to this area perf or m a Standard Address access to VMEbus with LWO RD dependent on the
access type. Line and Long Word ac cesses produce a D32 (LW ORD active) cycle. Word accesses
produce a D16 (LW ORD inactive) cycle. Byte accesses produce a D08(EO) cycle. These accesses
involve signals on both P1 and P2, therefore, a 'P2' Backplane is required.
This address space c an follow on contiguously from the top of a memory module, or the SRAM (if
RAMLO is set), or can be set to star t at a fixed base address (if VMELO is clear ). This allows for a
fixed partitioning of on-board and off - boar d memory for operating systems with this requir ement. Refer
to "7.10 VMEbus Slave Access Controller (on page 45)" for RAMLO and VMELO settings.
The following Address Modifier (AM) codes are generated:
CPU Supervisor Program Access = $0E
Data Access = $0D
CPU User Program Access = $0A
Data Access = $09
Copyright 1993,1995,1998,2001 BVM Ltd.
29 BVME4000/6000
7.4 SRAM
Base Address : E9000000 or F9000000.
Size : 512K/2Mby te.
The 512Kbytes or 2Mbytes of SRAM is 32-bits wide, and provides a 5 CPU clock cycle access . The
SRAM can be accessed at the above two locations, which provide f or different cache regions f or the
same mem ory. Normally the MC68040/68060 will be set-up so that accesses in the region E9000000 E9FFFFFF are write-through cached, and accesses in the region F9000000 - F9FFFFFF are noncached with bus-serialised access.
The SRAM is normally backed up by an on-board m emory storage capacitor , and typically is used for
non-volatile storage applications such as a RAM-disc. In this case, the SRAM can retain it's data for up
to 7 days. If link selected to enable backup from the on-board battery, then the data can be retained
for up to 2.5 years, allowing also for the supply to the Real Time Clock - see "5.2.11 LK21 SRAM
Backup Selection (on page 17)". T he SRAM is also backed-up fr om the VMEbus ST DBY line. W hen
using the VMEbus STDBY line, retention time is dependant on the external source.
The SRAM can also be mapped to appear at the bottom 512K/2Mbytes of the memory map for boards
without a memory module fitted by setting RAMLO. In this case the SRAM is used as main system
memory, and normally will be treated as copy-back c ached m em ory for m axim um perf orm ance. Refer
to "7.10 VMEbus Slave Access Controller (on page 45)" for RAMLO setting.
7.5 EPROM
Base Address : E8000000 or F8000000.
Size : 2Mbyte.
The BVME4000/6000 provides 2 x 32-Pin EPROM JEDEC compatible sockets that may be link
selected to accept either 64K8, 128K8, 512K8 or 1024K8 EPROM devices (e.g. 27C512, 27C010,
27C020, 27C040 or 27C080), providing 64K-2Mbytes of EPROM or 512K8 AM29F040 s ingle-voltage
FLASH EPROM devices, providing 1Mbyte of on-board programmable FLASH EPROM memory.
The EPROM space is 16-bits wide, and provides a 10 CPU cloc k cycle access. 90nS or faster devices
must be used at 33MHz, 120nS devices may be used at 25MHz bus clock. The EPROM can be
accessed at the above two locations, which provide for different cac he regions for the s ame m emor y.
Normally the MC68040/68060 will be set-up so that accesses in the region E8000000 - E8FFFFFF are
write-through cached, and accesses in the region F8000000 - F8FFFFFF are non-cached with busserialised access.
The EPROM is also mapped at the bottom of the memory map for the firs t two cycles after a reset.
This is to allow for the MC68040/68060 to fetch the initial program counter and stack pointer from the
first two longword locations in the EPROM.
When AM29F040 devices are fitted in these sockets, they can be accessed word-wide for
programming, erasing etc.. This means that effec tively the sector sizes are 128Kbytes (64Kbytes per
device), and they can be programmed/erased in parallel. For full programming details, refer to the
AMD AM29F040 documentation detailed in the "A.10 AM29F040 (on page 60)" section of this manual.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 30
7.6 SCSI Controller
7.6.1 Overview
The SCSI Interface uses the NCR53C710. This provides asynchronous transfers of up to 5Mbytes per
second and synchronous transfers of up to 10Mbytes per second. The 32-bit DMA driven interface
allows direct access to the entire memory map of the BVME4000/6000. The burst mode interface
stacks up 16 bytes at a time and transfers them as a line transfer at up to 4/2/2/2 access s peeds at
25MHz bus clock. This gives a 400nS burst every 3.2µS (at 5Mbyte/s) or 12.5% bus bandwidth
requirement.
The 53C710 is an intelligent Processor in its own right, running SCSI SCRIPTS software. This enables
very high level commands to be issued to the SCSI interface further minimising processor overhead.
7.6.2 Programming
The 53C710 is controlled using the 64 registers defined in section "7.6.4 SCSI Controller Registers (on
page 31)". Transfers with the SCSI bus ar e conduc ted independently of the m ain CPU. T he main CPU
sets up various parameters in the 53C710's registers, points the 53C710 at the start of a SCSI
SCRIPTS routine and tells it to run. Upon term ination the 53C710 interrupts the main CPU and waits
for a new start address. The main CPU can examine the res ults of the operation by interrogating the
53C710 registers.
The 53C710 can access the entire BVME4000/6000 address space, including becoming VMEbus
master. It access es memory for two purposes: SCRIPT S code fetches and DMA accesses for SCSI
data transfers.
Note that the 53C710 is configured for Big Endian Mode. T his can affect addressing in f airly subtle
ways. For full programming details, refer to the 53C710 documentation detailed in the "A.4 53C710 (on
page 60)" section of this manual.
Refer to "Appendix B CPU Cache Coherency and Bus Snooping (on page 62)" for details on Cache
Coherency Implications (snooping) while the 53C710 is a bus master.
Refer to "7.8 Interrupt Controller (on page 35)" for details of Interrupt generation by the 53C710.
7.6.3 Hardware Specific Considerations
The raw SCSI clock (SCLK) is driven with 40MHz. Thus the CF(1-0) bits in the DCNTL register must
be set to 00 (default value). This gives a core clock of 20MHz and a SCSI-1 synchronous transf er rate
of 5Mb/s. Optionally, the SSCF(1-0) bits in the SBCL may be set to 01 to give a SCSI-2 synchronous
transfer rate of 10Mb/s.
The 53C710 is hardware configured for Bus Mode 2. The following need to be set for correct operation
of the bus interface:
The first access to the 53C710 must be to set EA bit in DCNTL (This enables the 53C710 to
generate TA for slave cycles).
The TT1 bit of CTEST7 must be set (indicates TT1 pin cleared when bus master).
The TT0 bit of DMODE must be clear (indicates TT0 pin cleared when bus master).
The FC(2-1) bits of DMODE should be set to 10 (indicates Supervisor Data Access).
The PD bit of DMODE should always be clear (indicating Supervisor Data for all accesses).
The SM bit of CTEST8 must be clear (snoop control only driven as master).
The FA bit of DCNTL should always be clear (no 'fast' arbitration).
The BVME4000/6000 does not support differential SCSI transf ers thus the DIFF bit of CT EST7 must
always be clear.
Copyright 1993,1995,1998,2001 BVM Ltd.
31 BVME4000/6000
7.6.4 SCSI Controller Registers
Address Size Read Write Regi ster Description
FF000000 B R/W SIEN S CS I Interrupt Enable
FF000001 B R/W SDID SCSI Destination ID
FF000002 B R/W SCNTL1 SCSI Control 1
FF000003 B R/W SCNTL0 SCSI Control 0
FF000004 B R/W SOCL SCSI Output Control Latch
FF000005 B R/W SODL SCSI Output Data Latch
FF000006 B R/W SXFER SCSI Trans fer
FF000007 B R/W SCID SCSI Chip ID
FF000008 B R/W SBCL SCSI Bus Control Lines
FF000009 B R SBDL SCSI Bus Data Lines
FF00000A B R SIDL SCSI Input Data Latch
FF00000B B R/W* SFBR SCSI First Byte Received (Wri te Restrictions apply)
FF00000C B R SSTAT2 SCSI Status 2
FF00000D B R SSTAT0 SCSI Status 1
FF00000E B R SSTAT0 SCSI S tatus 0
FF00000F B R DSTAT DMA Status
FF000010 LW R/W DSA Data Structure Address
FF000014 B R CTE ST3 Chip Test 3
FF000015 B R CTE ST2 Chip Test 2
FF000016 B R CTE ST1 Chip Test 1
FF000017 B R/W CTEST0 Chip Test 0
FF000018 B R/W CTEST7 Chip Test 7
FF000019 B R/W CTEST6 Chip Test 6
FF00001A B R/W CTES T5 Chip Test 5
FF00001B B R/W CTES T4 Chip Test 4
FF00001C LW R/W T E MP Temporary Stack
FF000020 B R/W LCRC Longitudinal Parity
FF000021 B R/W CTEST8 Chip Test 8
FF000022 B R/W ISTAT Interrupt Status
FF000023 B R/W DFIFO DMA FIFO
FF000024 B R/W DCMD DMA Command
FF000025 (B) R/W DBC (lsb) DMA Byte Counter (least signif i cant byte)
FF000026 W R/W DBC DMA Byte Counter
FF000028 LW R/W DNAD DMA Next Address for Data
FF00002C LW R/W DSP DMA SCRIPTS Pointer
FF000030 LW R/W DSPS DMA SCRIPTS Pointer Save
FF000034 LW R/W SCRATCH General Purpose Scratch Pad
FF000038 B R/W DCNTL DMA Control
FF000039 B R/W DWT DMA Watchdog Ti mer
FF00003A B R/W DIEN DMA Int errupt Enable
FF00003B B R/W DMODE DMA Mode
FF00003C LW R/W A DDE R Sum Output of Internal Adder
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 32
7.6.5 SCSI Electrical Interface
The output drivers for the SCSI interf ace fully conform to the electrical requirements of SCSI-1 and
SCSI-2.
The drivers are isolated from the power supply. This ensures that, when powered down, the
BVME4000/6000 does not affect the active SCSI bus.
The SCSI bus requires termination at both ends of the bus. It is important that terminators are f itted at,
and only at, both ends of the bus. The BVME4000/6000 uses active, cur rent-mode terminators that
provide high performance termination that allows the BVME4000/6000 to achieve 10Mb/s transfer
rates when connected to a SCSI-2 bus.
The BVME4000/6000 terminators are active when LK13 is omitted. When LK13 is fitted, then the
BVME4000/6000 terminators are completely disabled and provide no load to the SCSI bus.
The BVME4000/6000 drives TERMPWR and uses T ERMPWR for its onboard ter m inators. T hus even
when unpowered the BVME4000/6000 will provide correct termination, if enabled (LK13 omitted).
Connection to SCSI bus is achieved via two alternative connections:
1. J1 provides a direct connection to a 50-way standard IDC ribbon. The layout of this connector
is intended for direct connection to SCSI peripherals built into a module with the
BVME4000/6000.
2. P2 carries all the SCSI signals (including T ERMPWR). T his allows a transition module to be
connected behind the backplane to provide connection to SCSI peripherals outside the
BVME4000/6000 enclosure.
Refer to section "6 Connector Pinouts (on page 19)" for details of SCSI connector pinouts.
Copyright 1993,1995,1998,2001 BVM Ltd.
33 BVME4000/6000
7.7 Ethernet Controller
7.7.1 Overview
The Ethernet Interface is built around the Intel 82596CA LANC. This provides a 32-bit DMA driven
interface to both Ethernet (via the AUI interface) and Cheapernet (via a front panel BNC). The 32- bit,
DMA driven interface allows direct acc ess to the entire m emory map of the BVME4000/6000 allowing
full packet management by the 82596CA. Each 32-bit transfer requires 320nS max (including
arbitration) to execute the cycle. A transfer will occur no more frequently than every 4µS (4 bytes at
1Mbyte per second). Thus worst case bus bandwidth requirement is 8% at 25MHz bus clock.
7.7.2 Programming
The CPU and the 82596CA do not communicate directly (by registers). Instead, they comm unic ate via
a shared memory model. That is, the CPU sets up command blocks in memory and activates the
82596CA's Channel Attention. The 82596CA then examines the command block and executes the
commands. When it has finished it generates an interrupt to the CPU.
The 82596CA is hardware configured for Big Endian operation. This has fairly subtle effects on
parameter ordering in mem ory command blocks; in partic ular, m os t address pointers have their words
swapped. For full programming details, refer to the 82596CA documentation detailed in the "A.3
82596CA (on page 60)" section of this manual.
Although the CPU and the 82596CA do not generally communicate directly, there is a 'virtual' register
that the CPU can access to assert Channel Attention and to write to an 82596CA internal register
(PORT).
Refer to "Appendix B CPU Cache Coherency and Bus Snooping (on page 62)" for details on Cache
Coherency Implications (snooping) while the 82596CA is a bus master.
Refer to "7.8 Interrupt Controller (on page 35)" for details of Interrupt generation by the 82596CA.
7.7.3 PORT Access
Accesses to the PORT register cons ist of tw o consecu tive 32-bit writes at location FF100000, with
bits D31..D16 of the command in the least s ignificant word and bits D15..D0 of the command in the
most significant word (i.e. the command is word-swapped). The PORT register is a write only register.
Writing to the 82596CA PORT allows the CPU to do four things:
1. Write an Alternative System Conf iguration Pointer (SCP) address. This needs to be done as
the 82596CA will, by default, access 00FFFFF6 for its initial command block after reset.
2. Perform a dump of the internal state of the 82596CA to a specified address.
3. Execute a software reset.
4. Execute a self-test and write the results to memory at the specified address.
Function D31 D4 D3 D2 D1 D0
Reset 0 0 0 0
Self-Test A31 Self-test Results Area A4 0 0 0 1
SCP A31 Alternative SCP Address A4 0 0 1 0
Dump A31 Dump Area Pointer A4 0 0 1 1
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 34
7.7.4 Channel Attention Access
Reading from location FF100000 causes a pulse on the 82596CA Channel Attention input. This
causes the 82596CA to execute command blocks.
7.7.5 Bus Error Handling
The 82596CA cannot directly handle bus errors. If the 82596CA is the bus master and access es a
location from which a bus error is generated (e.g. accesses non-existent memory) then special
hardware on the BVME4000/6000 handles the error condition.
When a bus err or occurs, the 82596CA is removed from the bus and kept off the bus by asserting
BOFF. ETHERR is generated causing an Ethernet Interrupt and the ETHERR bit to be set in the
Interrupt Local Status Register - ref er to "7.8 Interrupt Controller (on page 35)" for details of interrupt
control and status. The 82596CA is held of f the bus until a reset PORT command is issued to the
82596CA.
7.7.6 SYSBUS Byte Requirements
The SYSBUS byte of the SCP controls various hardware bus operations and must be set up as
follows:
Bit 6 Must be set.
INT Bit 5 Must be clear (active high interrupt).
LOCK Bit 4 LOCKed cycles are supported on the BVME4000/6000. It is recommended
that the LOCK function be enabled (bit is clear).
TRG Bit 3 External Triggering is supported on the BVME4000/6000. It is r ecommended
that external triggering be used (bit is set).
M(1-0) Bit 2,1 Should only be used in Linear Addressing Mode (bit 2 is set, bit 1 is clear).
7.7.7 Electrical Interface
The BVME4000/6000 provides both a full 'Cheapernet' (IEEE802.3 - 10Base2) coaxial interface via the
front panel and an Attachment Unit Interface (AUI) port via P2. This allows a transition module to be
connected behind the backplane to provide connection to Thick Ethernet (IEE802.3 - 10Base5) or
other Ethernet standards (e.g. Twisted Pair IEE802.3 - 10BaseT) outside the BVME4000/6000
enclosure.
Selection between the on board Cheapernet interface or the P2 AUI connection is m ade by three links
- refer to "5.2.7 LK7,8,9 Ethernet AUI/Cheapernet Select (on page 15)" for details of the link settings.
An optional 10BaseT (twisted pair) module is available which replaces the Cheapernet connection.
The AUI port is not available when this module is fitted.
Copyright 1993,1995,1998,2001 BVM Ltd.
35 BVME4000/6000
7.8 Interrupt Controller
7.8.1 Overview
The Interrupt Controller is responsible for two independent functions:
Processor Interrupter - T akes interrupts fr om all sourc es (including VMEbus IRQ's , IP IRQ's,
Timers, etc.) and generates an interrupt to the CPU.
VMEbus Interrupter - Generates Interrupts on the VMEbus.
7.8.2 Processor Interrupter
Interrupt Source Level Type
ABORT Switch 7 Auto-vectored
8570 Timers 6 Auto-vectored
68230 Timer 5 Vectored
Memory Module 4 Auto-vectored
85230 DUART 3 Vectored
53C710 SCSI 3 Auto-vectored
68230 Parallel 2 Vectored
82596CA ENET 2 Auto-vectored
Location Monitor 1 Auto-vectored
IP A Int 0
IP A Int 1
IP B Int 0
IP B Int 1
IP Daughter Board
Interrupts, up to 12
sources
VMEbus IRQ 7 7
VMEbus IRQ 6 6
VMEbus IRQ 5 5
VMEbus IRQ 4 4
VMEbus IRQ 3 3
VMEbus IRQ 2 2
VMEbus IRQ 1 1
VMEbus ACFAIL 7 Auto-vectored
Program
Program Vectored - Level Programmable on IP Daughter Board.
Vectored - Level Programmable in IP Interface see "7.9.6 IP Controller Registers (on page 42)".
Vectored - Individually maskable see "7.8.4.1 VMEIRQ Enable Register (on page 36)".
Where multiple sources are generating interrupts on the same level, the acknowledge cycle is
prioritised as follows:
Highest Priority: Auto-vectored
Local vectored
VMEbus Interrupt
Lowest Priority: IP
The IP Interrupts are highly programm able. They are program med in the IP Inter face - refer to "7.9 IP
Controller (on page 39)" for details. The IP interface is responsible for prioritising any pending IP
interrupts. The Interrupt Controller combines the current state of IP inter rupts with all other sources to
generate an Interrupt code to the CPU. During acknowledge cycles, the Interrupt Controller prioritis es
between sources of active interrupts and generates the appropriate acknowledge signal. If it
acknowledges the IP interrupt, then the IP Interface prioritises between any active IP interrupts.
When a VMEbus Interrupt is acknowledged, the BVME4000/6000 becomes a VMEbus master and
initiates an Interrupt Acknowledge cycle over VMEbus. The BVME4000/6000 expects the VMEbus
interrupter to return a vector which is then used by the processor vectoring mechanism . If no VMEbus
interrupter responds within the VMEbus time-out period, then a 'spurious interrupt' vector is generated.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 36
7.8.3 VMEbus interrupter
The BVME4000/6000 can generate interrupts on the VMEbus. This function is c ompletely independent
of the processor Interrupter function. When acknowledged by the VMEbus interrupt handler, the
BVME4000/6000 returns a programmable 8- bit vector. The interr upter is implem ented as Release On
AcKnowledge (ROAK). Thus the interrupt is cleared by the interrupt acknowledge cycle.
The BVME4000/6000 may generate an interrupt on any of the seven VMEbus IRQ levels. However, it
can only generate on a single level at any one time. The level on which an interrupt is gener ated is
programmable - refer to "7.8.4.2 VMEIRQ Vector Register (below)" for details.
The interrupt is asserted by the processor writing to the VMEIRQ Vector Register - refer to "7.8.4.3
VMEIRQ Level Register (on page 37)" for details. The value written to the VMEIRQ Vector Regist er is
then used as the value returned in the subsequent acknowledge cycle.
7.8.4 Interrupt Controller Registers
The Interrupt Controller contains six byte wide registers in four I/O loc ations. The first three locations
are WRITE ONLY - DO NOT READ FROM THEM, the last location is READ ONLY.
Address Register D7 D6 D5 D4 D3 D2 D1 D0
FF200003 VMEIRQ Enable
FF200007 VMEIRQ Vector
VMEIRQ Level
FF20000B LOCIRQ Enable
ETHIRQ Enable
FF20000F Local IRQ Status
VIEN7 VIEN6 VIEN5 VIEN4 VIEN3 VIEN2 VIEN1 ACFEN
VEC7 VEC6 VEC5 VEC4 VEC3 VEC2 VEC1 0
Rsrvd Rsrvd Rsrvd Rsrvd VLVL2 VLVL1 VLVL0 1
Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd LOCEN 0
Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd ETHEN 1
Rsrvd Rsrvd Rsrvd Rsrvd ABORT ACFAIL ETHERR ETHIRQ
7.8.4.1 VMEIRQ Enable Register
Bit 7-1: VIEN(7-1): VMEbus Interrupt Enable.
When SET thes e bits enable the corresponding inter rupts from VMEbus. For exam ple setting
bits 7 and 3 enable VMEbus IRQ's 7 and 3 to generate interrupts to the processor.
After RESET these bits are CLEAR (i.e. all VMEbus interrupts disabled).
Bit 0: ACFEN: ACFAIL Interrupt Enable.
When SET this bit enables interrupts from the VMEbus ACFAIL signal - r efer to "7.8.4.6 Local
IRQ Status Register (on page 38)" for details on ACFAIL interrupt operation.
After RESET this bit is CLEAR (i.e. ACFAIL interrupts disabled).
7.8.4.2 VMEIRQ Vector Register
Bit 7-1: VEC(7-1): Interrupt Vector.
Writing to this register s ets bits 7 to 1 of the Interrupt ID vector that will be returned to the
VMEbus Interrupt Handler, bit 0 is always set to ZERO. The act of writing to this register also
causes the VMEbus interrupt line, selected by the LVL(2-0) bits in the VMEIRQ Level
Register, to become active.
Bit 0: Select Bit.
This bit is used to select between the VMEIRQ Level Register and the VMEIRQ Vector
Register. This bit must be written as a ZERO to select the VMEIRQ Vector Register.
Copyright 1993,1995,1998,2001 BVM Ltd.
37 BVME4000/6000
7.8.4.3 VMEIRQ Level Register
Bit 7-4: Reserved.
For future compatibility these must be always written as zero.
Bit 3-1: VLVL(2-0): VMEbus Interrupter Level.
These bits select on which VMEbus Inter rupt level the board will act as an interrupter. The
binary code written selects the corresponding interrupt level (i.e. 101 selects level 5). W hen
set to 000 no interrupt can be generated on VMEbus.
After RESET these bits are CLEAR (i.e. VMEbus interrupt generation disabled).
Bit 0: Select Bit.
This bit is used to select between the VMEIRQ Level Register and the VMEIRQ Vector
Register. This bit must be written as ONE to select the VMEIRQ Level Register.
7.8.4.4 LOCIRQ Enable Register
Bit 7-2: Reserved.
For future compatibility these must be always written as zero.
Bit 1: LOCEN: Location Monitor Interrupt Enable.
When SET this bit enables interrupts from the VMEbus Location Monitor - refer to "7.10
VMEbus Slave Access Controller (on page 45)" for details of VMEbus Slave Operation.
After RESET this bit is CLEAR (i.e. location monitor interrupts disabled).
This bit is used to clear the Location Monitor Interrupt during interrupt service routines. T he
interrupt is cleared by disabling (CLEARing) and re-enabling (SET ting) the Location Monitor
Interrupt.
Bit 0: Select Bit.
This bit is used to select between the LOCIRQ Enable Register and the ETHIRQ Enable
Register. This bit must be written as ZERO to select the LOCIRQ Enable Register.
7.8.4.5 ETHIRQ Enable Register
Bit 7-2: Reserved.
For future compatibility these must be always written as zero.
Bit 1: ETHEN: Ethernet Interrupt Enable.
When SET this bit enables interrupts from the 85296 Ethernet Controller - refer to "7.7
Ethernet Controller (on page 33)" for details of Ethernet Controller Operation.
After RESET this bit is CLEAR (i.e. 82596CA interrupts disabled).
This bit is used to clear the 82596CA Interr upt during interrupt service routines. The interrupt
is cleared by disabling (CLEARing) and re-enabling (SETting) the Ethernet Interrupt.
Bit 0: Select Bit.
This bit is used to select between the LOCIRQ Enable Register and the ETHIRQ Enable
Register. This bit must be written as a ONE to select the ETHIRQ Enable Register.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 38
7.8.4.6 Local IRQ Status Register
Bit 7-4: Reserved.
These bits are unused. When read, their state is undefined.
Bit 3: ABORT: Abort Switch Interrupt.
This bit indicates the status of the ABORT switch. If this bit is SET the ABORT switch is
pressed. This will also generate an Auto-vector level 7 interrupt, so this bit can be used to
determine that the ABORT switch was the source of an Auto-vector level 7 interrupt.
Bit 2: ACFAIL: VMEbus ACFAIL Interrupt.
This bit indicates the status of the VMEbus ACFAIL signal. If this bit is SET the ACFAIL s ignal
is active. This will also generate an Auto-vector level 7 interrupt, s o this bit can be used to
determine that the ACFAIL signal was the source of an Auto-vector level 7 interrupt.
Bit 1: ETHERR: Ethernet ERROR Interrupt.
This bit indicates that a 82596CA Ethernet Controller BUS ERROR has occurred - refer to
"7.7.5 Bus Error Handling (on page 34)" for more details.
Bit 0: ETHIRQ: Ethernet Interrupt Level.
This bit indicates the status of the 82596CA Ethernet Controller interrupt signal. If this bit is
SET the 82596CA's interrupt signal is ac tive. Note: This does not indicate the s tatus of the
internal interrupt signal controlled by ETHEN, but indicates the status of the 82596CA's
interrupt signal directly. The 82596CA will pulse its interrupt line inactive whenever a 'new'
interrupt condition becomes true within the device. T hus to distinguish between an Ethernet
Error interrupt and a normal Ether net interrupt, the ETHERR bit should be interrogated; not
the ETHIRQ bit.
Copyright 1993,1995,1998,2001 BVM Ltd.
39 BVME4000/6000
7.9 IP Controller
7.9.1 Overview
The IP interface supports two onboard IP sites (I P A & IP B) as well as up to a further 4 IP s ites via an
expansion interface on a separate daughter board (IP's C to F).
Double width (D32) pairs of IP's are supported. Support for D16 and D32 Memory IP's is included.
High speed operation is supported:
8 MHz: This is the standard clock speed that all IP's support.
32 MHz: This higher speed operation is def ined in the IP Specification. Many modern
IP designs offer this higher speed operation.
SYNC: In this m ode, the IP runs synchronously with the main CPU clock speed. This
can achieve much higher performance on compatible IP's as clock
synchronisation is not necessary.
7.9.2 IP Expansion Interface
The IP expansion interface allows for a low cost IP carrier daughter board to be added - refer to
"Appendix D IP Expansion Interface Pinout (on page 67)" for details. The BVME4000/6000 c ontains all
the state machine and multiplexing logic thus minim ising daughter board circuitry requirements. The
interface allows up to four additional IP sites on a daughter board at all speed selections. F or exam ple
the EXP100 Expansion Board can be used - refer to the EXP100 documentation detailed in the to
"A.16 EXP100 Quad IP Expansion User's Manual (on page 61)" section of this manual.
7.9.3 IP Interrupts
Each IP can generate interrupts on two separate IRQ lines, INT0 and INT1. The IP Interfac e contains
registers for setting, in s oftware, the level on which each IRQ source will generate interrupts. IRQ's
from the on board IP's (i.e. first two) are supported in the IP interface. The daughter board is
responsible for prioritising any pending interrupts fr om IP's on the daughter board. The IP interface
combines the current state of the daughter board with that of onboard IP's to generate an interrupt
code to the Interrupt Controller - refer to "7.8 Interrupt Controller (on page 35)" for details.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 40
7.9.4 Memory Space Address Map
The Address Map logic decodes two 128Mbyte regions for memory space accesses, generating
/IPMEMCS when the processor accesses either of the IP Memory regions. The IP mem ory is dual
mapped in two regions to provide for acc esses using different c aching modes. Refer to "Appendix B
CPU Cache Coherency and Bus Snooping (on page 62)" for mor e details. This region is then fur ther
decoded in the IP Interface.
Each IP can be accessed in two ways:
1. As a single, 16-bit wide device through an 8Mbyte window.
2. As a double-size, 32-bit wide device through a 16Mbyte window. In this mode, a pair of IP
sites are used to take the double-size IP.
Thus A26 to A0 are used by the IP's or IP Interface for memory space decoding as shown below.
Address Range A[26:23] Size IP Selected IP A[22-A1]
E0000000 - E07FFFFF
F0000000 - F07FFFFF
E0800000 - E0FFFFFF
F0800000 - F0FFFFFF
E1000000 - E17FFFFF
F1000000 - F17FFFFF
E1800000 - E1FFFFFF
F1800000 - F1FFFFFF
E2000000 - E27FFFFF
F2000000 - F27FFFFF
E2800000 - E2FFFFFF
F2800000 - F2FFFFFF
E3000000 - E3FFFFFF
F3000000 - F3FFFFFF
E4000000 - E4FFFFFF
F4000000 - F4FFFFFF
E5000000 - E5FFFFFF
F5000000 - F5FFFFFF
E6000000 - E6FFFFFF
F6000000 - F6FFFFFF
E7000000 - E7FFFFFF
F7000000 - F7FFFFFF
0000 8Mb (D16) IP A A22 - A1
0001 8Mb (D16) IP B A22 - A1
0010 8Mb (D16) IP C A22 - A1
0011 8Mb (D16) IP D A22 - A1
0100 8Mb (D16) IP E A22 - A1
0101 8Mb (D16) IP F A22 - A1
0110 16Mb (D16) Reserved don't care
100x 16Mb (D32) IP A/B A23 - A2
101x 16Mb (D32) IP C/D A23 - A2
110x 16Mb (D32) IP E/F A23 - A2
111x 16Mb (D32) Reserved don't care
Copyright 1993,1995,1998,2001 BVM Ltd.
41 BVME4000/6000
7.9.5 I/O & ID Space Address Map
The address map logic decodes a 1Mbyte space of the I/O region to IP I/O. This space is shared
amongst the 8 IP's.
Each IP has an I/O space consisting of 128 bytes m apped as 64 words. Als o eac h IP has 128 bytes of
ID space, this again is word mapped.
In addition each pair of IP's can be combined to give 32-bit wide accesses, as for memory accesses.
Address Range A[11:7] Size IP Selected IP A[6-1]
FF800000 - FF80007F 0000 0 128 byte (D16) IP A I/O A6 - A1
FF800080 - FF8000FF 0000 1 128 byte (D16) IP A ID A6 - A1
FF800100 - FF80017F 0001 0 128 byte (D16) IP B I/O A6 - A1
FF800180 - FF8001FF 0001 1 128 byte (D16) IP B ID A6 - A1
FF800200 - FF80027F 0010 0 128 byte (D16) IP C I/O A6 - A1
FF800280 - FF8002FF 0010 1 128 byte (D16) IP C ID A6 - A1
FF800300 - FF80037F 0011 0 128 byte (D16) IP D I/O A6 - A1
FF800380 - FF8003FF 0011 1 128 byte (D16) IP D ID A6 - A1
FF800400 - FF80047F 0100 0 128 byte (D16) IP E I/O A6 - A1
FF800480 - FF8004FF 0100 1 128 byte (D16) IP E ID A6 - A1
FF800500 - FF80057F 0101 0 128 byte (D16) IP F I/O A6 - A1
FF800580 - FF8005FF 0101 1 128 byte (D16) IP F ID A6 - A1
FF800600 - FF8007FF 011X X 512 byte (D16) Reserved don't care
FF800800 - FF8008FF 1000 X 256 byte (D32) IP A/B I/O A7 - A2
FF800900 - FF8009FF 1001 X 256 byte (D32) IP C/D I/O A7 - A2
FF800A00 - FF800AFF 1010 X 256 byte (D32) IP E/F I/O A7 - A2
FF800B00 - FF800BFF 1011 X 256 byte (D32) Reserved don't care
FF800C00 - FF800FFF 11XX X 1024 byte Reserved don't care
FF801000 - FF8FFFFF XXXX X 1Mbyte minus 4Kbyte Reserved *
* NOTE: The address space FF801000 - FF8FFFFF is a wrap-around region of the FF800000 -
FF800FFF address space.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 42
7.9.6 IP Controller Registers
The IP Interface contains six byte wide registers. All registers are write only.
Address Register D7 D6 D5 D4 D3 D2 D1 D0
FF300003 IRQ Level A0
FF300083 IRQ Level A1
FF300103 IRQ Level B0
FF300183 IRQ Level B1
FF300203 Clock Speed Select
FF300283 SYNC Clock Select
7.9.6.1 IRQ Level A0 Register
Bit 7-3: Reserved.
For future compatibility these must be always written as zero.
Bit 2-0: A0L(2-0): IP A IntReq 0 Level.
These bits select on which Interrupt level the IP IntReq will act as an interrupter . The binary
code written selects the corresponding inter rupt level (e.g. 101 selects level 5). W hen set to
000 no interrupt can be generated.
Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd A0L2 A0L1 A0L0
Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd A1L2 A1L1 A1L0
Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd B0L2 B0L1 B0L0
Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd B1L2 B1L1 B1L0
RsrvdRsrvdRsrvdRsrvdRsrvdCLKXCLKBCLKA
Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd SYNCX SYNCB SYNCA
After RESET these bits are CLEAR (i.e. interrupt generation disabled).
7.9.6.2 IRQ Level A1 Register
Bit 7-3: Reserved.
For future compatibility these must be always written as zero.
Bit 2-0: A1L(2-0): IP A IntReq 1 Level.
These bits select on which Interrupt level the IP IntReq will act as an interrupter . The binary
code written selects the corresponding inter rupt level (e.g. 100 selects level 4). W hen set to
000 no interrupt can be generated.
After RESET these bits are CLEAR (i.e. Interrupt generation disabled).
7.9.6.3 IRQ Level B0 Register
Bit 7-3: Reserved.
For future compatibility these must be always written as zero.
Bit 2-0: B0L(2-0): IP B IntReq 0 Level.
These bits select on which Interrupt level the IP IntReq will act as an interrupter . The binary
code written selects the corresponding inter rupt level (e.g. 011 selects level 3). W hen set to
000 no interrupt can be generated.
After RESET these bits are CLEAR (i.e. Interrupt generation disabled).
Copyright 1993,1995,1998,2001 BVM Ltd.
43 BVME4000/6000
7.9.6.4 IRQ Level B1 Register
Bit 7-3: Reserved.
For future compatibility these must be always written as zero.
Bit 2-0: B1L(2-0): IP B IntReq 1 Level.
These bits select on which Interrupt level the IP IntReq will act as an interrupter . The binary
code written selects the corresponding inter rupt level (e.g. 010 selects level 2). W hen set to
000 no interrupt can be generated.
After RESET these bits are CLEAR (i.e. Interrupt generation disabled).
7.9.6.5 IP Clock Speed Select Register
The IP controller supports four different clock speeds to the IP sites: Two standard
frequencies; 8MHz and 32MHz and two 'Source Synchronous' frequencies that are derived
from the CPU clock. This register selects between the high speed (32MHz or CPU clock
frequency) and low speed (8MHz or CPU clock divided by four). It is set up in conjunction with
the IP Sync Clock Select Register to set the required IP frequency.
Bit 2: CLKX: IP Expansion Interface Clock Select.
When CLEAR the IP expans ion interface is clocked at 8MHz or CPU Clock divided by four
(depending on the setting of SYNCX bit of the IP SYNC Clock Select Regis ter). When SET
the IP expansion interface is clocked at 32MHz or CPU Clock (depending on the s etting of
SYNCX bit of the IP SYNC Clock Select Register).
After RESET this bit is CLEAR (i.e. 8MHz clock selected or CPU Clock divided by four).
Bit 1: CLKB: IP B Clock Select.
When CLEAR IP B is clocked at 8MHz or CPU Clock divided by four (depending on the setting
of SYNCX bit of the IP SYNCB Clock Select Register). W hen SET the IP expans ion interface
is clocked at 32MHz or CPU Clock (depending on the s etting of SYNCB bit of the IP SYNC
Clock Select Register).
After RESET this bit is CLEAR (i.e. 8MHz clock selected or CPU Clock divided by four).
Bit 0: CLKA: IP A Clock Select.
When CLEAR IP A is clocked at 8MHz or CPU Clock divided by four (depending on the setting
of SYNCX bit of the IP SYNCA Clock Select Register). W hen SET the IP expans ion interface
is clocked at 32MHz or CPU Clock (depending on the s etting of SYNCA bit of the IP SYNC
Clock Select Register).
After RESET this bit is CLEAR (i.e. 8MHz clock selected or CPU Clock divided by four).
7.9.6.6 IP SYNC Clock Select Register
The IP controller supports four different clock speeds to the IP sites. Two standard
frequencies: 8MHz and 32MHz and two 'Source Synchronous' frequencies that are derived
from the CPU clock. This r egister selects between the standar d speed (32MHz or 8MHz) and
Source Synchronous speed (CPU clock frequency or CPU clock divided by four). It is s et up in
conjunction with the IP Clock Speed Select Register to set the required IP frequency.
Bit 2: SYNCX: IP Expansion Interface SYNC Clock Select.
When CLEAR the IP expans ion interface is clock ed at 8 or 32MHz (dependent on the CLKX
bit see above). W hen SET the IP expansion inter face is clock ed synchronously with the main
CPU clock at either the CPU clock f requency or CPU clock divided by 4 (again dependent on
the CLKX bit).
After RESET this bit is CLEAR (i.e. 8/32MHz clock selected).
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 44
Bit 1: SYNCB: IP B SYNC Clock Select.
When CLEAR IP B is c locked at 8 or 32MHz (dependent on the CLKB bit see above). W hen
SET the IP expansion interface is clocked synchronously with the main CPU clock at either
the CPU clock frequency or CPU clock divided by 4 (again dependent on the CLKB bit).
After RESET this bit is CLEAR (i.e. 8/32MHz clock selected).
Bit 0: SYNCA: IP A SYNC Clock Select.
When CLEAR IP A is c locked at 8 or 32MHz (dependent on the CLKA bit see above). W hen
SET the IP expansion interface is clocked synchronously with the main CPU clock at either
the CPU clock frequency or CPU clock divided by 4 (again dependent on the CLKA bit).
After RESET this bit is CLEAR (i.e. 8/32MHz clock selected).
Copyright 1993,1995,1998,2001 BVM Ltd.
45 BVME4000/6000
7.10 VMEbus Slave Access Controller
7.10.1 Overview
The BVME4000/6000 allows other VMEbus masters to access som e of its onboard address s pace. It
allows accesses via either A24 or A32 address spaces. The BVME4000/6000 also acts as a location
monitor for A16 accesses.
7.10.2 Standard (A24) & Extended (A32) Accesses
Both the size of the window and the base address of the window (from the VMEbus master's point of
view) are programmable. T he bas e address of the acc ess f rom the onboar d m em ory's point of view is
also programmable.
Thus the BVME4000/6000 can be set-up to 'dual m ap' a programm able amount of mem ory (64Kbyte
to 4Gbyte) onto the VMEbus. The local base address of the memory is programmable (on window size
boundaries). The address that the 'dual mapped' memory appears at on VMEbus is also
independently programmable. So, for example, 512Kbytes of memory module memory located at
00380000 could be accessed by another VMEbus master accessing location 00C00000-00C80000.
The address decoding for A24 and A32 accesses are separate from each other. There are two
decoders, one for A24 and one for A32. T hey both work by comparing the m ost significant byte of the
address with the programmed base address. Thus A24 space is programmable on 64Kbyte (2
24
boundaries, and the A32 space is programmable on 16Mbyte (2
) boundaries.
16
)
The window sizing operates by masking out address bits to the comparator. Thus f or A24 space the
smallest window size (when no bits are masked) is 64Kbyte and for A32 is 16Mbyte. The window sizes
available are powers of two up to the maxim um window size of the address space (A24 = 8Mbytes,
A32 = 512Mbytes).
A restriction on the window base address is that it m ust be on a window size boundary. Thus if the
window size is 128Kbytes, the window base address must be on a 128Kbyte boundary, e.g. 00000000,
00020000, 00040000, 00D00000 etc.
The BVME4000/6000 responds to the following A24 Address Modifiers (AM) codes:
CPU Supervisor Program Access = $3E
Data Access = $3D
CPU User Program Access = $3A
Data Access = $39
The BVME4000/6000 responds to the following A32 Address Modifiers (AM) codes:
CPU Supervisor Program Access = $0E
Data Access = $0D
CPU User Program Access = $0A
Data Access = $09
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 46
7.10.3 Short I/O (A16) Accesses
The BVME4000/6000 will respond to Short I/O (A16) accesses. The size of the window is fixed at
256bytes. The base address is programmable on 256byte boundaries.
Short I/O space accesses act as a location monitor only and do not access physical memory within the
BVME4000/6000. This space is used to allow 'mail box' interrupts to the processor on the
BVME4000/6000. This allows other bus mas ters to use semaphor e control with the BVME4000/6000
without the use of the VMEbus IRQ lines.
The BVME4000/6000 responds to the following A16 Address Modifiers (AM) codes:
CPU Supervisor Data Access = $2D
CPU User Data Access = $29
7.10.4 Controlling The Window Size
The table below shows window sizes for valid combinations of the Mask Register:
Mask Register A24 Address Space Window Size A32 Address Space Window Size
00 64Kb 16Mb
01 128kb 32Mb
03 256kb 64Mb
07 512Kb 128Mb
0F 1024Kb 256Mb
1F 2048Kb 512Mb
3F 4096Kb 1024Mb
7F 8192Kb 2048Mb
FF 16384Kb 4096Mb
7.10.5 Local Address Generation
The two Local Base Address registers (A32LBA and A24LBA) contain the base address of the 'dual
mapped' memory window.
For A32 accesses, the unmasked (see A32MSK register description) A32 Local Base Address
(A32LBA) Register bits are used as the most significant address lines during the VMEbus slave
access to the onboard memory. All other local address lines are driven from the VMEbus Address bus.
For A24 accesses, The mos t significant eight local address lines are dr iven by the A32LBA register.
The unmask ed (see A24MSK register description) A24 Local Base Address (A24LBA) Register bits
are used as the next most s ignificant address lines during the VMEbus slave access to the onboard
memory. All other local address lines are driven from the VMEbus Address bus.
Thus for standard (A24) VMEbus accesses bot h the A32LBA and the A24LBA registers need to
be set up.
Copyright 1993,1995,1998,2001 BVM Ltd.
47 BVME4000/6000
7.10.6 Address Control Registers
Slave accesses are controlled by eight byte wide registers. All registers are write only.
Address Register D7 D6 D5 D4 D3 D2 D1 D0
FF400003 A32VBA A31cmp A30cmp A29cmp A28cmp A27cmp A26cmp A25cmp A24cmp
FF410003 A32MSK A31msk A30msk A29msk A28msk A27msk A26msk A25msk A24msk
FF420003 A24VBA A23cmp A22cmp A21cmp A20cmp A19cmp A18cmp A17cmp A16cmp
FF430003 A24MSK A23msk A22msk A21msk A20msk A19msk A18msk A17msk A16msk
FF440003 A16VBA A15cmp A14cmp A13cmp A12cmp A11cmp A10cmp A9cmp A8cmp
FF450003 A32LBA A31ladd A30ladd A29ladd A28ladd A27ladd A26ladd A25ladd A24ladd
FF460003 A24LBA A23ladd A22ladd A21ladd A20ladd A19ladd A18ladd A17ladd A16ladd
FF470003 ADDRCTL VMELO Rsrvd SCVME SCETH A32EN A24EN A16EN RAMLO
7.10.6.1 A32VBA - A32 VMEbus Base Address Register
This register contains an 8-bit value, against which extended (A32) VMEbus access es are m atched in
order to determine slave access. If VMEbus A[31..24] matches, then an access to the onboard
memory is performed.
7.10.6.2 A32MSK - A32 VMEbus Address Mask Register
This contains an 8-bit mask that is applied, on a bit by bit basis, to the VMEbus slave address
decoding for A32 (extended) accesses from another VMEbus master. If a bit is set (a 1) then the
corresponding address line is ignored. Thus the contents of this register control the s ize of the window
decoded by the BVME4000/6000 - refer to "7.10.4 Controlling The W indow Size (on page 46)" for
more details.
7.10.6.3 A24VBA - A24 VMEbus Base Address Register
This contains an 8-bit value, against which st andard (A24) VMEbus acc esses ar e matc hed in order to
determine slave access. If VMEbus A[23..16] matches, then an access to the onboard memory is
performed.
7.10.6.4 A24MSK - A24 VMEbus Address Mask Register
This contains an 8-bit mask that is applied, on a bit by bit basis, to the VMEbus slave address
decoding for A24 (standard) accesses from another VMEbus master. If a bit is set (a 1) then the
corresponding address line is ignored. Thus the contents of this register control the s ize of the window
decoded by the BVME4000/6000 - refer to "7.10.4 Controlling The W indow Size (on page 46)" for
more details.
7.10.6.5 A16VBA - A16 VMEbus Base Address Register
This contains an 8-bit value, against which A16 VMEbus accesses are m atched in order to determ ine
slave access. If VMEbus A[15..8] matches, then a Short I/O access is performed.
7.10.6.6 A32LBA - A32 Local Base Address Register
This contains an 8-bit value that is us ed to drive the onboard most significant address lines during an
access by another VMEbus master. In other words it contains the most significant part of the local
memory base address of the 'dual mapped' window - refer to "7.10.5 Local Addr ess Generation (on
page 46)" for more details.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 48
7.10.6.7 A24LBA - A24 Local Base Address Register
This contains an 8-bit value that is used to drive the onboard next most significant address lines during
an access by another VMEbus master. In other words it contains the next m ost significant part of the
local memory base address of the 'dual mapped' window - refer to "7.10.5 Local Addr ess Generation
(on page 46)" for more details.
7.10.6.8 ADDRCTL - Address Control Register
This contains some miscellaneous control bits, After RESET all bits are CLEAR.
Bit 7: VMELO: Map VMEbus Low.
When CLEAR accesses to the bottom 256Mbytes of the address map are c onfined to local
memory only; accesses to non existent m emory return a bus error. W hen SET accesses to
the bottom 256Mbytes of the address map will be to local memory (or memory module if fitted)
OR to VMEbus A32:D32 address space if there is no local memory at that address.
Bit 6: Reserved.
For future compatibility this must be always written as zero.
Bit 5: SCVME: VMEbus Snoop Control.
This bit enables snooping for VMEbus Slave Acces ses. When SET VMEbus slave accesses
are snooped by the CPU, so that the CPU will sink and source dirty data - refer to "Appendix B
CPU Cache Coherency and Bus Snooping (on page 62)" for a dis cussion on snooping and
cache coherency.
Bit 4: SCETH: Ethernet Snoop Control.
This bit enables snooping for Ethernet Controller Master Accesses. When SET Ethernet
Controller master acc esses are snooped by the CPU, so that the CPU will sink and source
dirty data - refer to "Appendix B CPU Cache Coherency and Bus Snooping (on page 62)" for a
discussion on snooping and cache coherency.
Bit 3: A32EN: VMEbus A32 Slave Access Enable.
When SET VMEbus A32 slave acces s es ar e enabled as spec if ied by the A32VBA, A32MSK &
A32LBA registers. When CLEAR VMEbus A32 slave accesses are disabled.
Bit 2: A24EN: VMEbus A24 Slave Access Enable.
When SET VMEbus A24 slave access es are enabled as specified by the A24VBA, A24MSK,
A24LBA & A32LBA registers. When CLEAR VMEbus A24 slave accesses are disabled.
Bit 1: A16EN: VMEbus A16 Slave Access Enable.
When SET VMEbus A16 slave accesses are enabled as specified by the A16LBA regis ter.
When CLEAR VMEbus A16 slave accesses are disabled.
Bit 0: RAMLO: Map RAM Low.
When SET the SRAM (located at E9000000 and F9000000) is also mapped at 00000000.
This is mainly intended to provide a common address map for systems with no memory
module fitted.
Copyright 1993,1995,1998,2001 BVM Ltd.
49 BVME4000/6000
7.11 Configuration Switch
This is a bank of four switches that are available through the front panel. The switches have no
dedicated hardware function. They are provided to allow configuration selection within software
applications. The state of each switch can be read in the Configuration Switch Register.
7.11.1 Configuration Switch Layout
Cheapernet
ON
1 2 3 4
1 2 3 4
Figure 27 Configuration Switch Layout
7.11.2 Configuration Switch Register
Address Register D7 D6 D5 D4 D3 D2 D1 D0
FF500003 CONFSW Rsrvd Rsrvd Rsrvd Rsrvd SW1 SW2 SW3 SW4
Bit 7-4: Reserved.
These bits are unused. When read, their state is undefined.
Bit 3-0: SW1, SW2, SW3, SW4.
Reflects the state of each numbered switch. When the switch is ON (lower position) the
associated bit is read as ZERO. When switch is OFF (upper position) the associated bit is
read as ONE.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 50
7.12 Real Time Clock/Timers
7.12.1 Overview
The Real Time Clock and Timer f ac ilities on the BVME4000/6000 ar e provided by the DP8570A Timer
Clock Peripheral, which provides two 16-bit tim er/counters , calendar/cloc k, a f lexible interrupt s chem e
and 44 bytes of non-volatile RAM.
Two independent, multi-mode, 16 bit tim ers are provided. Thes e timers oper ate in four m odes. Each
has its own prescaler and can select any of 8 possible c lock sourc es. T hus, by program m ing the input
clocks and the timer counter values a very wide range of time duration's can be achieved. The range
is from 200nS (8MHz external clock) to 65,535 seconds (18hrs., 12min.).
A very flexible and powerful on-chip interrupt structure is provided. Three basic types of interrupts are
available: Periodic (from 1mS to 1 m inute), Alarm /Com par e (fr om the RT C) and T imer . Interrupt m as k
and status registers enable the masking and easy determination of each interrupt.
For full programm ing details, refer to the DP8570A docum entation detailed in the "A.5 DP8570A (on
page 60)" section of this manual.
7.12.2 Hardware Specific Considerations
INTR pin Configuration
The INTR pin is fed to the Interrupt Controller - refer to "7.8 Interrupt Controller (on page 35)"
for more details. It m ust be programm ed as an active low, push-pull output. This is set up in
the OUTPUT MODE REGISTER by programming bit 2 (INTR Active Hi/Low) CLEAR and bit 3
(INTR Push-pull/Open Drain) SET.
T1 pin Configuration
The T1 pin (tim er 1 output) is f ed to the T IN pin of the PI/T (MC68230) - ref er to "7.13 Parallel
Port/Timer (on page 52) " for mor e details. It must be programm ed as a push-pull output. The
output may be programmed as active high or low as the application requir es. T his is set up in
the OUTPUT MODE REGISTER by programming bit 1 (T1 Push-pull/Open Drain) SET.
MFO pin Configuration
The MFO pin is not currently connected on the BVME4000/6000.
RTC Crystal Oscillator Frequency
The BVME4000/6000 uses a 32.768 kHz crystal. This pr ovides lowest power dissipation. The
DP8570A needs to be programmed with the oscillator f requency used. This is set up in the
REAL TIME MODE REGISTER by programming bits 7&6 (XT1 and XT0) both CLEAR.
TCK - External Timer Clock Input
TCK is driven from a fixed 8 MHz clock source.
PFAIL - Power Fail Input
This input is driven from the MAX791 power fail signal.
G0 & G1 - Timer Gate Inputs
These pins are pulled low on the BVME4000/6000.
Copyright 1993,1995,1998,2001 BVM Ltd.
51 BVME4000/6000
7.12.3 Programming
The register map of the DP8570A is shown below. The register map consists of two 31 byte pages
with a main status register that is common to both pages. A control bit (bit 7) in the Main Status
Register is used to select either page. Page 0 contains all the clock and timer functions, while page 1
has non-volatile RAM.
Page 0 is further sub-divided to provide two blocks of control registers. Again a bit in the Main Status
Register (bit 6) is used to select either register block.
The registers are all byte wide mapped on the least significant byte of long word boundaries.
Address Page Select = 1 Page Select = 0
Register Select = 1 Register Select = 0
FF900003 Main Status Register
FF900007 RAM Real Time Mode Timer 0 Control
FF90000B RAM Output Mode Timer 1 Control
FF90000F RAM Interrupt Control 0 Periodic Flag
FF900013 RAM Interrupt Control 1 Interrupt Routing
FF900017 RAM
FF90001B RAM Seconds Clock Counter
FF90001F RAM Minutes Clock Counter
FF900023 RAM Hours Clock Counter
FF900027 RAM Day of Month Clock Counter
FF90002B RAM Months Clock Counter
FF90002F RAM Years Clock Counter
FF900033 RAM Units Julian Clock Counter
FF900037 RAM 100s Julian Clock Counter
FF90003B RAM Day of Week Clock Counter
FF90003F RAM Timer 0 LSB
FF900043 RAM Timer 0 MSB
FF900047 RAM Timer 1 LSB
FF90004B RAM Timer 1 MSB
FF90004F RAM Seconds Compare RAM
FF900053 RAM Minutes Compare RAM
FF900057 RAM Hours Compare RAM
FF90005B RAM Day of Month Compare RAM
FF90005F RAM Months Compare RAM
FF900063 RAM Day of Week Compare RAM
FF900067 RAM Seconds Time Save RAM
FF90006B RAM Minutes Time Save RAM
FF90006F RAM Hours Time Save RAM
FF900073 RAM Day of Month Time Save RAM
FF900077 RAM Months Time Save RAM
FF90007B RAM RAM
FF90007F RAM RAM/TEST
1
/
Second Counter
100
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 52
7.13 Parallel Port/Timer
7.13.1 Overview
The Parallel Interface/Tim er (PI/T) is based on the MC68230. T his block provides a bi-directional, 8bit, double-buffered, Centronics com patible parallel Interface. This interfac e is electrically buffered to
provide 48mA of drive. Connection can be m ade via the front panel connector JP3 or via a paddle
board connected to the backplane P2.
The PI/T provides internal Board Contr ol Register func tions to control SCC c lock s election, Watchdog
refresh and VMEbus Arbitration Selection.
The PI/T contains an independent, 24-bit timer with a 5-bit presc aler. The timer m ay be clocked from
the PI/T clock pin or from the T1 output pin of the RTC Timer 1 - refer to "7.12 Real Time
Clock/Tim ers (on page 50)" for more details. It can generate periodic interrupts or a s ingle interrupt
after programm ed time period. T he CLK pin is driven from CPUCLK divided by 4, thus with a 25MHz
bus clock, the PI/T CLK is driven at 6.25MHz.
For full programming details, ref er to the MC68230 documentation detailed in the "A.7 MC68230 (on
page 60)" section of this manual.
7.13.2 Port A Usage
The MC68230 port A is available for use as an 8-bit parallel I/O port. It is buffered using a bidirectional transceiver to give 48mA of dr ive. The direction control of the transceiver is via port C refer to "7.13.4 Port C Usage (on page 54)" for more details. Any of the port A sub-m odes may be
used. However, because the port is connected to an 8-bit wide transceiver, ALL the bits must be
programmed to be in the same direction; all inputs or all outputs. The direction programmed must
match that of the transceiver set up via port C.
7.13.3 Port B Usage
The MC68230 port B is dedicated as an internal Board Control Register. This port needs to be
configured for simple pin I/O. Theref ore the MC68230 m ust be conf igured for Port Mode 0. This is s et
up in the PORT GENERAL CONTROL REGISTER by program ming bits 7 & 6 both CLEAR. Port B
must be configured to Sub Mode 1X. This is set up in the PORT B CONTROL REGISTER by
programming bit 7 SET.
D7 D6 D5 D4 D3 D2 D1 D0
OUT OUT OUT OUT OUT IN/OUT OUT OUT
/RRS /SYSCON RQLVL1 RQLVL0 SCL SDA SCLKA SCLKB
Bit 7: /RRS: Round Robin Select.
This must be programmed as an output pin. This bit controls the VMEbus arbitration
mechanism used by the BVME4000/6000 when enabled as a System Controller. When the bit
is SET straight prioritised (PRI) or single level (SGL) is used. When CLEAR Round Robin
Select (RRS) is used. See Section 3 of the VMEbus Specification for a full description - refer
to "A.8 VMEbus (on page 60)" for details of this documentation.
Bit 6: /SYSCON: System Controller Function Enable.
This must be pr ogramm ed as an output pin. This bit controls whether the BVME4000/6000 is
the VMEbus System Controller unless overridden by the System Controller Link - refer to
"5.2.12 LK22 VMEbus System Controller Enable (on page 17)" for more details. When
programmed as the VMEbus System Controller, the BVME4000/6000 performs as the
VMEbus arbiter, it drives VMEbus SYSCLK and VMEbus BCLR. When the bit is SET the
BVME4000/6000 is NOT the System controller. When CLEAR the BVME4000/6000 is the
VMEbus System Controller.
Copyright 1993,1995,1998,2001 BVM Ltd.
53 BVME4000/6000
Bit 5,4: RQLVL1,RQLVL0: VMEbus Request Level Selec tion.
These must be programm ed as output pins. The BVME4000/6000 can request m astership of
the VMEbus on any of the four VMEbus request levels. These two bits select which level
VMEbus requests are made upon:
RQLVL1 RQLVL0 VMEbus Request Level
0 0 Requests on level 0
0 1 Requests on level 1
1 0 Requests on level 2
1 1 Requests on level 3
Bit 3: SCL: Serial Clock Line.
This must be programmed as an output pin. This bit controls the I
2
C Clock Line, used for
clocking data in and out of the NM24C02 EEPROM. When the bit is SET the clock line is
HIGH, when the bit is CLEAR the clock line is LOW. For f ull program m ing details, refer to the
NM24C02 documentation detailed in the "A.11 NMC24C02 (on page 61)" section of this
manual.
Bit 2: SDA: Serial Data Line.
This is the I
2
C Data Line, used for reading the data to/from the NM24C02 EEPROM. When
the set as an output pin, the data will be OUTPUT to the EEPROM, when s et as an input pin,
the data will be INPUT from the EEPRO M. The bit sets the data to the EEPROM in output
mode, and reflects the data from the EEPROM in input m ode. For full programm ing details,
refer to the NM24C02 documentation detailed in the "A.11 NMC24C02 (on page 61)" section
of this manual.
Bit 1: SCLKA: Serial Communications Controller Clock Select for Channel A.
This must be program med as an output pin. T his bit controls which clock sour ce is applied to
the RTxCA pin of the SCC. Refer to "7.14 Ser ial Communications Controller (on page 56)" for
details of Baud Rate generation for Serial channels. The clock source can be selected
between an onboard crystal and an external clock from the P2 connector.
SCLKA Value Clock Applied to RTxCA
0 Onboard Crystal - 7.3728 MHz
1 SCLKINA signal from P2 (pin 4c)
Bit 0: SCLKB: Serial Communications Controller Clock S elect for Channel B.
This must be program med as an output pin. T his bit controls which clock sour ce is applied to
the RTxCB pin of the SCC. . Refer to "7.14 Ser ial Communications Controller (on page 56)"
for details of Baud Rate generation for Serial channels. The clock source can be selected
between an onboard crystal and an external clock from the P2 connector.
SCLKB Value Clock Applied to RTxCB
0 Onboard Crystal - 7.3728 MHz
1 SCLKINB signal from P2 (pin 8c)
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 54
7.13.4 Port C Usage
The MC68230 port C is nominally an 8 bit general purpose I/O port ( similar to Ports A & B). However
five of the pins carry special functions associated with interrupts and timer operation.
The PORT SERVICE REQUEST REGISTER s hould be set up to us e vec tor ed interr upts on PIRQ and
PIACK. Thus bits 4 & 3 should be set as: Bit 4 SET, Bit 3 SET. T he PORT INTERRUPT VECT OR
REGISTER should be set up with the required Interrupt vector.
The TIMER CONTRO L REGISTER should be s et up to use vectored inter rupts on T OUT and T IACK.
Thus bits 7 & 6 should be set as: Bit 7 SET , Bit 6 CLEAR. Bit 5 should be used as an interr upt enable
bit. The TIMER INTERRUPT VECTOR REGISTER should be set up with the required Interrupt vector.
D7 D6 D5 D4 D3 D2 D1 D0
Special Special Special IN/OUT Special Special OUT OUT
/TIACK /PIACK /PIRQ WDOG TOUT TIN PADIR PAEN
Bit 7: /TIACK: Timer Interrupt Acknowledge.
The Interrupt Controller assumes that the MC68230 Timer Interrupter supports vectored
interrupts. This pin is connected to the Interrupt Controller's TIMIACK line.
Bit 6: /PIACK: Parallel Port Interrupt Acknowledge.
The Interrupt Controller assumes that the MC68230 Parallel Interrupter supports vectored
interrupts. This pin is connected to the Interrupt Controller's PARIACK line.
Bit 5: /PIRQ: Parallel Port Interrupt Request.
This output drives the 68230 Parallel Interrupt input to the Inter rupt Controller - refer to "7.8
Interrupt Controller (on page 35)" for more details.
Bit 4: WDOG: WatchDog Refresh.
This bit drives the input to the watchdog circuit. When this bit is configured as an INPUT , the
watchdog function is disabled. When c onf igured as an O UT PUT, the watchdog is enabled and
this bit must be toggled every second if a Watchdog time out is to be avoided. If the WDOG bit
is not toggled within the time out period (1 second m inimum) then a hardware reset will be
generated.
Bit 3: TOUT: Timer Output.
This output drives the 68230 Timer Interrupt input to the Interrupt Controller - refer "7.8
Interrupt Controller (on page 35)" for more details.
Bit 2: TIN: Timer Input.
This input is driven from the T1 output of the DP8570A - refer to "7.12 Real Time
Clock/Timers (on page 50)" for more details.
Bit 1: PADIR: Port A Direction.
This OUTPUT controls the DIRECTION of the transceiver. When SET the transceiver will
drive OUT from the BVME4000/6000 to the connector. When CLEAR the transceiver will
receive IN from the connector and drive into Port A.
Bit 0: PAEN: Port A Enable.
This OUTPUT controls the ENABLE to the tr ansceiver. When SET the tr ansceiver is disabled
and its outputs are hi-impedance. When CLEAR the transceiver is enabled and will drive in the
direction controlled by its DIRECTION input.
Copyright 1993,1995,1998,2001 BVM Ltd.
55 BVME4000/6000
7.13.5 Handshake Pin Usage
H1: This must be configured as an input. It is connected to /PACKNOW signal via an inverting
buffer.
H2: T his must be configured as an output. It is connected to /PSTROBE signal via an inverting
buffer.
H3: This must be configured as an input. It is connected to PBUSY signal via an inverting buffer.
H4: This signal is currently not connected on the BVME4000/6000.
7.13.6 MC68230 PI/T Registers
The register map of the MC68230 is shown below. The register map consists of a bank of 32 byte
wide registers (of which som e are undefined). The registers are mapped on the least significant byte
of long words.
Address Register Access Affected by
Reset
FFA00003 Port General Control Register R/W Yes No
FFA00007 Port Service Request Register R/W Yes No
FFA0000B Port A Data Direction Register R/W Yes No
FFA0000F Port B Data Direction Register R/W Yes No
FFA00013 Port C Data Direction Register R/W Yes No
FFA00017 Port Interrupt Vector Register R/W Yes No
FFA0001B Port A Control Register R/W Yes No
FFA0001F Port B Control Register R/W Yes No
FFA00023 Port A Data Register R/W No Yes
FFA00027 Port B Data Register R/W No Yes
FFA0002B Port A Alternate Register R No No
FFA0002F Port B Alternate Register R No No
FFA00033 Port C Data Register R/W No No
FFA00037 Port Status Register R/W Yes No
FFA0003B Reserved
FFA0003F Reserved
FFA00043 Timer Control Register R/W Yes No
FFA00047 Timer Interrupt Vector Register R/W Yes No
FFA0004B Reserved
FFA0004F Counter Preload Register High R/W No No
FFA00053 Counter Preload Register Middle R/W No No
FFA00057 Counter Preload Register Low R/W No No
FFA0005B Reserved
FFA0005F Counter Register High R No No
FFA00063 Counter Register Middle R No No
FFA00067 Counter Register Low R No No
FFA0006B Timer Status Register R/W Yes No
FFA0006F Reserved
Affected by
Access
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 56
7.14 Serial Communications Controller
7.14.1 Overview
The Serial Comm unications Controller (SCC) resource is based on the Z85230. This bloc k provides
two independent, full-duplex serial communication channels. Both channels handle asynchronous,
byte synchronous and bit synchronous protocols. Each channel has its own baud rate generator,
clocked from a variety of sources, including a Digital Phase Locked Loop (DPLL).
Each channel can be independently electrically buffered as RS232, RS422 or RS485. Connection can
be made via the front panel connectors JP1 and JP2 or via a paddle board connected via the P2
connector.
For full programm ing details, ref er to the Z85230 docum entation detailed in the "A.6 Z85230 (on page
60)" section of this manual.
7.14.2 Serial Clock Sources
PCLK This is the master Z85230 c lock pin. It is used to synchronise all internal signals. It is available
as a clock source to the baud rate generator. The BVME4000/6000 dr ives this signal with the
processor clock divided by 2. Thus with a 25MHz bus clock, the Z85230 is clocked at
12.5MHz. Because this pin is CPU clock dependent it is recom mended that it is not used f or
baud rate generation.
RTxCA This input pin can be programmed to supply any combination of: the receive clock, the
transmit clock, the baud rate generator and the DPLL. T he BVME4000/6000 drives this signal
from a multiplexer contr olled by the SCLKA bit of the BOARD CONTROL REGISTER. Refer
to "7.13 Parallel Port/Timer (on page 52)" for more details of this register. The clock sourc e
can be selected between an onboard 7.3728MHz crystal and an external clock from P2
Connector.
SCLKA Value Clock Applied to RTxCA
0 Onboard Crystal - 7.3728 MHz
1 SCLKINA signal from P2 (pin 4c)
RTxCB This input pin can be programmed to supply any combination of: the receive clock, the
transmit clock, the baud rate generator and the DPLL. T he BVME4000/6000 drives this signal
from a multiplexer contr olled by the SCLKB bit of the BOARD CONTROL REG ISTER. Refe r
to "7.13 Parallel Port/Timer (on page 52)" for more details of this register. The clock sourc e
can be selected between an onboard 7.3728MHz crystal and an external clock from P2
Connector.
SCLKB Value Clock Applied to RTxCB
0 Onboard Crystal - 7.3728 MHz
1 SCLKINB signal from P2 (pin 8c)
TRxCA This pin is connected to the SCLKOUTA signal on P2 pin 4a. It can be programmed to be
either an input or an output. When programmed as an input, a clock source is received and
can then supply the clock to the receiver and/or the transmitter. When programmed as an
output, it can supply a clock from; the RTxCA pin, the RxDPLL or the baud rate generator.
TRxCB This pin is connected to the SCLKOUTB signal on P2 pin 8a. It can be programmed to be
either an input or an output. When programmed as an input, a clock source is received and
can then supply the clock to the receiver and/or the transmitter. When programmed as an
output, it can supply a clock from; the RTxCB pin, the RxDPLL or the baud rate generator.
Copyright 1993,1995,1998,2001 BVM Ltd.
57 BVME4000/6000
7.14.3 Programming
Each channel has a data register, when it is read, the receiver FIFO is read. W hen it is written, the
transmitter FIFO is written.
Each channel also has a number of W rite Registers and Read Registers that are used to control the
operation of the channel. These are generally accessed as a two step procedure. First the regis ter to
be accessed is written to the Control Register, then the next acc ess to the Control Register ac cesses
the referenced Read or Write Register.
Address Register Access
FFB00003 Control Register - Channel B (JP2)
FFB00007 Data Register - Channel B (JP2)
FFB0000B Control Register - Channel A (JP1)
FFB0000F Data Register - Channel A (JP1)
The BVME4000/6000 supports vectored interr upts fr om the SCC - ref er to "7.8 Interr upt Controller (on
page 35)" for more details.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 58
8. Specifications
8.1 On-Board Functions
BVME4000: MC68040, MC68LC040 or MC68EC040 CPU at 25MHz/33MHz.
BVME6000: MC68060, MC68LC060 or MC68EC060 CPU at 50MHz/66MHz (25MHz/33MHz bus).
Z85230 Dual Serial interface controller, 7.3728MHz or external clock source,
RS232 buffers (RS422 & RS485 options), front panel and P2 connections.
DP8570A Timer Clock Peripheral (calendar-clock, 3 timers, 44 byte NVR).
MC68230 Parallel Interface/Timer, front panel and P2 printer connections.
NCR53C710-1 DMA SCSI Controller, header and P2 connections.
85296CA DMA Ethernet/Cheapernet Controller,
Front panel BNC Cheapernet and P2 AUI connections (RJ45 10BaseT option).
MAX791 Watchdog: refresh period = 1000mS (when enabled).
2 x 32-pin CPU PROM sockets, 16-bit wide, accept 512Kbit to 8Mbit EPROM's, 4Mbit FLASH,
(90ns @ 25MHz bus, 120ns @ 33MHz bus).
512K/2Mbytes CMOS SRAM, 32-bit wide, battery backed (up to 7 days or 2.5 years).
32-bit wide memory module interface with burst-fill up to 2/1/1/1.
2Kbit serial access EEPROM.
LOCAL BUS TIMEOUT period 64 CPU clocks (2.56µS @ 25MHz bus clock).
RED LED indicates VMEbus MASTER access.
GREEN LED indicates processor status.
RESET switch (if enabled).
ABORT switch (level 7 auto-vectored interrupt).
8.2 VMEbus Master
FAIR Bus Requester, request on any of 4 levels.
A32, A24, A16
D32, D16, D08(EO)
RMW
AM6
8.3 VMEbus Slave
A32, A24, A16
D32, D16, D08(EO)
RMW
AM6
LOCATION MONITOR
8.4 VMEbus System Controller Functions
ARBITER: SGL, PRI or RRS, software programmable, FAIR ROR (RWD option).
SYSCLK Driver.
SYSRESET Driver/Monitor power-up and switch.
VMEbus RESET minimum period = 200mS.
BUS TIMEOUT period 128µS.
BUS ERROR monitor.
ACFAIL monitor (level 7 auto-vectored interrupt).
Copyright 1993,1995,1998,2001 BVM Ltd.
59 BVME4000/6000
8.5 VMEbus Interrupts
Interrupter D08(O) ROAK:
I(1-7) single level, software programmable;
Interrupt vector ID, software programmable.
Interrupt handler D08(O): I(1-7) all levels, software maskable.
8.6 IP Functions
Two IP compatible sites:
2 x Single IPs (16-bit) or 1 x Double IP (32-bit);
8MHz, 32MHz or CPU synchronous IP clocks, software selectable;
Software programmable IP interrupts;
Front panel IP I/O connections.
IP expansion connector:
Supports up to four additional IP compatible sites.
8.7 Board Configuration
Configuration Switch: 4-bit, software readable.
LINKS: ABORT/RESET switch enable;
VMEbus RESET IN/OUT enable;
VMEbus SYSTEM CONTROLLER enable;
CPU cache inhibit;
Cheapernet Heartbeat enable;
Cheapernet/Ethernet select;
PROM type;
SCSI Termination select;
SRAM backup source select.
PROGRAM: VMEbus SYSTEM CONTROLLER functions;
VMEbus Master Request Level;
VMEbus SLAVE addressing;
VMEbus interrupt handler levels;
VMEbus interrupt level & vector ID;
Local SRAM & VMEbus mapping;
IP interrupt levels;
IP clock sources;
Serial Port clock sources.
8.8 Operating Environment
Dimensions: 160mm x 233.35mm (6U) single slot.
Power: +5V +0.25V/-0.125V <50mV noise/ripple 2.2A typical;
+12V +0.60V/-0.36V <50mV noise/ripple 150mA maximum;
-12V -0.60V/+0.36V <50mV noise/ripple 0mA;
RESET @ <4.65V, RTC disable @ <4.8V.
Note: power requirements exclude IP, Memory Module & Disc Drive power.
Environmental: 0 to 70 °C, 95%
Refer to "Appendix E Thermal Management (on page 68)" for airflow/heatsink
requirements.
Copyright 1993,1995,1998,2001 BVM Ltd.
humidity non-condensing (extended range to order).
BVME4000/6000 60
Appendix A Data Sheet & Manual References A.1 MC68040/68LC040/68EC040 User's Manual
MOTOROLA MC68040 MC68EC040 MC68LC040 MICROPROCESSORS USER'S MANUAL (1992,
MOTOROLA order number: M68040UM/AD).
MOTOROLA PROGRAMMER'S REFERENCE MANUAL (1991, MOTOROLA order number:
M68000PM/AD).
A.2 MC68060/68LC060/68EC060 User's Manual
MOTOROLA MC68060 MC68LC060 MC68EC060 MICROPROCESSORS USER'S MANUAL (1994,
MOTOROLA order number: M68060UM/AD).
MOTOROLA PROGRAMMER'S REFERENCE MANUAL (1991, MOTOROLA order number:
M68000PM/AD).
A.3 82596CA User's Manual
INTEL 32-Bit Local Area Network (LAN) Compliant User's manual (1992, INTEL order number:
296853-001).
INTEL 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NET WORK COPROCESSOR DAT A
SHEET (July 1992, INTEL order number: 290218-005).
A.4 53C710 Data Manual & Programmers Guide
NCR53C710, 53C710-1 SCSI I/O Processor Data Manual (June 1992, NCR Corporation).
NCR53C710 SCSI I/O Processor Programmers Guide (Sept 1990, NCR Corporation)
A.5 DP8570A Data Sheet
NATIONAL SEMICONDUCTOR DP8570A Timer Counter Peripheral (TCP) Data Sheet (May 1993,
TL/F/8638).
A.6 Z85230 User's Manual
ZILOG SCC User's Manual (Q4/1992).
A.7 MC68230 Data Sheet
MOTOROLA MC68230 PARALLEL INTERFACE/TIMER (PI/T) Data Sheet (Dec 1983).
A.8 VMEbus Specification
THE VMEbus SPECIFICATION (Sept 1987, VITA).
A.9 RS422/485 Interface Module User's Manual
BVM 453-62370/62371 RS422/RS485 INTERFACE MODULE User's Manual (BVM part num ber: 454-
68370).
A.10 AM29F040 Data Book
AMD Flash Memory Products Data Book/Handbook 1996.
Copyright 1993,1995,1998,2001 BVM Ltd.
61 BVME4000/6000
A.11 NMC24C02 Data Sheet
NATIONAL SEMICONDUCTOR NMC24Cxx – Standard 2-W ire Bus Inter face Serial EEPROM Fam ily
(May 1996).
A.12 MEM390 Memory Module User's Manual
MEM390 4/8 Mbyte DRAM MEMORY MODULE User's Manual (BVM part number: 454-68391).
A.13 MEM400 Memory Module User's Manual
MEM400 16Mbytes DRAM 4/8 Mbytes FLASH MEMORY MODULE User's Manual (BVM part number:
454-61400).
A.14 MEM480 Memory Module User's Guide
MEM480 16/32/48Mbytes DRAM MEMORY MODULE User's Guide (BVM part number: 454-61480).
A.15 MEM4SD Memory Module User's Guide
MEM4SD 16 to 512Mbytes SDRAM MEMORY MODULE User's Guide (BVM part number: 454-
61490).
A.16 EXP100 Quad IP Expansion User's Manual
EXP100 Quad IP Expansion User's Manual (BVM part number: 454-44100).
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 62
Appendix B CPU Cache Coherency and Bus Snooping
B.1 BVME4000 (MC68040)
The MC68040 is a third generation 68000 series processor with separate data and instruction c aches
of 4Kbytes each. The cache unit supports full copyback cac hing, in addition to write-through caching
(as available on earlier processors), cache inhibited, and bus-serialised cache modes.
Copyback caching means that when data is written out by the program, it m ay only reach the cache,
and not the main memory. This poses cache coherency problems over those nor m ally associated with
earlier 68000 series processor s (e.g. 68030), as the main memory can contain s tale data, affecting
DMA operations transferring data from dual-ported memory as well as to
Bus serialisation is required as the 68040's internal architecture has a high degree of parallelism.
Reads and writes do not occur in the order in which they are defined by the programmer. Normally this
causes no problem as the 68040 will detect any clashes and synchronise them, but if access es are
being made to I/O areas for example, the ordering of reads and writes are very important. Bus
serialised regions cause correct ordering of the reads and writes.
It follows on from the above that it is im portant to be able to define regions of the addres s space as
operating in different caching modes. This isn't strictly a caching issue, but is very relevant to the
operation of system and user software.
dual ported memory.
Use is made of the 68040's "Transparent T rans lation Regis ter s" and MMU "Page Tables" to define the
caching mode for different regions of the address space. The 68LC040 also has an MMU, and
functions exactly the same way as a 68040 in this respect. O n the 68EC040 however, although the
MMU is not available, the Transparent Tr anslation Regist ers are s till present, and can be us ed f or this
function, although the strategy needs to be slightly different.
The 68040's Transparent Translation Registers contain an address and mask f ield to allow definition
of an address range to be used. They also contain fields to specif y the relevant caching m odes for the
defined region. There are four regis ters, two for data DTT0 and DTT1 and two for instructions ITT0
and ITT1.
The TT0 registers override the TT1 registers if there is any overlap, and undefined regions will be
accessed in the 68040's default mode (write-through caching enabled) if the MMU is disabled. If the
MMU is enabled (not on 68EC040) any regions undefined in the TT regis ters will be checked in the
Page Tables. The Page Tables relate to a 4 or 8KByte region, and the caching mode is specified in a
field of the page descriptor in a similar way to the TT registers.
On the BVME4000 with a 68040 or 68LC040 processor, a c ache-inhibited, bus-serialised region can
be defined from $F0000000 to $FFFFFFFF for access to IP Memory, EPROM, SRAM, VMEbus A24,
VMEbus A16 & on-board registers for supervisor access. The rest of the address space is defined as
write-through caching for instructions and copy-back caching f or data for supervisor m ode. The page
descriptors would be used to define the regions f or us er-s tate acces ses, alloc ated on a dynamic basis
(by operating system software). The values that need to be set into the 68040 TT registers to
implement this scheme are as follows:
DTT0 = $F00FA040, DTT1 = $00FFA020, ITT0 = NOT USED, ITT1 = $00FFA000
On the BVME4000 with a 68EC040 processor, a similar scheme as that for the 68040/68LC040 can
be set up. This gives an I/O region from $F0000000 to $FFFFFFFF for supervisor and user-state
access, with the rest of the address space defined as write-through caching for instructions and
copyback caching for data for s upervisor and user-state access . The values that need to be s et into
the 68EC040 TT registers to implement this scheme are as follows:
DTT0 = $F00FC040, DTT1 = $00FFC020,ITT0 = NOT USED, ITT1=$00FFC000
Copyright 1993,1995,1998,2001 BVM Ltd.
63 BVME4000/6000
Note that instruction caching only functions in write-through mode, not copy-back m ode, as no writes
occur to the instruction address space. To use write-through cac hing in place of copyback, the "$20"
should be replaced by a "$00" in the above values for DTT1.
The DTT1 and IT T1 values could be changed to introduce a third region of write-through caching in
addition to copy-back caching as follows for the 68EC040:
DTT1 = $000FC020, ITT1 = $000FC000
Now the on-board RAM is defined as copy-back caching from $00000000 to $0FFFFFFF and the
region from $10000000 to $EFFFFFFF is defined as write-through caching (the 68EC040's default). A
similar mechanism may be used via the page descriptors when the MMU is used in the 68040 or
68LC040.
It is useful to have different regions def ined for the sam e address space, becaus e as the BVME4000
dual-maps some of the address space, it can be accessed in diff erent caching modes. If the above
scheme was adopted, then the VMEbus A24 space could be accessed at address $EE000000 as
write-through cached, and at address $FE000000 as cache-inhibited bus-serialised access.
The BVME4000 has three separate blocks capable of bus mas tership ( DMA) other than the pr ocess or
itself: the Ethernet Controller, SCSI Controller and the VMEbus Slave Inter face. When any of these
bus masters transfer data directly into a memory region (DMA), c ache coher ency problems c an occ ur,
as the processor may not know that data in it's internal caches is now invalid.
This problem can be approached in a number ways:
1. Normally main system memory resides on the BVME4000, and the 68040 can use "bussnooping" to monitor accesses to the memory by any of the other bus masters. The bussnooping must be enabled by programm ing the relevant bus-snoop enable bit(s) for the bus
master in question. For the Ethernet Controller and VMEbus Slave Interface, there is a
SNOOP ENABLE bit - refer to "7.10 VMEbus Slave Access Controller (on page 45) " for m ore
details. For the SCSI Controller, there are SNOOP MODE bits in it's register set - ref er to the
53C710 documentation detailed in the "A.4 53C710 Data Manual & Programmers Guide (on
page 60)" section of this manual.
2. The 68040's internal caches can be "flushed" if it is known that their data m ay be invalid (e.g.
when an interrupt occurs after a DMA operation). It m ay also be necessary to do a "cache
push" if copyback caching is in us e. This can be very wasteful, as data not involved in the
transfers at all will also be purged from the caches.
3. Non-cached regions can be used to acc ess the memory. For example, the Ethernet Controller
can be set-up to DMA into a separate buffer region (e.g. the SRAM), which is acc essed via a
non-cached address. In this cas e, bus-snooping is not required, but the data, once DMAed
into memory, is not subject to the advantages of caching. This does also have a potential
performance advantage, as there is a tim ing overhead involved in bus-snooping by the 68040
processor.
Other schemes may be determined by the user, or a combination of the above may be used in
conjunction.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 64
B.2 BVME6000 (MC68060)
The MC68060 is a superscaler 68000 s eries processor with separate data and instruction caches of
8Kbytes each. The cache unit supports full copyback caching, in addition to write-through caching (as
available on earlier processors), cache-inhibited imprecise-mode and precise-mode (bus-serialised)
cache modes.
Copyback caching means that when data is written out by the program, it m ay only reach the cache,
and not the main memory. This poses cache coherency problems over those nor m ally associated with
earlier 68000 series processor s (e.g. 68030), as the main memory can contain s tale data, affecting
DMA operations transferring data from dual-ported memory as well as to
Cache-inhibited precise-mode is required as the 68060's internal architecture has a high degree of
parallelism. Reads and writes do not occ ur in the order in which they are defined by the programm er.
Normally this causes no problem as the 68060 will detect any clashes and synchronise them, but if
accesses are being made to I/O areas for example, the ordering of reads and writes are very
important. Cache-inhibited precise-mode regions cause correct ordering of the reads and writes.
It follows on from the above that it is im portant to be able to define regions of the addres s space as
operating in different caching modes. This isn't strictly a caching issue, but is very relevant to the
operation of system and user software.
dual ported memory.
Use is made of the 68060's "Transparent T rans lation Regis ter s" and MMU "Page Tables" to define the
caching mode for different regions of the address space. The 68LC060 also has an MMU, and
functions exactly the same way as a 68060 in this respect. O n the 68EC060 however, although the
MMU is not available, the Transparent Tr anslation Regist ers are s till present, and can be us ed f or this
function, although the strategy needs to be slightly different.
The 68060's Transparent Translation Registers contain an address and mask f ield to allow definition
of an address range to be used. They also contain fields to specif y the relevant caching m odes for the
defined region. There are four regis ters, two for data DTT0 and DTT1 and two for instructions ITT0
and ITT1.
The TT0 registers override the TT1 registers if there is any overlap, and undefined regions will be
accessed in the 68060's default m ode set in the "Translation Control Register" T CR (normally writethrough caching enabled) if the MMU is disabled. If the MMU is enabled (not on 68EC060) any regions
undefined in the TT registers will be check ed in the Page Tables. The Page Tables relate to a 4 or
8KByte region, and the caching mode is specified in a field of the page des criptor in a similar way to
the TT registers.
On the BVME6000 with a 68060 or 68LC060 processor, a cache-inhibited, prec ise-mode region can
be defined from $F0000000 to $FFFFFFFF for access to IP Memory, EPROM, SRAM, VMEbus A24,
VMEbus A16 & on-board registers for supervisor access. The rest of the address space is defined as
write-through caching for instructions and supervisor data access. The page descriptors would be
used to define the regions for user -s tate ac c ess es inc luding copyback r egions, alloc ated on a dynamic
basis (by operating system software). The values that need to be set into the 68060 T T registers to
implement this scheme are as follows:
DTT0 = $F00FA040, DTT1 = $00FFA000, ITT0 = NOT USED, ITT1 = $00FFA000
On the BVME6000 with a 68EC060 processor, a similar scheme as that for the 68060/68LC060 can
be set up. This gives an I/O region from $F0000000 to $FFFFFFFF for supervisor and user-state
access, with the rest of the address space defined as write-through caching for instructions and
supervisor data, and copyback caching for us er-state data ac cess . T he values that need to be set into
the 68EC060 TT registers to implement this scheme are as follows:
DTT0 = $F00FC040, DTT1 = $00FFC020,ITT0 = NOT USED, ITT1=$00FFC000
Copyright 1993,1995,1998,2001 BVM Ltd.
65 BVME4000/6000
Note that instruction caching only functions in write-through mode, not copy-back m ode, as no writes
occur to the instruction address space. To use write-through cac hing in place of copyback, the "$20"
should be replaced by a "$00" in the above values for DTT1.
The DTT1 and IT T1 values could be changed to introduce a third region of write-through caching in
addition to copy-back caching as follows for the 68EC060:
DTT1 = $000FC020, ITT1 = $000FC000
Now the on-board RAM is defined as copy-back caching from $00000000 to $0FFFFFFF and the
region from $10000000 to $EFFFFFFF is defined as default caching set in the TCR (norm ally writethrough caching enabled). A similar m echanism m ay be used via the page descr iptors when the MMU
is used in the 68060 or 68LC060.
It is useful to have different regions def ined for the sam e address space, becaus e as the BVME6000
dual-maps some of the address space, it can be accessed in diff erent caching modes. If the above
scheme was adopted, then the VMEbus A24 space could be accessed at address $EE000000 as
write-through cached, and at address $FE000000 as cache-inhibited precise-mode access.
The BVME6000 has three separate blocks capable of bus mas tership ( DMA) other than the pr ocess or
itself: the Ethernet Controller, SCSI Controller and the VMEbus Slave Inter face. When any of these
bus masters transfer data directly into a memory region (DMA), c ache coher ency problems c an occ ur,
as the processor may not know that data in it's internal caches is now invalid.
This problem can be approached in a number ways:
1. Normally main system memory resides on the BVME6000, and the 68060 can use "bussnooping" to monitor accesses to the memory by any of the other bus masters. The bussnooping must be enabled by programm ing the relevant bus-snoop enable bit(s) for the bus
master in question. For the Ethernet Controller and VMEbus Slave Interface, there is a
SNOOP ENABLE bit - refer "7.10 VMEbus Slave Access Controller (on page 45)" for more
details. For the SCSI Controller, there is the SC0 SNOOP MODE bit in it's register s et - refer
to the 53C710 documentation detailed in the "A.4 53C710 Data Manual & Programmers Guide
(on page 60)" section of this manual. The m em or y must be acc essed in write- through cac hing
mode as the 68060 can only invalidate cache entries, unlike the 68040 which can source and
sink data from/to the cache. This means that supervisor accesses (i.e. operating system
software) are write-through, whereas user-state accesses would normally be copyback.
2. The 68060's internal caches can be "flushed" if it is known that their data m ay be invalid (e.g.
when an interrupt occurs after a DMA operation). It m ay also be necessary to do a "cache
push" if copyback caching is in us e. This can be very wasteful, as data not involved in the
transfers at all will also be purged from the caches.
3. Non-cached regions can be used to acc ess the memory. For example, the Ethernet Controller
can be set-up to DMA into a separate buffer region (e.g. the SRAM), which is acc essed via a
non-cached address. In this cas e, bus-snooping is not required, but the data, once DMAed
into memory, is not subject to the advantages of caching. This does also have a potential
performance advantage, as there is a tim ing overhead involved in bus-snooping by the 68060
processor.
Other schemes may be determined by the user, or a combination of the above may be used in
conjunction.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 66
Appendix C Memory Module Pinout
M1 M2 M3
PIN Name Function PIN Name Function PIN Name Function
1 A31 1 /RST Reset Module 1 D0
2 A30 2 TT1 Transfer 2 D1
3 A29 3 TT0 Type # 3 D2
4 A28 4 TM2 Transfer 4 D3
5 A27 5 TM1 Modifier# 5 D4
6A26 6TM0 6 D5
7 A25 7 +5V 5 Volt Power 7 D6
8 A24 8 /W E Write Enable # 8 D7
9 A23 A 9 SIZ1 Transfer 9 D8
10 A22 D 10 SIZ0 Size # 10 D9 D
11 A21 D 11 GND Ground 11 D10 A
12 A20 R 12 /TS Transf er S tart # 12 D11 T
13 A19 E 13 /TIP Trans. In Prog. # 13 D12 A
14 A18 S 14 /LOCK Locked (RMW) # 14 D13
15 A17 S 15 +5V 5 Volt Power 15 D14 L
16 A16 16 /TA Transfer Ac k. # 16 D15 I
17 A15 L 17 SC1 Snoop 17 D16 N
18 A14 I 18 SC0 Control # 18 D17 E
19 A13 N 19 GND Ground 19 D18 S
20 A12 E 20 CLK CPU Clock # 20 D19
21 A11 S 21 GND Ground 21 D20 #
22 A10 22 /MIRQ Module IRQ 22 D21
23 A9 # 23 / MI Memory Inhibit # 23 D22
24 A8 24 +5V 5 Volt Power 24 D23
25 A7 25 GND Ground 25 D24
26 A6 26 CLK2 CPU Clock2 # 26 D25
27 A5 27 GND Ground 27 D26
28 A4 28 MERR Module Error 28 D27
29 A3 29 N/C No Connect 29 D28
30 A2 30 GND Ground 30 D29
31 A1 31 +5VSB 5V Standby Power 31 D30
32 A0 32 +12V 12 Volt Power 32 D31
NOTES: This allows connection to a BVM Memory Module. # indicates a direct connection to the
equivalent processor signal, see the MC68040 and MC68060 m anual or data sheet f or an
explanation. /RST is a general reset signal, /MIRQ is an interrupt signal fr om the m odule,
and MERR is a bus error signal from the module. The 12 volt power connection is not
switched, and is intended for FLASH memory programming on those modules that
support it. The 5 volt standby power supply is connected directly to the VMEbus +5STDBY
line, and is intended for non-volatile SRAM backup on those modules that support it.
The interface is not intended f or us er connec tion, the pinout is provided her e f or r ef erenc e
only.
Some mem ory modules pr ovide a JT AG progr am m ing strip to allow direc t progr am m ing f rom the hos t
module. This connec tor detail is k nown as M4, the connections are s hown below, and are for factory
use only.
M4
PIN Name PIN Name
1TCK6Vcc
2 GND 7 TDO
3TMS8GND
4GND9TRST
5 TDI 10 ENABLE
Copyright 1993,1995,1998,2001 BVM Ltd.
67 BVME4000/6000
Appendix D IP Expansion Interface Pinout
J3 Pin Row a Row b
1GNDGND
2 /WE /RESET
3D16D17
4D18D19
5D20D21
6D22D23
7D24D25
8D26D27
9D28D29
10 D30 D31
11 /BS0 /BS1
12 A5 A6
13 GND GND
14 /IPLWRD SA1
15 CS0 CS1
16 CS2 CS3
17 A11 /IPL0
18 /IPL1 /IPL2
19 IACK /IPCYC
20 /CSIOD /CSMEM
21 D0 D1
22 D2 D3
23 D4 D5
24 D6 D7
25 D8 D9
26 D10 D11
27 D12 D13
28 D14 D15
29 A3 A4
30 A1 A2
31 /ACKA /ACKB
32 GND GND
NOTES: This allows connection to a BVM IP Expansion Daughter Board (e.g. EXP100). The
BVME4000/6000 architecture provides for a further 6 IP sites to be added via this
extension interface. The interface allows full capability sites to be added including Interrupt
Control, 32-bit operation 8MHz, 32MHz and CPU Synchronous speeds.
The interface is not intended f or us er connec tion, the pinout is provided her e f or r ef erenc e
only.
Copyright 1993,1995,1998,2001 BVM Ltd.
BVME4000/6000 68
Appendix E Thermal Management
BVME4000
25MHz
MC68EC/LC040
33MHz
MC68EC/LC040
25MHz
MC68040
33MHz
MC68040
BVME6000
50MHz
MC68EC/LC060
66MHz
MC68EC/LC060
50MHz
MC68060
66MHz
MC68060
NOTES: Temperatures shown above are for ambient air temperature.
If operation above 50 °C for extended periods is antic ipated, then it is recomm ended that
the airflow is doubled, or (where not already specified) a heatsink is fitted.
25 °C 50 °C 70 °C
No Heatsink
No Airflow
No Heatsink
No Airflow
No Heatsink
No Airflow
No Heatsink
Natural Airflow
25 °C 50 °C 70 °C
No Heatsink
No Airflow
No Heatsink
No Airflow
No Heatsink
No Airflow
No Heatsink
Natural Airflow
No Heatsink
No Airflow
No Heatsink
Natural Airflow
No Heatsink
Natural Airflow
No Heatsink
0.5m/s Airflow
No Heatsink
No Airflow
No Heatsink
0.5m/s Airflow
No Heatsink
Natural Airflow
No Heatsink
0.5m/s Airflow
No Heatsink
0.5m/s Airflow
No Heatsink
0.5m/s Airflow
No Heatsink
0.5m/s Airflow
Heatsink
1.0m/s Airflow
No Heatsink
0.5m/s Airflow
No Heatsink
1.0m/s Airflow
No Heatsink
0.5m/s Airflow
No Heatsink
1.0m/s Airflow
Where a heatsink is specified, fit AAVID part 3325 24 B 0 0032.
Copyright 1993,1995,1998,2001 BVM Ltd.
69 BVME4000/6000
Appendix F Circuit Diagrams
NOTE: Circuit diagrams are provided here for customer reference only. This information was
current at the time this User Manual was last revised. This information is not necessarily
current or complete manufacturing data, nor is it part of the product specification.
Copyright 1993,1995,1998,2001 BVM Ltd.
This is the master sheet for the
BVME4000/6000 rev F.
87654321
D
Processor and Memory
pro_mem.sch
2
C
Ethernet
eth.sch
3
SCSI
scsi.sch
B
4
This sheet contains:
Processor socket
SRAM
EPROM
MM Interface
This sheet contains:
Ethernet Interface
- Takes CPUCLK1
This sheet contains:
SCSI Interface
- Takes CPUCLK1
Industry Pack Interface
ip.sch
5
VME Interface
vme.sch
6
Peripherals and Interrupts
periph.sch
7
This sheet contains:
Industry Pack Interface
IP Connectors
EXP100 Connector
- Takes CPUCLK1
This sheet contains:
VME Interface
P1 & P2 Connectors
This sheet contains:
Serial Port
Parallel Port
Real Time Clock
Peripheral Control PAL
Interrupt Control PAL
Power and Reset
pwr.sch
8
This sheet contains:
3.3 V Power Supply
Reset Circuit
Oscillator Circuit
Battery Circuit
General De-Couplers
D
C
B
A
1 2 3 4 5 6 78
BVM Ltd.
Hobb Lane.
Hedge End
Southampton
SO30 0GH
(01489) 780144
Title
BVME4000/6000
Issue Dwg No.
7 BVM00228
Sheet 1 of 8
Drawn By
S J Bush
Date
Size
10 December 1998
Approved
A
A3
8
IC17F
13 12
SC0 /SNOOP
7654321
74F14
A[0..31]
Vcc
R400
Vcc
4K7
R401
Vcc
4K7
R402
Vcc
D
4K7
R403
Vcc
4K7
R404
Vcc
4K7
R405
Vcc
4K7
R406
Vcc
4K7
R407
Vcc
4K7
R408
Vcc
4K7
R409
Vcc
4K7
R410
Vcc
4K7
R411
Vcc
4K7
R412
Vcc
4K7
R413
Vcc
4K7
R414
Vcc
4K7
R415
Vcc
4K7
R416
Vcc
4K7
R417
Vcc
4K7
R418
Vcc
4K7
R419
Vcc
4K7
R420
Vcc
4K7
R421
Vcc
4K7
R422
Vcc
4K7
R423
Vcc
4K7
R424
Vcc
4K7
R425
Vcc
4K7
R426
Vcc
4K7
R427
Vcc
4K7
R428
Vcc
4K7
R429
Vcc
4K7
R430
Vcc
4K7
R431
4K7
C
JP7
5
4
3
+12V
2
1
HEADER 5
B
D[0..31]
A
A[0..31]
IC2
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
R35
4K7
VCC
GND
A31
D3
A30
A30
B1
A29
A29
E3
A28
A28
C1
A27
A27
E2
A26
A26
F3
A25
A25
D1
A24
A24
G3
A23
A23
E1
A22
A22
F1
A21
A21
G1
A20
A20
J2
A19
A19
H1
A18
A18
J1
A17
A17
K2
A16
A16
K1
A15
A15
L1
A14
A14
M1
A13
A13
N1
A12
A12
N3
A11
A11
P1
A10
A10
F16
A9
A9
E18
A8
A8
F18
A7
A7
G16
A6
A6
G18
A5
A5
H18
A4
A4
J18
A3
A3
J17
A2
A2
K18
A1
A1
L18
A0
A0
PVcc
K15
CLA(060)
D18
D31
D31
E17
D30
D30
E16
D29
D29
C18
D28
D28
D16
D27
D27
B18
D26
D26
C16
D25
D25
A18
D24
D24
C15
D23
D23
B16
D22
D22
A17
D21
D21
A16
D20
D20
A15
D19
D19
B12
D18
D18
A14
D17
D17
B11
D16
D16
A13
D15
D15
A12
D14
D14
A11
D13
D13
A10
D12
D12
A9
D11
D11
A8
D10
D10
A7
D9
D9
B7
D8
D8
A6
D7
D7
A5
D6
D6
A4
D5
D5
A3
D4
D4
A2
D3
D3
C4
D2
D2
B3
D1
D1
C3
D0
D0
L15
THERM0(060)
M15
THERM1(060)
A1
A31
68040/060
D[0..31]
VMEMST
/VMEAS
PST2
SC0(040)
SC1(040)
MI(040)
SNOOP(060)
BGR(060)
BTT(060)
IPEND
PST4(060)
BCLK(040)
CLKEN(060)
JTAG(060)/GND(040)
LOCKE
CIOUT
BS0(060)
BS1(060)
BS2(060)
BS3(060)
SAS(060)
TRA(060)
DLE(040)
IC67A
1
2
74F38
T12
SC0
SC0
S12
SC1
SC1
Q16
/MI
/SNOOP
/BR040
/BG040
PVCC
/MDIS
/CPURST
/IPL2
/IPL1
/IPL0
/AVEC
PST2
CPUCLK
CLK_X_2
TT1
TT0
TM2
TM1
TM0
/CPUWE
SIZ1
SIZ0
/LOCK
/LOCKE
/TS
/TIP
/TA
/TEA
/TCI
/TBI
Vcc
/MI
/BR040
/BG040
/BBSY
/CPURST
/IPL2
/IPL1
/IPL0
/AVEC
CPUCLK
CLK_X_2
/CLKEN
TCK
TMS
GND
TDF
TDG
/TRST
TT1
TT0
TM2
TM1
TM0
/CPUWE
SIZ1
SIZ0
/LOCK
/LOCKE
/TS
/TA
/TEA
/TBI
PVcc
R28
4K7
Vcc
R66
10K
IC67B
4
5
74F38
8
R100
10K
IC67D
12
GLED
13
74F38
P15
T18
BR
T13
BG
Q11
T17
BB
Q15
T5
CDIS
S6
MDIS
S7
RSTI
R3
RSTO
T6
IPL2
T7
IPL1
T8
IPL0
S1
T11
AVEC
Q13
T16
PST3
R14
PST2
S14
PST1
T15
PST0
R7
R9
PCLK
Q8
T4
S4
TCK
S5
TMS
S3
TDI
T2
TDO
T3
TRST
P2
TT1
P3
TT0
K17
TM2
M18
TM1
N18
TM0
P18
TLN1
Q18
TLN0
Q1
UPA1
Q3
UPA0
N16
WE
P16
SIZ1
P17
SIZ0
S18
LOCK
R18
R1
Q4
Q5
Q6
Q7
R16
TS
R15
TIP
Q14
T14
TA
Q12
S13
TEA
T10
TCI
S11
TBI
T9
IC67C
9
10
74F38
3
Vcc
R34
4K7
PVcc
R30
Vcc
R16
4k7
PVcc
4K7
R33
4K7
PVcc
R17
4K7
M1
D0
1
D1
2
D2
3
D3
4
D4
5
D5
6
D6
7
D7
8
D8
9
D9
10
D10
11
D11
12
D12
13
D13
14
D14
15
D15
16
D16
17
D17
18
D18
19
D19
20
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
CPUCLK2
21
/MIRQ
22
23
24
25
26
27
/MEMOK
28
29
30
+5VSB
31
32
CON32
/CPURST
TT1
TT0
TM2
TM1
TM0
VCC
/CPUWE
SIZ1
SIZ0
GND
/TS
/TIP
/LOCK
VCC
/TA
RES'VD
RES'VD
GND
GND
/MIRQ
/MI
VCC
GND
CLK_X_2
GND
/MEMOK
GND
+5VSB
+12V
M2
1
2
3
4
5
6
(+5V)
7
8
9
10
11
12
13
14
(+5V)
15
16
17
18
19
20
21
22
23
(+5V)
24
25
26
27
28
29
30
31
32
CON32
M3
A31
1
A30
2
A29
3
A28
4
A27
5
A26
6
A25
7
A24
8
A23
9
A22
10
A21
11
A20
12
A19
13
A18
14
A17
15
A16
16
A15
17
A14
18
A13
19
A12
20
A11
21
A10
22
A9
23
A8
24
A7
25
A6
26
A5
27
A4
28
A3
29
A2
30
A1
31
A0
32
CON32
MEMORY MODULE INTERFACE
/ROMOE
/ROMLE
/ROMOE
/ROMLE
/ROMWE
IC60
3
22
A0
A1
A2
A3
A4
A5
A6
A7
OEAB
LEAB
CEAB
OEBA
LEBA
CEBA
74ABT543
R631KR64
1
11
R61
330R
D15
B0
21
D14
B1
20
D8
B2
19
D13
B3
18
D9
B4
17
D12
B5
16
D10
B6
15
D11
B7
IC36
2
D03Q0
5
D14Q1
6
D27Q2
9
D38Q3
12
D413Q4
15
D514Q5
16
D617Q6
19
D718Q7
OE
LE
74AC373 (VRAM)
JP8
1 2
3 4
5 6
7 8
/ENABLE /ENABLE
9 10
HEADER 5X2
D31
4
D30
5
D24
6
D29
7
D25
8
D28
9
D26
10
D27
13
14
11
2
1
23
/ROMOE
/ROMLE
/ROMWE
/ETHBE0
/ETHBE1
/ETHBE2
/ETHBE3
VCC VCC
1K
TCK
TMS
TDI
TDO
/TRST
R62
330R
GND GND
IC61
3
22
A0
A1
A2
A3
A4
A5
A6
A7
OEAB
LEAB
CEAB
OEBA
LEBA
CEBA
74ABT543
D7
B0
21
D6
B1
20
D0
B2
19
D5
B3
18
D1
B4
17
D4
B5
16
D2
B6
15
D3
B7
D23
4
D22
5
D16
6
Vcc
R21
Vcc
4K7
R22
4K7
PVcc
R18
Vcc
4K7
R20
4K7
Vcc
R15
4K7
D21
7
D17
8
D20
9
D18
10
D19
13
/ROMWE /ROMWE
14
11
A1 A1
2
/ROMOE
1
/ROMLE
23
GND GND
LK5
1 2
GND
Vcc
R37
330R
LED2
REDLED
6
/RLED
12
C69
+
10uF
A19
11 10
GND
Vcc
R36
330R
LED1
GRNLED
11
/GLED
12
C68
+
10uF
/ETHBE0
VRAM
/ETHBE1
R65
/ETHBE2
10K
/ETHBE3
IC17E
/RAMCS
74F14
VRAM
R38
10K
TCK
TMS
TDA
TDH
/TRST /ENABLE
GND
/RAMBE0
/RAMBE1
/RAMBE2
/RAMBE3
/A19
D8
D9
D10
D11
D12
D13
D14
D15
ROMHI
D0
D1
D2
D3
D4
D5
D6
D7
PPIN1
ROMHI
PPIN1
A19
/ROMWE
A20
A19
IC45
13
14
15
17
18
19
20
21
31
1
12
ROMA1
A0
D0
11
A2
A1
D1
10
A3
A2
D2
9
A4
A3
D3
8
A5
A4
D4
7
A6
A5
D5
6
A7
A6
D6
5
A8
A7
D7
27
A9
A8
26
A10
A9
23
A11
A10
25
A12
A11
4
A13
A12
28
A14
A13
29
A15
A14
3
A16
A15
PGM
2
A17
A16
VPP
30
PPIN30
A17
22
GND
CE
24
/ROMOE
OE
PROM32
IC44
D0
D1
D2
D3
D4
D5
D6
D7
PGM
VPP
PROM32
1
3
1
3
VRAM
12
ROMA1
A0
11
A2
A1
10
A3
A2
9
A4
A3
8
A5
A4
7
A6
A5
6
A7
A6
5
A8
A7
27
A9
A8
26
A10
A9
23
A11
A10
25
A12
A11
4
A13
A12
28
A14
A13
29
A15
A14
3
A16
A15
2
A17
A16
30
PPIN30
A17
22
GND
CE
24
/ROMOE
OE
ROMA1
LK14
LK15
VRAM
R51
R52
10K
10K
VCC
GND
LK10
1
VCC
2
PPIN30
3
A18
LK11
1
VCC
2
ROMHI
(31)
3
2
LK12
1
VCC
2
PPIN1
3
2
VRAM
VRAM
R53
R54
10K
10K
M4
TCK
1
GND
2
TMS
3
GND
4
VCC
GND
/TRST
BVM Ltd.
Hobb Lane.
Hedge End
Southampton
SO30 0GH
(01489) 780144
5
6
7
8
9
10
HEADER 10
Title
Issue Dwg No.
Drawn By
TDG
TDH
13
14
15
17
18
19
20
21
31
1
ROMA1
VRAM
R50
10K
/RAMWE
/RAMWE
/RAMOE
/RAMOE
IC10
13
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
A0
D0
14
A1
D1
15
A2
D2
17
A3
D3
18
A4
D4
19
A5
D5
20
A6
D6
21
A7
D7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
CS1
OE
WE
628128/512
IC9
13
A0
D0
14
A1
D1
15
A2
D2
17
A3
D3
18
A4
D4
19
A5
D5
20
A6
D6
21
A7
D7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
CS1
OE
WE
628128/512
IC8
13
A0
D0
14
A1
D1
15
A2
D2
17
A3
D3
18
A4
D4
19
A5
D5
20
A6
D6
21
A7
D7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
CS1
OE
WE
628128/512
IC7
13
A0
D0
14
A1
D1
15
A2
D2
17
A3
D3
18
A4
D4
19
A5
D5
20
A6
D6
21
A7
D7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
CS1
OE
WE
628128/512
BVME4000/60000
7 BVM00228
Sheet 2 o f 8
S J Bush
12
A2
11
A3
10
A4
9
A5
8
A6
7
A7
6
A8
5
A9
27
A10
26
A11
23
A12
25
A13
4
A14
28
A15
3
A16
31
A17
2
A18
30
/A19
1
A20
22
/RAMBE0
24
/RAMOE
29
/RAMWE
12
A2
11
A3
10
A4
9
A5
8
A6
7
A7
6
A8
5
A9
27
A10
26
A11
23
A12
25
A13
4
A14
28
A15
3
A16
31
A17
2
A18
30
/A19
1
A20
22
/RAMBE1
24
/RAMOE
29
/RAMWE
12
A2
11
A3
10
A4
9
A5
8
A6
7
A7
6
A8
5
A9
27
A10
26
A11
23
A12
25
A13
4
A14
28
A15
3
A16
31
A17
2
A18
30
/A19
1
A20
22
/RAMBE2
24
/RAMOE
29
/RAMWE
12
A2
11
A3
10
A4
9
A5
8
A6
7
A7
6
A8
5
A9
27
A10
26
A11
23
A12
25
A13
4
A14
28
A15
3
A16
31
A17
2
A18
30
/A19
1
A20
22
/RAMBE3
24
/RAMOE
29
/RAMWE
D
C
B
A
Size
Date
10 December 1998
Approved
A2
1 2 3 4 5 6 78
7654321
8
D
A[0..31]
A[0..31]
C
BRENET
B
D[0..31]
D[0..31]
HOLDA
/ETHBOFF
/LOCK
/ETHBRQ
CPUCLK1
ETHRST
/ETHPORT
/ETHCA
/ETHINT
/ETHADS
/TA
R108
ETHWE
Vcc
10K
IC3
70
A31
A31
71
A30
A30
72
A29
A29
73
A28
A28
74
A27
A27
76
A26
A26
79
A25
A25
80
A24
A24
81
A23
A23
82
A22
A22
83
A21
A21
84
A20
A20
85
A19
A19
87
A18
A18
90
A17
A17
91
A16
A16
92
A15
A15
93
A14
A14
94
A13
A13
95
A12
A12
96
A11
A11
97
A10
A10
101
A9
A9
102
A8
A8
103
A7
A7
104
A6
A6
105
A5
A5
106
A4
A4
107
A3
A3
108
A2
A2
53
D31
D31
52
D30
D30
51
D29
D29
50
D28
D28
48
D27
D27
47
D26
D26
46
D25
D25
43
D24
D24
42
D23
D23
41
D22
D22
40
D21
D21
39
D20
D20
38
D19
D19
37
D18
D18
36
D17
D17
35
D16
D16
32
D15
D15
31
D14
D14
30
D13
D13
29
D12
D12
28
D11
D11
27
D10
D10
26
D9
D9
25
D8
D8
21
D7
D7
20
D6
D6
19
D5
D5
18
D4
D4
17
D3
D3
16
D2
D2
15
D1
D1
14
D0
D0
123
HOLD
118
HLDA
116
BOFF
126
/LOCK
LOCK
117
GND
AHOLD
115
BREQ
9
CLK
69
RESET
3
PORT
119
CA
125
INT
124
ADS
130
RDY
2
BRDY
128
BLAST
120
WE
65
BE
82596CA
GND
TXD
TXC
LPBK
RXD
RXC
RTS
CTS
CRS
CDT
BS16
BE3
BE2
BE1
BE0
DP3
DP2
DP1
DP0
PCHK
54
64
58
60
59
57
62
63
61
ETHCLK
129
109
112
113
114
7
6
5
4
127
ETHCLK
IC4
17
TXD
16
15
GND
14
13
Vcc
Vcc
R12
4K7
Vcc
R13
4K7
Vcc
Vcc
R10910K
COLL-
TXC
COLL+
3
LB/WDT
9
RXD
RXC
TEN
CSN
COLL
X1
X2
8023A-PLCC
Vcc
R14
4K7
/BS16
/ETHBE3
/ETHBE2
/ETHBE1
/ETHBE0
RX-
RX+
TX-
TX+
MODE?
MODE?
/BS16
/ETHBE3
/ETHBE2
/ETHBE1
/ETHBE0
Vcc
R3210K
Vcc
R11010K
8
6
7
R11
4K7
R11110K
C1
11
12
5
4
18
19
39R
R1
39R
100n
R2
39R
C2
R3
39R
R4
100n
240R
R5
240R
R6
1
2
VCC
PSU1
2
VIN
+V
1
GND
0V
NML0509S
GND
510R
-9V
BNC_CL+
R8
510R
BNC_CL-
R9
510R
BNC_RC+
R10
10
11
BNC_RC-
R23
510R
BNC_TR+
BNC_TR-
5
6
7
8
9
4
3
VEE
VEE
VEE
VEE
VEE
VEE
VEE
PT1
1
2
4
5
7
8 9
PULSE TRAN
SHIELD
F2
-9V
0.2A
3
2
4
CD-
CD+
RX+
DP8392CV
RX-
TX-14TX+13GND16GND
12
-9V
123
CDS1TXO
HBE
15
LK6
BNC_CL-
16
BNC_CL+
15
BNC_RC-
13
12
10
BNC_RC+
BNC_TR-
BNC_TR+
For MAU (Thick Ethernet):
All links to right
For BNC (Cheapernet):
All Links to left
SHIELD
2
D1
1N4150
28
26
27
IC5
NC
RXI
25
VEE
24
VEE
23
VEE
22
VEE
21
VEE
20
VEE
19
RR-
RR+
17
18
SHIELD
Heart Beat Enable Link
Fit 1-2 for Disable
(normal Operation)
Fit 2-3 For Enable
(Factory Test)
SHIELD
MAU_CL-
246
LK7
135
MAU_CL+
MAU_RC-
246
LK8
135
MAU_RC+
MAU_TR-
246
LK9
135
MAU_TR+
1
JP4
BNC
-9V
C100
100nF
R7
1K0
D
C
B
A
Title
BVM Ltd.
Hobb Lane.
Hedge End
Southampton
SO30 0GH
(01489) 780144
BVME4000/6000
Issue Dwg No.
7 BVM00228
Sheet 3 o f 8
Drawn By
S J Bush
Date
10 December 1998
Approved
A
Size
A2
1 2 3 4 5 6 78
7654321
8
D
D[0..31]
A[0..31]
SC1
SC0
/BRSCSI
/BGSCSI
/BBSY
TT1
TT0
TM2
TM1
TM0
/CPUWE
SIZ1
SIZ0
/TS
/TA
/TEA
/TBI
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SC1
SC0
/BBSY
SCSIPU
TT1
TT0
TM2
TM1
TM0
/CPUWE
SIZ1
SIZ0
/TS
/TA
/TEA
/TBI
IC6
24
A31
23
A30
21
A29
20
A28
18
A27
17
A26
16
A25
14
A24
13
A23
12
A22
11
A21
10
A20
8
A19
7
A18
5
A17
4
A16
3
A15
1
A14
160
A13
159
A12
158
A11
157
A10
155
A9
154
A8
152
A7
151
A6
150
A5
148
A4
147
A3
146
A2
145
A1
144
A0
42
D31
43
D30
44
D29
45
D28
47
D27
48
D26
50
D25
51
D24
53
D23
55
D22
56
D21
57
D20
58
D19
59
D18
60
D17
62
D16
65
D15
66
D14
67
D13
68
D12
70
D11
71
D10
72
D9
73
D8
76
D7
77
D6
78
D5
80
D4
81
D3
83
D2
84
D1
85
D0
89
SC1
88
SC0
101
BR
100
BG
98
BB
95
BOFF
33
TT1
34
TT0
28
TM2
29
TM1
30
TM0
32
WE
26
SIZ1
27
SIZ0
25
TS
40
TIP
36
TA
37
TEA
35
TBI
53C710
SBSYDIR
SSELDIR
SRSTDIR
MASTER
ENDIAN
SATN
SACK
SMSG
SREQ
SDIR0
SDIR1
SDIR2
SDIR3
SDIR4
SDIR5
SDIR6
SDIR7
SDIRP
SCLK
SLACK
FETCH
BCLK
A[0..31]
C
B
D[0..31]
D3
1NS817
/SCD0
/SCD1
/SCD2
/SCD3
/SCD4
/SCD5
/SCD6
/SCD7
/SCDP
SCPWR
/SCATN
/SCBSY
/SCACK
/SCRST
/SMSG
/SCSEL
/SCCD
/SCREQ
/SCIO
F_12V
GND GND
F_5V F_12V
SCSCLK
VccR112
10K
/CPURST
/SCSINT
CPUCLK1
Vcc
R29
10K
/SCSICS
F1
SCPWR
1.5A
J1
/SCD0
/SCD1
/SCD2
/SCD3
/SCD4
/SCD5
/SCD6
/SCD7
/SCDP
/SCBSY
/SCACK
/SCRST
/SMSG
/SCSEL
/SCCD
/SCREQ
/SCIO
1
3
5
GND
SCPWR
/SCATN
J14
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
CON50A
2
4
6
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
GND
VCC
F3
F_5V
2A
F4
+12V
2A
IC69
17
16
/SCD5
14
/SCD3
13
/SCD1
8
/SCD0
7
/SCD2
6
/SCD4
5
/SCD6
4
/SCDP
TL2218-285
1
SCPWR SCPWR/SCD7
TPWR1
D8
20
TPWR2
D7
D6
19
/STERM /STERM
DISABLE
D5
D4
D3
D2
D1
D0
/STERM
LK13
1 2
/SCREQ
/SCSEL
/SCRST
/SCBSY
/SCATN
/SCACK
/SMSG
/SCCD
/SCIO
IC70
17
16
14
13
8
7
6
5
4
1
TPWR1
D8
20
TPWR2
D7
D6
19
DISABLE
D5
D4
D3
D2
D1
D0
TL2218-285
VCC
131
/SCD0
SD0
130
/SCD1
SD1
129
/SCD2
SD2
127
/SCD3
SD3
126
/SCD4
SD4
125
/SCD5
SD5
124
/SCD6
SD6
122
/SCD7
SD7
121
/SCDP
SDP
120
/SCATN
119
/SCBSY
SBSY
117
/SCACK
116
/SCRST
SRST
115
/SMSG
114
/SCSEL
SSEL
112
/SCCD
SCD
111
/SCREQ
110
/SCIO
SIO
142
141
140
138
137
135
134
133
132
108
106
107
104
SIGS
103
STGS
102
SCSCLK
92
38
97
52
DP3
63
DP2
74
DP1
86
DP0
91
GND
BS
90
VCC
94
/CPURST
RST
105
/SCSINT
IRQ
41
87
SCSIPU
DLE
93
CS
GND
D
C
B
A
Title
BVM Ltd.
Hobb Lane.
Hedge End
Southampton
SO30 0GH
(01489) 780144
BVME4000/6000
Issue Dwg No.
7 BVM00228
Sheet 4 o f 8
Drawn By
S J Bush
Date
10 December 1998
Approved
A
Size
A2
1 2 3 4 5 6 78
7654321
8
Industry Pack I/O Connectors
J6
JP5A
D
C
B
A[0..31]
A
D[0..31]
A[0..31]
D[0..31]
/IPADDR
/IPADDR
/IPADDR
/IPADDR
IC24
2
4
1A
1B
2A
2B
3A
3B
4A
4B
G
A/B
74ACT257
IC23
1A
1B
2A
2B
3A
3B
4A
4B
G
A/B
74ACT257
IC25
1A
1B
2A
2B
3A
3B
4A
4B
G
A/B
74ACT257
IC26
1A
1B
2A
2B
3A
3B
4A
4B
G
A/B
74ACT257
IC27
1A
1B
2A
2B
3A
3B
4A
4B
G
A/B
74ACT257
IC28
1A
1B
2A
2B
3A
3B
4A
4B
G
A/B
74ACT257
IPA1
1Y
7
IPA2
2Y
9
IPA3
3Y
12
IPA4
4Y
4
1Y
7
IPA5
2Y
9
3Y
12
IPA6
4Y
4
SD0
1Y
7
SD1
2Y
9
SD2
3Y
12
SD3
4Y
4
SD4
1Y
7
SD5
2Y
9
SD6
3Y
12
SD7
4Y
4
SD8
1Y
7
SD9
2Y
9
SD10
3Y
12
SD11
4Y
4
SD12
1Y
7
SD13
2Y
9
SD14
3Y
12
SD15
4Y
SA1
3
5
A2
6
11
A3
10
14
A4
13
A5
15
GND
1
IPD32
2
3
VCC
5
A5
6
11
10
GND
14
A6
13
A7
15
GND
1
IPD32
2
A7
3
5
A8
6
11
A9
10
14
A10
13
A11
15
1
IPD32
2
A11
3
5
A12
6
11
A13
10
14
A14
13
A15
15
1
IPD32
2
A15
3
5
A16
6
11
A17
10
14
A18
13
A19
15
1
IPD32
2
A19
3
5
A20
6
11
A21
10
14
A22
13
A23
15
1
IPD32
D7
D6
D5
D4
D3
D2
D1
D0
/LOEIP
/IPLLE
/IPOEL
/IPLLE
D15
D14
D13
D12
D11
D10
D9
D8
/LOEIP
/IPLLE
/IPOEL
/IPLLE
D23
D22
D21
D20
D19
D18
D17
D16
/UOEIP
/IPULE
/IPOEL
/IPULE
D31
D30
D29
D28
D27
D26
D25
D24
/UOEIP
/IPULE
/IPOEL
/IPULE
IC29
3
22
A0
B0
4
21
A1
B1
5
20
A2
B2
6
19
A3
B3
7
18
A4
B4
8
17
A5
B5
9
16
A6
B6
10
15
A7
B7
13
OEAB
14
LEAB
11
GND
CEAB
2
OEBA
1
LEBA
23
GND
CEBA
74ABT43
IC30
3
22
A0
B0
4
21
A1
B1
5
20
A2
B2
6
19
A3
B3
7
18
A4
B4
8
17
A5
B5
9
16
A6
B6
10
15
A7
B7
13
OEAB
14
LEAB
11
GND
CEAB
2
OEBA
1
LEBA
23
GND
CEBA
74ABT543
IC31
3
22
A0
B0
4
21
A1
B1
5
20
A2
B2
6
19
A3
B3
7
18
A4
B4
8
17
A5
B5
9
16
A6
B6
10
15
A7
B7
13
OEAB
14
LEAB
11
GND
CEAB
2
OEBA
1
LEBA
23
GND
CEBA
74ABT543
IC32
3
22
A0
B0
4
21
A1
B1
5
20
A2
B2
6
19
A3
B3
7
18
A4
B4
8
17
A5
B5
9
16
A6
B6
10
15
A7
B7
13
OEAB
14
LEAB
11
GND
CEAB
2
OEBA
1
LEBA
23
GND
CEBA
74ABT543
/IPCSMEM
XM4
CLK
XM8-32M
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
19
/SWAP
GND
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
19
/SWAP
GND
SD23
SD22
SD21
SD20
SD19
SD18
SD17
SD16
SD31
SD30
SD29
SD28
SD27
SD26
SD25
SD24
IC71
2
A26
1A
3
A10
1B
5
A25
2A
6
A9
2B
11
A24
3A
10
A8
3B
14
A23
4A
13
A7
4B
15
/IPIAK
G
1
A/B
74ACT257
/CLK16M CLK16M
5
CLK32M
SD[0..31]
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
IC33
A1
A2
A3
A4
A5
A6
A7
A8
G
NC
QS3245Q
IC34
A1
A2
A3
A4
A5
A6
A7
A8
G
NC
QS3245Q
18
SD23
B1
17
SD22
B2
16
SD21
B3
15
SD20
B4
14
SD19
B5
13
SD18
B6
12
SD17
B7
11
SD16
B8
18
SD31
B1
17
SD30
B2
16
SD29
B3
15
SD28
B4
14
SD27
B5
13
SD26
B6
12
SD25
B7
11
SD24
B8
4
IPCS3
1Y
7
IPCS2
2Y
9
IPCS1
3Y
12
IPCS0
4Y
J4
GND
1
IPCLKA IPCLKB
2
3
SD0
4
SD1
5
SD2
6
SD3
7
SD4
8
SD5
9
SD6
10
SD7
11
SD8
12
SD9
13
SD10
14
SD11
15
SD12
16
SD13
17
SD14
18
SD15
19
/IPBS0
20
/IPBS1
21
-12VIPA
22
+12VIPA
23
+5VIPA
24
GND
25
GND
26
+5VIPA
27
/CPUWE /CPUWE
28
/IDSELA
29
30
/MEMSELA
31
32
/INTSELA
33
/IPDAKA /IPDAKB
34
/IOSELA
35
36
IPA1
37
/IPDENDA /IPDENDB
38
IPA2
39
/IPERRA /IPERRB
40
IPA3
41
/IPIRQA0
42
IPA4
43
/IPIRQA1
44
IPA5
45
/IPSTBA /IPSTBB
46
IPA6
47
/IPACKA
48
49
GND
X 1 5
RN1
SMRNC10K
X 1 5
RN2
SMRNC10K
50
IPCON
16
1
SD9
2
SD8
3
SD6
4
SD5
5
SD4
6
SD3
7
SD2
8
SD1
9
SD0
10
11
12
/IPDAKA
13
14
SD7
15
/IPDENDA
16
1
/IPACKA
2
/IPSTBA
3
/IPIRQA1
4
SD15
5
SD14
6
SD13
7
SD12
8
SD11
9
SD10
10
11
/IPIRQA0
12
13
14
15
VCC VCC
VCC
VCC
4
IC39A
2
5
D
Q
PR
3
CLK
6
Q
CL
74F74
VCC
1
CLK16M
/CLK16M
VCC
GND
/CPURST/CPURST
SD16
SD17
SD18
SD19
SD20
SD21
SD22
SD23
SD24
SD25
SD26
SD27
SD28
SD29
SD30
SD31
/IPBS0
/IPBS1
-12VIPB
+12VIPB
+5VIPB
GND
GND
+5VIPB
/IDSELB
/MEMSELB
/INTSELB
/IOSELB
IPA1
IPA2
IPA3
/IPIRQB0
IPA4
/IPIRQB1
IPA5
IPA6
/IPACKB
GND
X 1 5
RN3
SMRNC10K
X 1 5
RN4
SMRNC10K
J5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
CPUCLK1
38
39
CLK8M
40
41
/CPURST
42
43
/IPCSMEM
44
/IPCSIOD
45
/IPAKIN
46
47
48
/Q_TIP
49
50
IPCON
16
1
SD25
2
SD24
3
SD22
4
SD21
5
SD20
6
SD19
SD18
SD17
SD16
/IPDAKB
SD23
/IPDENDB
/IPACKB
/IPSTBB
/IPIRQB1
SD31
SD30
SD29
SD28
SD27
SD26
/IPIRQB0
SIZ1
SIZ0
/CPUWE
TM2
TM1
TM0
/IPIFWE
TCK
TMS
TDB
TDC
/TRST
/ENABLE
-12VIPA
+12VIPA
+5VIPA
+5VIPB
SIPCLKA IPCLKA
SIPCLKB IPCLKB
SIPCLKD IPCLKD
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
J3A
GND
1
/CPUWE
2
SD16
3
SD18
4
SD20
5
SD22
6
SD24
7
SD26
8
SD28
9
SD30
10
/IPBS0
11
IPA5
12
GND
13
/IPLWRD
14
IPCS0
15
IPCS2
16
A11
17
/IPINT1
18
/IPIAK
19
/IPCSIOD
20
SD0
21
SD2
22
SD4
23
SD6
24
SD8
25
SD10
26
SD12
27
SD14
28
IPA3 IPA4
29
IPA1 IPA2
30
/IPACKDA /IPACKDB
31
GND
32
CON32
IC43
13
CLKSY
18
CLK32M
/CPURST
/IPCSMEM
/IPCSIOD
/IPAKIN
/IPINT2
/IPINT1
/IPINT0
/IPIRQA0
/IPIRQA1
/IPIRQB0
/IPIRQB1
/IPIFWE
/CPUWE
CLK32M
86
CLK8M
97
RESET
93
IPCSMEM
23
IPCSIOD
63
IPIAKIN
43
/Q_TIP
TIP
21
A11
IPCS4
35
IPCS3
IPCS3
37
IPCS2
IPCS2
31
IPCS1
IPCS1
33
IPCS0
IPCS0
56
A1
A1
55
A0
A0
8
SIZ1
SIZ1
99
SIZ0
SIZ0
34
CPUWE
69
TM2
TM2
68
TM1
TM1
62
TM0
TM0
61
IPINT2
75
IPINT1
73
IPINT0
72
IPINTA1
71
IPINTA2
70
IPINTB1
58
IPINTB2
36
REGWE
60
D2
D2
59
D1
D1
54
D0
D0
28
TCK
27
TMS
3
TDI
78
TDO
77
TRST
53
ENABLE
MACH446-IPIF
-12VIPA
+12VIPA
+5VIPA
+5VIPB
R200
33R
R201
33R
R202
33R
J3B
IPCLKD
1
/CPURST
2
SD17
3
SD19
4
SD21
5
SD23
6
SD25
7
SD27
8
SD29
9
SD31
10
/IPBS1
11
IPA6
12
GND
13
A1
14
IPCS1
15
IPCS3
16
/IPINT0
17
/IPINT2
18
/IPCYC
19
/IPCSMEM
20
SD1
21
SD3
22
SD5
23
SD7
24
SD9
25
SD11
26
SD13
27
SD15
28
29
30
31
GND
32
CON32
IPCLK2
IPCLK1
IPCLK0
IPADDREN
IPIAKOUT
MEMSELA
IOSELA
IDSELA
INTSELA
MEMSELB
IOSELB
IDSELB
INTSELB
ACKDA
ACKDB
IPENC2
IPENC1
IPENC0
IPLWRD
-12VIPB
+12VIPB
OEL
LOEIP
UOEIP
SWAP
LLE
ULE
SA1
IPCYC
IPDS1
IPDS0
ACKA
ACKB
IPD32
TA
-12VIPB
+12VIPB
BVM Ltd.
Hobb Lane.
Hedge End
Southampton
SO30 0GH
(01489) 780144
CON50
32
SIPCLKD
44
SIPCLKB
50
SIPCLKA
83
/IPADDR
95
/IPOEL
96
/LOEIP
94
/UOEIP
81
/SWAP
100
/IPLLE
98
/IPULE
24
SA1
76
/IPCYC
26
/IPIAK
57
/IPBS1
87
/IPBS0
7
/MEMSELA
11
/IOSELA
10
/IDSELA
25
/INTSELA
9
/MEMSELB
5
/IOSELB
12
/IDSELB
20
/INTSELB
49
/IPACKA
47
/IPACKDA
46
/IPACKB
45
/IPACKDB
6
/IPENC2
19
/IPENC1
22
/IPENC0
38
/IPLWRD
48
IPD32
74
/TA
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44
45
45
46
46
47
47
48
48
49
49
50
50
IPCON
/IPENC2
/IPENC1
/IPENC0
/TA
Title
BVME4000/6000
Issue Dwg No.
7 BVM00228
Sheet 5 o f 8
Drawn By
S J Bush
Date
1 2 3 4 5 6 78
JP5B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CON50
10 December 1998
Approved
J7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
IPCON
D
C
B
A
Size
A2
D
D[0..31]
A[0..31]
/VMESLV
VMEMST
C
SC1
SC0
/VSLVWE
/ETHMST
TCK
TMS
TDC
TDD
/TRST
/ENABLE
CPUCLK
/CPURST
/LOCK
/LOCKE
SIZ1
SIZ0
B
/TS
/TA
/TEA
/CPUWE
/TBI
/Q_TIP
R92
/CSVIAK
Vcc
/MEMOK
4K7
/VSLVIAK
/BRVME
/BGVME
/BBSY
/LOCDET
/SYSCON
/RRS
RQLVL1
RQLVL0
TCK
TMS
TDE
TDF
/TRST
A
/ENABLE
TDE TDF
TDE TDF
1 2 3 4 5 6 78
No VME
VME
D[0..31]
A[0..31]
/VMESLV
VMEMST
/CPURST
/A16OK
/VSLVRQ
/VSLVWE
/CSVIAK
/MEMOK
/VSLVRQ
/VSLVIAK
/BRVME
/BGVME
/BBSY
/A16OK
/LOCDET
/SYSCON
/RRS
RQLVL1
RQLVL0
LK23
0R
SC1
SC0
/TS
/TA/TA
/TEA
/CPUWE
/TBI
/Q_TIP
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
D7
D6
D5
D4
D3
D2
D1
D0
/ETHMST
CPUCLK
/CPURST
/LOCK
/LOCKE
CS3
CS2
CS1
CS0
/Q_TIP
/TBI
/MEMOK
SIZ1
SIZ0
A1
A0
VD8
VD9
VD10
VD11
VD12
VD13
VD14
VD15
GND
/VSFAIL
/VBERR
/VRESET
/VLWORD
VAM5
VA23
VA22
VA21
VA20
VA19
VA18
VA17
VA16
VA15
VA14
VA13
VA12
VA11
VA10
VA9
VA8
+12V
RXDA
CTSA
DCDA
RXCLKA
RXDB
CTSB
DCDB
RXCLKB
GND+12V
/SCREQ/SCIO
/SCSEL
/SCRST/SMSG
/SCBSY/SCACK
SCPWR
/SCD7/SCDP
/SCD5/SCD6
/SCD3/SCD4
/SCD1/SCD2
GND
GND
PDATA[1..8]
10 December 1998
Approved
MAU_RCMAU_CL-MAU_CL+
/PACKNOW
RXDA
CTSA
DCDA
RXCLKA
RXDB
CTSB
DCDB
RXCLKB
8
Vcc
13
IC1D
74ABT125
D
C
B
R67
10K
1112
A
Size
A2
7654321
12
/A16OK
LK200R
12
VA14_I
LK160R
12
VA13_I
LK170R
Fitted
IC12
31
LA31
32
LA30
33
LA29
50
LA28
49
LA27
48
LA26
56
LA25
57
LA24
100
LA23
99
LA22
98
LA21
26
LA20
25
LA19
24
LA18
75
LA17
74
LA16
93
VMESLV
35
VMEMST
62
RESET
8
A16OK
5
VMEREQ
20
SC1
19
SC0
13
WSTB
97
D7
96
D6
94
D5
95
D4
23
D3
22
D2
21
D1
18
D0
34
ETHMST
28
TCK
27
TMS
3
TDI
78
TDO
77
TRST
53
ENABLE
MACH446-VSLV
IC11
13
CPUCLK
95
RESET
60
LOCK
46
LOCKE
25
SIZ1
24
SIZ0
35
A1
26
A0
8
TS
10
TA
11
TEA
96
CPUWE
94
TBI
44
TIP
38
CS3
37
CS2
36
CS1
97
CS0
34
CSVIAK
54
MEMOK
86
VSLVRQ
85
VSLVIAK
93
BRVME
63
BGVME
33
BBSY
45
A16OK
31
LOCDET
68
SYSCON
84
RRS
23
RQLVL1
18
RQLVL0
28
TCK
27
TMS
3
TDI
78
TDO
77
TRST
53
ENABLE
MACH446-VMST
12
IPCSMEM
IPCSIOD
TESTEN
VMEMST
VLWORD
VDTKOUT
VDTKIN
VBERROUT
VMESLV
VBBSYIN
VBBSYOUT
VBROUT
VBRIN3
VBRIN2
VBRIN1
VBRIN0
VBGIN3
VBGIN2
VBGIN1
VBGIN0
VBGOUT3
VBGOUT2
VBGOUT1
VBGOUT0
VBERR
VBCLR
VA31
VA30
VA29
VA28
VA27
VA26
VA25
VA24
VA23
VA22
VA21
VA20
VA19
VA18
VA17
VA16
VA15
VA14
VA13
VA12
VA11
VA10
VA09
VA08
VAM5
VAM4
VAM3
VAM1
VAM0
VIAK
VDS1
VDS0
LOEV
SOEV
UOEV
LOEL
SOEL
UOEL
INVA1
Not Fitted
CS3
CS2
CS1
CS0
VAS
LLE
SLE
ULE
12
VA14
LK240R
12
VA13
LK250R
FittedNot Fitted
/VRSTOUT
IC35A
74F32
IC35B
74F32
IC35C
74F32
IC35D
74F32
IC52
A0
A1
A2
A3
A4
A5
A6
A7
OEAB
LEAB
CEAB
OEBA
LEBA
CEBA
74ABT543
IC55
A0
A1
A2
A3
A4
A5
A6
A7
OEAB
LEAB
CEAB
OEBA
LEBA
CEBA
74ABT543
IC57
A0
A1
A2
A3
A4
A5
A6
A7
OEAB
LEAB
CEAB
OEBA
LEBA
CEBA
74ABT543
IC58
A0
A1
A2
A3
A4
A5
A6
A7
OEAB
LEAB
CEAB
OEBA
LEBA
CEBA
74ABT543
/VBROUT[0..3]
22
VD0
B0
21
VD1
B1
20
VD2
B2
19
VD3
B3
18
VD4
B4
17
VD5
B5
16
VD6
B6
15
VD7
B7
22
VD8
B0
21
VD9
B1
20
VD10
B2
19
VD11
B3
18
VD12
B4
17
VD13
B5
16
VD14
B6
15
VD15
B7
/VILVL0
/VILVL1
/VILVL2
/VMEINT
22
VD0
B0
21
VD1
B1
20
VD2
B2
19
VD3
B3
18
VD4
B4
17
VD5
B5
16
VD6
B6
15
VD7
B7
22
VD8
B0
21
VD9
B1
20
VD10
B2
19
VD11
B3
18
VD12
B4
17
VD13
B5
16
VD14
B6
15
VD15
B7
3
/CLLE
6
/CSLE
8
/CULE
11
/CLKEN
38
54
43
44
45
46
47
58
88
87
86
85
84
83
82
81
73
72
71
68
63
61
60
59
76
70
69
55
37
36
10
7
9
11
12
6
4
57
48
50
49
43
9
58
47
32
19
20
21
5
6
12
100
99
98
22
7
82
81
83
70
73
72
71
59
69
76
75
74
61
62
55
56
VA31
VA30
VA29
VA28
VA27
VA26
VA25
VA24
VA23
VA22
VA21
VA20
VA19
VA18
VA17
VA16
VA15
VA14_I
VA13_I
VA12
VA11
VA10
VA9
VA8
VMEAM5
VMEAM4
VMEAM3
VMEAM1
VMEAM0
/VMEIAK
CS3
CS2
CS1
CS0
/IPCSMEM
/IPCSIOD
R39
Vcc
10K
VMEMST
/VMEAS
/VMEDS1
/VMEDS0
/VMELWORD
/VDTKOUT
/VDTACK
/VBERR
/VBERROUT
/LOEV
/SOEV
/UOEV
/LLE
/SLE
/ULE
/LOEL
/SOEL
/UOEL
/INVA1
/VMESLV
/VBBSY
/VBBSYOUT
/VMEBCLR
/VBROUT
/VBR3
/VBR2
/VBR1
/VBR0
/VBG3IN
/VBG2IN
/VBG1IN
/VBG0IN
/VBG3OUT
/VBG2OUT
/VBG1OUT
/VBG0OUT
IC53
2
18
74F623
IC54
74F623
IC40
74F623
IC56
74F623
IC41
74F623
IC50
74F623
IC64
74F14
IC65
BU4S584
/VDS1
A1
B1
17
/VLWORD
A2
B2
16
/VDS0
A3
B3
15
VAM5
A4
B4
14
VAM0
A5
B5
13
VAM1
A6
B6
12
/VAS
A7
B7
11
VAM2
A8
B8
GBA
GAB
18
VAM3
A1
B1
17
/VIAK
A2
B2
16
A3
B3
15
VAM4
A4
B4
14
A5
B5
13
VA3
A6
B6
12
VA2
A7
B7
11
VA1
A8
B8
GBA
GAB
18
VA23
A1
B1
17
VA22
A2
B2
16
VA21
A3
B3
15
VA20
A4
B4
14
VA19
A5
B5
13
VA18
A6
B6
12
VA17
A7
B7
11
VA16
A8
B8
GBA
GAB
18
VA6
A1
B1
17
VA12
A2
B2
16
VA5
A3
B3
15
VA11
A4
B4
14
VA4
A5
B5
13
VA10
A6
B6
12
VA9
A7
B7
11
VA8
A8
B8
GBA
GAB
18
VA24
A1
B1
17
VA25
A2
B2
16
VA26
A3
B3
15
VA27
A4
B4
14
VA28
A5
B5
13
VA29
A6
B6
12
VA30
A7
B7
11
VA31
A8
B8
GBA
GAB
18
/VWE
A1
B1
17
A2
B2
16
A3
B3
15
A4
B4
14
VA15
A5
B5
13
VA7
A6
B6
12
VA14
A7
B7
11
VA13
A8
B8
GBA
GAB
/VIRQ7
/VIRQ6
/VIRQ5
/VIRQ4
/VIRQ3
/VIRQ2
/VIRQ1
CPUCLK
/LLE
/SLE
/ULE
1
I0
O0
3
I1
O1
5
I2
O2
9
I3
O3
11
I4
O4
13
I5
O5
24
3
D0
4
D1
5
D2
6
D3
7
D4
8
D5
9
D6
10
D7
13
/LOEV
14
/CLLE
11
GND
2
/LOEL
1
/CLLE
23
GND
3
D8
4
D9
5
D10
6
D11
7
D12
8
D13
9
D14
10
D15
13
/LOEV
14
/CLLE
11
GND
2
/LOEL
1
/CLLE
23
GND
3
D16
4
D17
5
D18
6
D19
7
D20
8
D21
9
D22
10
D23
13
/SOEV
14
/CSLE
11
GND
2
/SOEL
1
/CSLE
23
GND
3
D24
4
D25
5
D26
6
D27
7
D28
8
D29
9
D30
10
D31
13
/SOEV
14
/CSLE
11
GND
2
/SOEL
1
/CSLE
23
GND
1
2
4
5
9
10
12
13
/VMEDS1
3
/VMELWORD
4
/VMEDS0
5
VMEAM5
6
VMEAM0
VMEAM0
VMEAM1
VMEAM2
VMEA3
VMEA2
VMEA1
/VMEIAK
CS3
CS2
CS1
CS0
/IPCSMEM
/IPCSIOD
VMEMST
/VMEAS
/VMEDS0
/INVA1
VMEAM1
/VMEAS
VMEAM2
A6
A12
A5
A11
A4
A10
A9
A8
A24
A25
A26
A27
A28
A29
A30
A31
A15
A7
A14
A13
VIRQ7
VIRQ6
VIRQ5
VIRQ4
VIRQ3
VIRQ2
VMEMST
VMEMST
A23
A22
A21
A20
A19
A18
A17
A16
VCC
VMEMST
/VMESLV
VMEMST
VCC
VMEMST
/CPUWE
VMEAM3
/VMEIAK
VMEAM4
VMEA3
VMEA2
VMEA1
/VMESLV
VMEMST
7
8
9
19
1
2
3
4
5
6
7
8
9
19
1
2
3
4
5
6
7
8
9
19
1
2
3
4
5
6
7
8
9
19
1
2
3
4
5
6
7
8
9
19
1
2
3
4
5
6
7
8
9
19
1
2
4
6
8
10
12
VIRQ1
/VRSTOUT
/VRSTIN
IC49
2
/VBBSYOUT
3
/VBERROUT
4
/VRESET
5
/VMERST
6
/VBROUT0
7
/VBROUT1
8
/VBROUT2
9
/VBROUT3
19
VCC
1
VCC
74F621
IC48
2
/VDTKOUT /VDTACK
3
/VINT7
4
/VINT6
5
/VINT5
6
/VINT4
7
/VINT3
8
/VINT2
9
/VINT1
19
VCC
1
VCC
74F621
IC62
1
/VILVL0
2
/VILVL1
3
/VILVL2
6
VCC
4
/VMEINT
5
74HCT138
IC37
3
D16
4
D17
5
D18
6
D19
7
D20
8
D21
9
D22
10
D23
13
/UOEV
14
/CULE
11
GND
2
/UOEL
1
/CULE
23
GND
74ABT543
IC38
3
D24
4
D25
5
D26
6
D27
7
D28
8
D29
9
D30
10
D31
13
/UOEV
14
/CULE
11
GND
2
/UOEL
1
/CULE
23
GND
74ABT543
RQLVL1
RQLVL0
Vcc
R70
10K
GND
LK3
1 2
LK4
1 2
D12
RB751V-40
18
A1
B1
17
A2
B2
16
A3
B3
15
A4
B4
14
A5
B5
13
A6
B6
12
A7
B7
11
A8
B8
GBA
GAB
18
A1
B1
17
A2
B2
16
A3
B3
15
A4
B4
14
A5
B5
13
A6
B6
12
A7
B7
11
A8
B8
GBA
GAB
15
A
Y0
14
B
Y1
13
C
Y2
12
Y3
11
Y4
10
G1
Y5
9
G2A
Y6
7
G2B
Y7
22
A0
B0
21
A1
B1
20
A2
B2
19
A3
B3
18
A4
B4
17
A5
B5
16
A6
B6
15
A7
B7
OEAB
LEAB
CEAB
OEBA
LEBA
CEBA
22
A0
B0
21
A1
B1
20
A2
B2
19
A3
B3
18
A4
B4
17
A5
B5
16
A6
B6
15
A7
B7
OEAB
LEAB
CEAB
OEBA
LEBA
CEBA
GND
/SYSCON_A /SYSCON
/SYSCON_A
2
RQLVL1
3
RQLVL0
1
/VBROUT
14
13
15
Vcc
/VBBSY
/VBERR
/VRSTIN
/VRESET
/VBR0
/VBR1
/VBR2
/VBR3
/VIRQ7
/VIRQ6
/VIRQ5
/VIRQ4
/VIRQ3
/VIRQ2
/VIRQ1
VD16
VD17
VD18
VD19
VD20
VD21
VD22
VD23
VD24
VD25
VD26
VD27
VD28
VD29
VD30
VD31
IC68A
74F139
IC68B
74F139
Vcc
R68
R49
10K
100K
/VMERST
/CPURST
/CPURST
P1A
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
/VDS1
A12
/VDS0
A13
/VWE
A14
A15
/VDTACK
A16
A17
/VAS
A18
A19
/VIAK
A20
/VIAKIN
A21
/VIAKOUT
A22
A23
A24
A25
A26
A27
A28
A29
A30
-12V
10
Vcc
R44
10K
/VBROUT0
/VBROUT1
/VBROUT2
/VBROUT3
A31
A32
P2A
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
PDATA[1..8]
89
R55
10K
GND
/VBROUT[0..3]
BVM Ltd.
Hobb Lane.
Hedge End
Southampton
SO30 0GH
(01489) 780144
/VINT7
/VINT6
/VINT5
/VINT4
/VINT3
/VINT2
/VINT1
LK22
12
LINK2
IC1C
74ABT125
4
A
Y0
5
B
Y1
6
Y2
7
G
Y3
12
A
Y0
11
B
Y1
10
Y2
9
G
Y3
P1B
VD0
VD1
VD2
VD3
VD4
VD5
VD6
VD7
GND
VSYSCLK
GND
GND
GND
GND
VAM4
VA7
VA6
VA5
VA4
VA3
VA2
VA1
TXDA
RTSA
DTRA
SCLKOUTA
TXDB
RTSB
DTRB
SCLKOUTB
GND GND
/SCCD
/SCATN
GND GND
/SCD0
GND VCC
PDATA8 PDATA7
PDATA6 PDATA5
PDATA4 PDATA3
PDATA2 PDATA1
/PSTROBE
PBUSY
/VBBSY
B1
/VBCLR
B2
B3
/VBG0IN
B4
/VBG0OUT
B5
/VBG1IN
B6
/VBG1OUT
B7
/VBG2IN
B8
/VBG2OUT
B9
/VBG3IN
B10
VSYSCLK
/VBG3OUT
B11
/VBR0
B12
/VBR1
B13
/VBR2
B14
/VBR3
B15
B16
B17
B18
B19
B20
B21
/VIAKIN
B22
/VIAKOUT
B23
/VIRQ7
B24
/VIRQ6
B25
/VIRQ5
B26
/VIRQ4
B27
/VIRQ3
B28
/VIRQ2
B29
/VIRQ1
B30
+5VSB
B31
-12V +12V
VCCVCC VCC
B32
P2B
B1
TXDA
B2
RTSA
B3
DTRA
B4
SCLKOUTA
B5
TXDB
B6
RTSB
B7
DTRB
B8
SCLKOUTB
B9
MAU_TR+ MAU_TR-
B10
MAU_RC+
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
/SYSCON
CLK16M
CLK16M
/SYSCON
/VMEBCLR
Title
BVME4000/6000
Issue Dwg No.
Sheet 6 o f 8
Drawn By
P1C
C1
C2
/ACFAIL
VAM0
VAM1
VAM2
VAM3
GND
GND
VCC
GND
VA24
VA25
VA26
VA27
VA28
VA29
VA30
VA31
GND
VCC
VD16
VD17
VD18
VD19
VD20
VD21
VD22
VD23
GND
VD24
VD25
VD26
VD27
VD28
VD29
VD30
VD31
GND
VCC
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
+5VSB
C31
C32
P2C
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
4
5 6
VSYSCLK
IC1B
74ABT125
1
2 3
/VBCLR
IC1A
74ABT125
7 BVM00228
Date
S J Bush
JP3
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
JP1
1 2
3 4
5 6
7 8
9 10
11 12
13 14
HDR7X2
JP2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
HDR7X2
XM3
CLK
NC
XM8-7.3728MHz
10 December 1998
Approved
8
D
C
5
BAUDCLK
1
B
A
Size
A2
7654321
IC59
13
CPUCLK1
/TS
/TA
/TEA
/CPUWE
TT1
TT0
TM2
TM1
TM0
SIZ1
SIZ0
A1
A0
CS3
CS2
CS1
CS0
/BBSY
/LOCK
/LOCKE
/BRVME
/CSVIAK
/IPENC2
/IPENC1
/IPENC0
/RTCINT
/TIMINT
/PARINT
/SERINT
/LOCDET
/MIRQ
/ETHERR
VMEMST
/VMESLV
/INVA1
/IPLWE
CPUCLK
/CPURST
/ACFAIL
ABORT
/TS
/TA
/TEA
CPUCLK
18
RESET
6
TS
83
TA
38
TEA
33
CPUWE
69
TT1
73
TT0
72
TM2
20
TM1
36
TM0
76
SIZ1
75
SIZ0
74
A1
48
A0
34
CS3
23
CS2
22
CS1
4
CS0
61
TIMIAK
60
PARIAK
59
SERIAK
7
BBSY
46
LOCK
45
LOCKE
54
BR040
55
BRSCSI
35
BRENET
47
BRVME
63
MI
43
ETHADS
44
ETHWE
68
CSVIACK
28
TCK
27
TMS
3
TDI
78
TDO
77
TRST
53
ENABLE
MACH446-PERIPH
IC42
18
CPUCLK
88
RESET
87
IPENC2
86
IPENC1
85
IPENC0
4
ACFAIL
69
ABORT
68
RTCINT
54
TIMINT
63
PARINT
35
SERINT
62
LOCDET
61
ETHINT
60
SCSINT
59
MEMINT
13
ETHERR
58
TS
56
TA
55
TEA
26
TT1
TT1
25
TT0
TT0
34
TM2
TM2
10
TM1
TM1
8
TM0
TM0
24
A3
LA3
98
A2
LA2
32
A1
LA1
12
VMEMST
9
VMESLV
46
INVA1
11
REGCS
96
D7
D7
93
D6
D6
48
D5
D5
100
D4
D4
95
D3
D3
94
D2
D2
49
D1
D1
31
D0
D0
28
TCK
27
TMS
3
TDI
78
TDO
77
TRST
53
ENABLE
MACH446-IPL
CPUCLK1
/CPURST
/CPURST
/TS
/TA
/TEA
D
/CPUWE
TT1
TT0
TM2
TM1
TM0
SIZ1
SIZ0
CS3
CS2
CS1
CS0
/TIMACK
/TIMACK
/PARACK
/PARACK
/SERACK
/SERACK
/BBSY
/LOCK
/LOCKE
/BR040
/BRSCSI
BRENET
/BRVME
/MI
/ETHADS
ETHWE
/CSVIAK
TCK
TMS
C
TDA
TDB
/TRST
/ENABLE
CPUCLK
/IPENC2
/IPENC1
/IPENC0
/ACFAIL
/LOCDET
/ETHINT
R94
/SCSINT
Vcc
/MIRQ
4K7
B
TT1
TT0
TM2
TM1
TM0
VMEMST
/VMESLV
/INVA1
TCK
TMS
TDD
TDE
/TRST
/ENABLE
A
ROMOE
ROMLE
ROMWE
ROMA1
RAMWE
RAMOE
SERCLK
SERWR
BGG040
BGSCSI
BGVME
ETHBRQ
HOLDA
ETHERR
ETHRST
ETHBE3
ETHBE2
ETHBE1
ETHBE0
ETHMST
ETHPORT
VSLVWE
CONFRD
PITCLK
PITACK
SERCS
SERRD
RTCCS
ETHCA
IPLWE
IPIFWE
SCSICS
57
/Q_TIP
TIP
50
71
PITCS
58
97
98
21
82
100
99
96
86
87
88
81
56
19
26
49
8
11
12
BOFF
70
BS16
84
24
25
32
31
62
85
9
37
10
94
95
93
IPL2
IPL1
IPL0
VIRQ7
VIRQ6
VIRQ5
VIRQ4
VIRQ3
VIRQ2
VIRQ1
AVEC
VMEACK
IPACK
TIMACK
PARACK
SERACK
VIAK
VIAKIN
VIAKOUT
VDS0
VA3
VA2
VA1
VMEAM2
VMEAM1
VMEAM0
VSLVIAK
VMEINT
VILVL2
VILVL1
VILVL0
PITCLK
/PITCS
/PITACK
SERCLK
/SERCS
/SERRD
/SERWR
/RTCCS
/BGVME
/ETHERR
/ETHMST
/IPLWE
/IPIFWE
/VSLVWE
/CONFRD
36
37
38
84
82
81
73
72
71
70
76
75
44
74
43
50
21
47
6
45
20
19
33
22
83
23
7
99
97
57
5
/ROMOE
/ROMLE
/ROMWE
ROMA1
/RAMWE
/RAMOE
/CSVIAK
/IPAKIN
/TIMACK
/PARACK
/SERACK
/VMEIAK
/VIAKIN
/VIAKOUT
/VMEDS0
VMEA3
VMEA2
VMEA1
VMEAM2
VMEAM1
VMEAM0
/VSLVIAK
/VMEINT
/VILVL2
/VILVL1
/VILVL0
/Q_TIP
/BG040
/BGSCSI
/BGVME
/ETHBRQ
HOLDA
/ETHBOFF
/BS16
ETHRST
/ETHBE3
/ETHBE2
/ETHBE1
/ETHBE0
/ETHMST
/ETHPORT
/ETHCA
/IPIFWE
/VSLVWE
/SCSICS
/IPL2
/IPL1
/IPL0
VIRQ7
VIRQ6
VIRQ5
VIRQ4
VIRQ3
VIRQ2
VIRQ1
/AVEC
/IPAKIN
/VMEIAK
/VIAKIN
/VIAKOUT
/VMEDS0
VMEA3
VMEA2
VMEA1
VMEAM2
VMEAM1
VMEAM0
/VSLVIAK
/VMEINT
/VILVL2
/VILVL1
/VILVL0
Vcc
Vcc
R40
R42
10K
10K
Vcc
Vcc
R41
R43
10K
8
7
6
5
1 2
SW1
1 2
10K
IC63
3
CSW3
A1
4
CSW2
A2
5
CSW1
A3
6
CSW0
A4
1
/CONFRD
GAB
13
GND
GBA
74F243
Vcc
R31
4K7
LK1
IC17D
9 8
74F14
SW3
1
2
3
4
C12
220pF
A[0..31]
D[0..31]
D[0..31]
STXDA
SRTSA
SRXDA
SCTSA
SDTRA
SDTRB
SDCDA
SDCDB
STXDB
SRTSB
SRXDB
SCTSB
/PEN
PDIR
BAUDCLK
BAUDCLK
RXCLKA
RXCLKA
BAUDCLK
RXCLKB
BAUDCLK
RXCLKB
SCLKSL0
SCLKSL1
IC16
2
A1
B1
3
A2
B2
4
A3
B3
5
A4
B4
6
A5
B5
7
A6
B6
8
A7
B7
9
A8
B8
19
G
1
DIR
74ABT245
IC17B
34
74F14
IC17C
5 6
74F14
IC17A
12
74F14
IC20
12
1
C+
C9
+
4u7
2
8
7
9
6
12
C7
+
4u7
12
C11
+
4u7
V+
T1OUT
C-
T2OUT
T1IN
R1IN
T2IN
R2IN
R1OUT
R2OUT
V-
MAX231
IC19
1
C+
T1OUT
2
C-
T2OUT
8
T1IN
R1IN
7
T2IN
R2IN
9
R1OUT
6
R2OUT
MAX231
IC21
1
C+
T1OUT
2
C-
T2OUT
8
T1IN
R1IN
7
T2IN
R2IN
9
R1OUT
6
R2OUT
MAX231
IC22
6
1C0
1Y
5
1C1
4
1C2
3
1C3
10
2C0
2Y
11
2C1
12
2C2
13
2C3
14
A
2
B
1
1G
15
2G
74F153
GND
BVM Ltd.
Hobb Lane.
Hedge End
Southampton
SO30 0GH
(01489) 780144
IC15
48
D0
D0
49
D1
D1
50
D2
D2
51
D3
D3
52
D4
D4
1
D5
D5
2
D6
D6
3
D7
D7
45
/PITCS
/CPUWE
/CPURST
11
D3
B1
10
D2
B2
9
D1
B3
8
D0
B4
/TIMACK
/PARACK
PITCLK
A2
A3
A4
A5
A6
T1OUT
CE
47
WR
43
RESET
44
BCLK
32
RS1
31
RS2
30
RS3
29
RS4
28
RS5
41
TIACK
40
PIACK
36
TIN
MC68230FN
IC18
1
D0
D0
2
D1
D1
44
D2
D2
3
D3
D3
43
D4
D4
4
D5
D5
42
D6
D6
5
D7
D7
38
ABORT
A[0..31]
R113
4K7
/SERCS
/SERRD
/SERWR
Vcc
/RTCCS
/SERRD
/SERWR
/L_PFAIL
VBATT
SERCLK
A3
A2
D0
D1
D2
D3
D4
D5
D6
D7
A2
A3
A4
A5
A6
/SERACK
/SERINT
VCC
CE
41
RD
40
WR
39
A/B
37
D/C
9
INTACK
6
INT
8
IEI
7
IEO
23
CLK
Z8530V
IC14
18
D0
19
D1
20
D2
21
D3
22
D4
23
D5
24
D6
25
D7
1
CE
2
RD
3
WR
4
A0
5
A1
6
A2
7
A3
8
A4
27
PFAIL
11
VBB
DP8570AV
DTACK
RTXCA
TRXCA
SYNCA
W/REQA
RTXCB
TRXCB
SYNCB
W/REQB
OSC_IN
OSC_OUT
4
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
H1
H2
H3
H4
PC0
PC1
PC4
TOUT
PIRQ
RXDA
TXDA
RTSA
CTSA
DTRA
DCDA
RXDB
TXDB
RTSB
CTSB
DTRB
DCDB
INTR
MFO
T1
TCK
G0
G1
PD1
5
PD2
6
PD3
7
PD4
9
PD5
10
PD6
11
PD7
12
PD8
18
SCLKSL0
19
SCLKSL1
22
SDA
23
SCL
24
RQLVL0
RQLVL0
25
RQLVL1
RQLVL1
26
/SYSCON_A
/SYSCON_A
27
/RRS
/RRS
14
PACK
15
PSTRB
16
/PBSY
17
34
/PEN
35
PDIR
38
WDOG
Vcc
SCLKOUTA
SCLKOUTB
CLK8M
Vcc
R27
4K7
R26
4K7
Vcc
R25
4K7
37
/TIMINT
39
/PARINT
46
/PITACK
14
SRXDA
13
SCLKA
16
STXDA
15
SCLKOUTA
12
11
20
SRTSA
21
SCTSA
19
SDTRA
22
SDCDA
31
SRXDB
32
SCLKB
29
STXDB
30
SCLKOUTB
33
34
26
SRTSB
25
SCTSB
27
SDTRB
24
SDCDB
17
/RTCINT
16
10
T1OUT
26
CLK8M
15
GND
9
GND
12
XL1
32.768KHz
13
C4
47pF
C5
10pF
RXCLKA
R90
R91
10K
10K
Vcc
Vcc
IC51
6
SCL
5
SDA
24CXX
VCC
1
A0
SCL
2
A1
SDA
3
A2
7
WP
GND
RXCLKB
18
17
16
15
14
13
12
11
/PACKNOW
/PSTROBE
PBUSY
V+
V-
V+
V-
PDATA1
PDATA2
PDATA3
PDATA4
PDATA5
PDATA6
PDATA7
PDATA8
14
11
4
10
5
3
14
11
4
10
5
3
14
11
4
10
5
3
7
9
PDATA[1..8]
Vcc
R106
470R
/PACKNOW
/PSTROBE
Vcc
R107
470R
PBUSY
+12V
TXDA
TXDA
RTSA
RTSA
RXDA
RXDA
CTSA
CTSA
C8
4u7
+
1 2
+12V
DTRA
DTRA
DTRB
DTRB
DCDA
DCDA
DCDB
DCDB
C6
4u7
+
1 2
+12V
TXDB
TXDB
RTSB
RTSB
RXDB
RXDB
CTSB
CTSB
C10
4u7
+
1 2
SCLKA
SCLKB
Title
BVME4000/6000
Issue Dwg No.
7 BVM00228
Sheet 7 o f 8
Drawn By
S J Bush
PDATA[1..8]
/PSTROBE
PDATA1
PDATA2
PDATA3
PDATA4
PDATA5
PDATA6
PDATA7
PDATA8
/PACKNOW
PBUSY
R102
10K
GND
RXDA
TXDA
CTSA
RTSA
DTRA
GND
GND
RXDB
TXDB
CTSB
RTSB
DTRB
GND
+12V
+12VR104
10K
R105
10K
+12V
R103
10K
Date
1 2 3 4 5 6 78
VRAM
/RAMCS
/VRSTOUT
+5VIPA
+5VIPB
-12VIPA
-12VIPB
10 December 1998
Approved
8
D
C
B
A
Size
A2
7654321
D10
LK21
VBATT
D
SCSCLK
Vcc
4K7
R47
10
IC39B
XM2
CLK
XM8-40M
C
B
C90
100nF
VRAM
C74
100nF
C45
100nF
C13
100nF
VRAM
C29
100nF
A
12
C61
+
10uF
1 2 3 4 5 6 78
12
D
Q
PR
11
5
SCSCLK
CLK
Q
CL
74F74
13
Vcc
4K7
R48
VCC
R58
47R
XM1
CLK
12.5 MHz or 16.67MHz
R95
1M
Vcc
R57
4K7
R46
270K
C72
C73
0.1u
10u
C91
100nF
C75
100nF
C46
100nF
C14
100nF
C30
100nF
330R
R56
C71
0.1u
R59
47R
GND
C92
C93
100nF
100nF
C76
C77
100nF
100nF
C47
C48
100nF
100nF
C15
C16
100nF
100nF
C31
C32
100nF
100nF
12
12
C63
C64
+
+
10uF
10uF
SCSCLK
9
ETHCLK/ETHCLK
ETHCLK
8
/ETHCLK
/TS
8
C101
10p
GND
Vcc
/VRSTOUT
4K7
R45
C94
100nF
C78
100nF
C49
100nF
C17
100nF
C33
100nF
12
C65
+
10uF
IC47
8
3
13
4
5
6
7
MC88916
C95
100nF
C79
100nF
C50
100nF
C18
100nF
C34
100nF
12
C66
+
10uF
SYNC
MR
PLL_EN
RST_IN
VCC (an)
RC1
GND(an)
C96
100nF
C80
100nF
C51
100nF
C19
100nF
C35
100nF
19
2X_Q
10
Q0
12
Q1
16
Q2
1
Q3
14
RST_OUT
18
Q/2
C97
100nF
C81
100nF
C52
100nF
C20
100nF
C36
100nF
VCC
GND
VCC
R71
10K
R72
100K
VCC
R73
10K
GND
R74
100K
GND
CLK_X_2
CPUCLK
CPUCLK1
CPUCLK2
/CPUCLK3
/CLKEN
C98
100nF
C82
C83
100nF
C53
100nF
C21
100nF
C37
100nF
C84
100nF
100nF
C54
C55
100nF
100nF
C22
C23
100nF
100nF
C38
C39
100nF
100nF
GND
/TA
VCC
PVCC PVCC
R75
R77
100R
100R
R76
R78
100R
100R
GND
C85
C86
100nF
100nF
C56
C57
100nF
100nF
C24
C25
100nF
100nF
C40
C41
100nF
100nF
VBATT
12
BT1
CR2430
R79
100R
R80
100R
VCC
VCC
R85
10K
R86
100K
VCC
R87
10K
GND
R88
100K
GND
R81
R19
R84
100R
100R
100R
R82
R83
R89
100R
100R
100R
C87
100nF
C58
100nF
C26
100nF
C42
100nF
+5VSB
D8
1N4148
PVCC
GND
VCC
C88
C89
100nF
100nF
GND
VCC
C59
C60
100nF
100nF
GND
VCC
C27
C28
100nF
100nF
GND
VCC
C43
C44
100nF
100nF
GND
12
LINK2
1N4148
D6
+5VSB
1N4148
D7
12
1N4148
C70
+
0.1F
GND
D4
/WDO
1N4148
LK2
1 2
SW2
1 2
GND
IC46
LM2596-3.3
VCC
1
V_IN
ON5GND
12
C62
+
470u
GND
+12V
GND
VCC
123
L100
HF70
L101
HF70
IC13
1
11
WDOG
9
7
13
MAX791
4
V_FB
2
V_OUT
GND
3
H
GND
LK19
LK1X3
GND
12
+
C200
4u7 16V
GND
12
+
C201
4u7 16V
GND
5
VBAT
BATON
2
VRAM
VOUT
8
WDI
SWT
10
MR
LWLN
WDO
PFI
WDPO
PFO
CEIN
CEOUT
RESET
L1
22u
D11
30VF10F
GND
F5
1A
F6
1A
-12V
BVM Ltd.
Hobb Lane.
Hedge End
Southampton
SO30 0GH
(01489) 780144
VCC
14
16
6
12
15
-12V
GND
/WDO
/RAMCS
12
+12VIPA
+12VIPB
+
VCC
/L_PFAIL
GND
PVCC
123
L2
10u
C67
470u
Title
Issue Dwg No.
Sheet 8 o f 8
Drawn By
/VRSTOUT
R60
10K
LK18
LK1X3
L104
FERRITE
L102
HF70
L103
HF70
BVME4000/6000
7 BVM00228
S J Bush
R24
10KC3100nF
GND GND
VCC
D2
D1F20
D5
D1F20
D9
D1F20
GND
+
GND
+
GND
12
C500
+
10uF
12
C99
+
330u
GND
F10
2A
F7
12
2A
+
C204
10u 16V
F8
1A
C202
4u7 16V
1 2
F9
1A
C203
4u7 16V
1 2
Date
Loading...