Burr Brown Corporation DAC7621EB-1K, DAC7621EB, DAC7621E-1K, DAC7621E Datasheet

®

12-Bit, Parallel Input

DIGITAL-TO-ANALOG CONVERTER

DESCRIPTION

The DAC7621 is a 12-bit digital-to-analog converter
(DAC) with guaranteed 12-bit monotonicity perfor­mance over the industrial temperature range. It re­quires a single +5V supply and contains an input
register, latch, 2.435V reference, DAC, and high speed
rail-to-rail output amplifier. For a full-scale step, the
output will settle to 1 LSB within 7µs. The device
consumes 2.5mW (0.5mA at 5V).

The parallel interface is compatible with a wide variety
of microcontrollers. The DAC7621 accepts a 12-bit
parallel word, has a double-buffered input logic struc­ture and provides data readback. In addition, two
control pins provide a chip select (CS) function and
asynchronous clear (CLR) input. The CLR input can
be used to ensure that the DAC7621 output is 0V on
power-up or as required by the application.

The DAC7621 is available in a 20-lead SSOP package
and is fully specified over the industrial temperature
range of –40°C to +85°C.

FEATURES

● LOW POWER: 2.5mW

● FAST SETTLING: 7µs to 1 LSB

● 1mV LSB WITH 4.095V FULL-SCALE

RANGE

● COMPLETE WITH REFERENCE

● 12-BIT LINEARITY AND MONOTONICITY

OVER INDUSTRIAL TEMP RANGE

● ASYNCHRONOUS RESET TO 0V

APPLICATIONS

● PROCESS CONTROL

● DATA ACQUISITION SYSTEMS

● CLOSED-LOOP SERVO-CONTROL

● PC PERIPHERALS

● PORTABLE INSTRUMENTATION

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone]

Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

®

DAC7621

12-Bit DAC

Ref

DAC Register

Input Register

I/O Buffer

12

12

12

CLR

LOADDAC

CS

R/W

V

DD

V

OUT

DGND

DAC7621

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11

DAC7621

© 1998 Burr-Brown Corporation PDS-1502B Printed in U.S.A. March, 1999

For most current data sheet and other product

information, visit www.burr-brown.com

®

2

DAC7621

SPECIFICATIONS

ELECTRICAL

At TA = –40°C to +85°C, and VDD = +5V, unless otherwise noted.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

DAC7621E DAC7621EB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 12 ✻ Bits

ACCURACY

Relative Accuracy

(1)

–2 ±1/2 +2 –1 ±1/4 +1 LSB
Differential Nonlinearity Guaranteed Monotonic –1 ±1/2 +1 –1 ±1/4 +1 LSB
Zero-Scale Error Code 000

H

–1 +1 +3 ✻✻✻ LSB
Full Scale Voltage Code FFF

H

4.079 4.095 4.111 4.087 4.095 4.103 V

ANALOG OUTPUT

Output Current Code 800

H

±5 ±7 ✻✻ mA
Load Regulation R

LOAD

≥ 402Ω, Code 800

H

13 ✻✻ LSB
Capacitive Load No Oscillation 500 ✻ pF
Short-Circuit Current ±20 ✻ mA
Short-Circuit Duration GND or V

DD

Indefinite ✻

DIGITAL INPUT

Data Format Parallel ✻
Data Coding Straight Binary ✻
Logic Family CMOS ✻
Logic Levels

V

IH

0.7 • V

DD

✻ V

V

IL

0.3 • V

DD

✻ V

I

IH

±10 ✻ µA

I

IL

±10 ✻ µA

DYNAMIC PERFORMANCE

Settling Time

(2)

(tS) To ±1 LSB of Final Value 7 ✻ µs
DAC Glitch 5 ✻ nV-s
Digital Feedthrough 2 ✻ nV-s

POWER SUPPLY

V

DD

+4.75 +5.0 +5.25 ✻✻✻ V

I

DD

VIH = 5V, VIL = 0V, No Load, at Code 000

H

0.5 1 ✻✻ mA

Power Dissipation V

IH

= 5V, VIL = 0V, No Load 2.5 5 ✻✻ mW

Power Supply Sensitivity ∆V

DD

= ±5% 0.001 0.004 ✻✻%/%

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

✻ Same specification as for DAC7621E.

NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions where
the final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated.

®

3 DAC7621

PIN CONFIGURATION

Top View SSOP

VDD to GND .......................................................................... –0.3V to 6V

Digital Inputs to GND .............................................. –0.3V to V

DD

+ 0.3V

V

OUT

to GND ........................................................... –0.3V to VDD + 0.3V

Power Dissipation ........................................................................ 325mW

Thermal Resistance,

θ

JA

........................................................... 150°C/W

Maximum Junction Temperature.................................................. +150°C

Operating Temperature Range ...................................... –40°C to +85°C

Storage Temperature Range ....................................... –65 °C to +150°C

Lead Temperature (soldering, 10s) .............................................. +300°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS

(1)

PIN DESCRIPTIONS

PIN LABEL DESCRIPTION

1 CLR Reset. Resets the DAC register to zero. Active

LOW. Asynchronous input.

2V

DD

Postive Power Supply

3V

OUT

DAC Output Voltage
4 AGND Analog Ground
5 DGND Digital Ground
6 DB11 Data Bit 11, MSB
7 DB10 Data Bit 10
8 DB9 Data Bit 9
9 DB8 Data Bit 8
10 DB7 Data Bit 7
11 DB6 Data Bit 6
12 DB5 Data Bit 5
13 DB4 Data Bit 4
14 DB3 Data Bit 3
15 DB2 Data Bit 2
16 DB1 Data Bit 1
17 DB0 Data Bit 0, LSB
18 R/W Read and Write Control
19 CS Chip Select. Active LOW.
20 LOADDAC Loads the internal DAC register. The DAC register

is a transparent latch and is transparent when

LOADDAC is LOW (regardless of the state of CS or

CLK).

ELECTROSTA TIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degrada­tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.

PACKAGE/ORDERING INFORMATION

MINIMUM

RELATIVE DIFFERENTIAL SPECIFICATION PACKAGE

ACCURACY NONLINEARITY TEMPERATURE DRAWING ORDERING TRANSPORT

PRODUCT (LSB) (LSB) RANGE PACKAGE NUMBER

(1)

NUMBER

(2)

MEDIA

DAC7621E ±2 ±1 –40°C to +85°C 20-Lead SSOP 334 DAC7621E Rails

"" " " ""DAC7621E/1K Tape and Reel

DAC7621EB ±1 ±1 –40°C to +85°C 20-Lead SSOP 334 DAC7621EB Rails

"" " " ""DAC7621EB/1K Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7621E/1K” will get a single
1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

1
2
3
4
5
6
7
8
9

10

20
19
18
17
16
15
14
13
12
11

CLR

V

DD

V

OUT

AGND
DGND

DB11 (MSB)

DB10

DB9
DB8
DB7

LOADDAC
CS
R/W
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6

DAC7621E

®

4

DAC7621

TIMING DIAGRAMS

LOGIC TRUTH TABLE

TIMING SPECIFICATIONS

TA = –40°C to +85°C

SYMBOL

DESCRIPTION MIN TYP MAX UNITS

t

RCS

CS LOW for Read 200 ns

t

RDS

R/W HIGH to CS LOW 10 ns

t

RDH

R/W HIGH after CS HIGH 0 ns

t

DZ

CS HIGH to Data Bus 100 ns

in High Impedance

t

CSD

CS LOW to Data Bus Valid 100 160 ns

t

WCS

CS LOW for Write 50

t

WS

R/W LOW to CS LOW 0 ns

t

WH

R/W LOW after CS HIGH 5 ns

t

DS

Data Valid to CS LOW 0 ns

t

DH

Data Valid after CS HIGH 5 ns

t

LWD

LOADDAC LOW 50 ns

INPUT DAC

R/W CS LOADDAC REGISTER REGISTER MODE

L L L Write Write Write

L L H Write Hold Write Input
H L H Read Hold Read Input
X H L Hold Update Update
X H H Hold Hold Hold

X = Don’t Care.

t

RCS

CS

t

RDS

t

RDH

t

CSD

t

DZ

R/W

Data Out

Data Valid

t

WCS

CS

t

WS

t

WH

R/W

t

LWD

LOADDAC

t

DS

t

DH

Data In

Data Output Timing

Digital Input Timing