
DAC716
16-Bit DIGITAL-TO-ANALOG CONVERTER
with Serial Data Interface
DESCRIPTION
The DAC716 is a complete monolithic D/A converter
including a +10V temperature compensated voltage
reference, current-to-voltage amplifier, a high-speed
synchronous serial interface, a serial output which
allows cascading multiple converters, and an asynchronous clear function which immediately sets the
output voltage to zero.
The output voltage range is 0 to +10V while operating
from ±12V to ±15V supplies, and the gain and bipolar
offset adjustments are designed so that they can be set
via external potentiometers or external D/A converters. The output amplifier is protected against shortcircuiting to ground.
The 16-pin DAC716 is available in a plastic 0.3" DIP
and a wide-body plastic SOIC package. The DAC716P,
U, PB, and UB are specified over the –40°C to +85°C
range while the DAC716UK and PK are specified
over the 0°C to +70°C range.
®
© 1996 Burr-Brown Corporation PDS-1324B Printed in U.S.A. March, 1998
FEATURES:
● SERIAL DIGITAL INTERFACE
● VOLTAGE OUTPUT: 0 to +10V
● ±2 LSB INTEGRAL LINEARITY
● PRECISION INTERNAL REFERENCE
● LOW NOISE: 120nV/ √Hz Including Reference
● 16-LEAD PLASTIC SKINNY DIP AND PLASTIC
SOIC PACKAGES
V
OUT
V
REF OUT
+10V
Reference
Circuit
16-Bit D/A Converter
D/A Latch
SDO
16
Input Shift Register
16
A
1
SDI
CLK
CLR
A
0
Offset Adjust
Gain
Adjust
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Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

2
®
DAC716
SPECIFICATIONS
At TA = +25°C, +V
CC
= +15V, –VCC = –15V, unless otherwise noted.
Straight Binary
DAC716P, U DAC716PB, UB DAC716PK, UK
PARAMETER MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error ±4 ±2 ±2 LSB
T
MIN
to T
MAX
±8 ±4 ±2 LSB
Differential Linearity Error ±4 ±2 ±2 LSB
T
MIN
to T
MAX
±8 ±4 ±2 LSB
Monotonicity 14 15 15 Bits
Monotonicity Over Spec Temp Range 13 14 15 Bits
Gain Error
(3)
±0.1 ✻✻%
T
MIN
to T
MAX
±0.25 ✻✻%
Unipolar Zero Error
(3)
±0.1 ✻✻% of FSR
(2)
T
MIN
to T
MAX
±0.2 ✻✻% of FSR
Power Supply Sensitivity of Gain ±0.003 ✻✻%FSR/%V
CC
±30 ✻✻ppm FSR/%V
CC
DYNAMIC PERFORMANCE
Settling Time
(to ±0.003%FSR, 5kW || 500pF Load)
(4)
20V Output Step 6 10 ✻✻ ✻✻ µs
1LSB Output Step
(5)
4 ✻✻µs
Output Slew Rate 10 ✻✻V/µs
Total Harmonic Distortion
0dB, 1001Hz, f
S
= 100kHz 0.005 ✻✻%
–20dB, 1001Hz, f
S
= 100kHz 0.03 ✻✻%
–60dB, 1001Hz, f
S
= 100kHz 3.0 ✻✻%
SINAD: 1001Hz, f
S
= 100kHz 87 ✻✻dB
Digital Feedthrough
(5)
2 ✻✻nV–s
Digital-to-Analog Glitch Impulse
(5)
15 ✻✻nV–s
Output Noise Voltage (includes reference) 120 ✻✻nV/√Hz
ANALOG OUTPUT
Output Voltage Range
+V
CC
, –VCC = ±11.4V +10 ✻✻V
Output Current ±5 ✻✻mA
Output Impedance 0.1 ✻✻W
Short Circuit to ACOM Duration Indefinite ✻✻
REFERENCE VOLTAGE
Voltage +9.975 +10.000 +10.025 ✻✻✻ ✻✻✻ V
T
MIN
to T
MAX
+9.960 +10.040 ✻✻✻✻V
Output Resistance 1 ✻✻W
Source Current 2 ✻✻mA
Short Circuit to ACOM Duration Indefinite ✻✻
INTERFACE
RESOLUTION 16 ✻✻Bits
DIGITAL INPUTS
Serial Data Input Code
Logic Levels
(1)
V
IH
+2.0 (VCC –1.4) ✻✻✻✻V
V
IL
0 +0.8 ✻✻✻✻V
I
IH
(VI = +2.7V) ±10 ✻✻µA
I
IL
(VI = +0.4V) ± 10 ✻✻µA
DIGITAL OUTPUT
Serial Data
V
OL (ISINK
= 1.6mA) 0 +0.4 ✻✻✻✻V
V
OH (ISOURCE
= 500µA),T
MIN
to T
MAX
+2.4 +5 ✻✻✻✻V
POWER SUPPLY REQUIREMENTS
Voltage
+V
CC
+11.4 +15 +16.5 ✻✻✻ ✻✻✻ V
–V
CC
–11.4 –15 –16.5 ✻✻✻ ✻✻✻ V
Current (No Load, ±15V Supplies)
(6)
+V
CC
13 16 ✻✻ ✻✻ mA
–V
CC
22 26 ✻✻ ✻✻ mA
Power Dissipation
(7)
625 ✻✻mW
TEMPERATURE RANGES
Specification
All Grades –40 +85 ✻✻0 +70 °C
Storage –60 +150 ✻✻✻✻°C
Thermal Coefficient,
θ
JA
75 ✻✻°C/W
✻ Specifications are the same as the grade to the left.
NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for 0 to +10V output, FSR = 10V. (3) Errors externally
adjustable to zero. (4) Maximum represents the 3σ limit. Not 100% tested for this parameter. (5) For the worst-case Straight Binary code changes: 7FFF to 8000 and 8000 to 7FFF. (6) During power supply
turn on, the transient supply current may approach 3x the maximum quiescent specification. (7) Typical (i.e. rated) supply voltages times maximum currents.

3
®
DAC716
DIFFERENTIAL
LINEARITY ERROR TEMPERATURE
PRODUCT PACKAGE T
MIN
to T
MAX
RANGE
DAC716P Plastic DIP ±8 LSB –40°C to +85°C
DAC716U Plastic SOIC ±8 LSB –40°C to +85°C
DAC716PB Plastic DIP ±4 LSB –40°C to +85°C
DAC716UB Plastic SOIC ±4 LSB –40°C to +85°C
DAC716PK Plastic DIP ±2 LSB 0°C to +70°C
DAC716UK Plastic SOIC ±2 LSB 0°C to +70°C
PIN CONFIGURATION
Top View
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
PIN DESCRIPTIONS
PIN LABEL DESCRIPTION
1 CLK Serial Data Clock
2A
0
Enable for Input Register (Active Low)
3A
1
Enable for D/A Latch (Active Low)
4 SDI Serial Data Input
5 SDO Serial Data Output
6 DCOM Digital Supply Ground
7+V
CC
Positive Power Supply
8 ACOM Analog Supply Ground
9V
OUT
D/A Output
10 NC No Connection
11 NC No Connection
12 V
REF OUT
Voltage Reference Output
13 Offset Adjust Offset Adjust
14 Gain Adjust Gain Adjust
15 –V
CC
Negative Power Supply
16 CLR Clear
ORDERING INFORMATION
SOIC/DIP
+V
CC
to Common .................................................................... 0V to +17V
–V
CC
to Common .................................................................... 0V to –17V
+V
CC
to –VCC....................................................................................... 34V
ACOM to DCOM ...............................................................................±0.5V
Digital Inputs to Common............................................. –1V to (V
CC
–0.7V)
External Voltage Applied to BPO and Range Resistors..................... ±V
CC
V
REF OUT
......................................................... Indefinite Short to Common
V
OUT
............................................................... Indefinite Short to Common
SDO ............................................................... Indefinite Short to Common
Power Dissipation ..........................................................................750mW
Storage Temperature ...................................................... –60°C to +150°C
Lead Temperature (soldering, 10s)................................................ +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
CLK
A
0
A
1
SDI
SDO
DCOM
+V
CC
ACOM
DAC716
CLR
–V
CC
Gain Adjust
Offset Adjust
V
REF OUT
NC
NC
V
OUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
PACKAGE DRAWING
PRODUCT PACKAGE NUMBER
(1)
DAC716P Plastic DIP 180
DAC716U Plastic SOIC 211
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet,
or Appendix C of Burr-Brown IC Data Book.
PACKAGE INFORMATION

4
®
DAC716
TIMING SPECIFICATIONS
TA = –40°C to +85°C, +VCC = +15V, –VCC = –15V.
SYMBOL PARAMETER MIN MAX UNITS
t
CLK
Data Clock Period 100 ns
t
CL
Clock LOW 50 ns
t
CH
Clock HIGH 50 ns
t
A0S
Setup Time for A
0
50 ns
t
A1S
Setup Time for A
1
50 ns
t
AOH
Hold Time for A
0
10 ns
t
A1H
Hold Time for A
1
10 ns
t
DS
Setup Time for DATA 50 ns
t
DH
Hold Time for DATA 10 ns
t
DSOP
Output Propagation Delay 140 ns
t
CP
Clear Pulsewidth 200 ns
A
0
A
1
CLK CLR DESCRIPTION
011 → 0 → 1 1 Shift Serial Data into SDI
101 → 0 → 1 1 Load D/A Latch
111 → 0 → 1 1 No Change
001 → 0 → 1 1 Two Wire Operation
(1)
X X 1 1 No Change
X X X 0 Reset D/A Latch
NOTES: X = Don’t Care. (1) All digital input changes will appear at the
D/A output.
TRUTH TABLE
TIMING DIAGRAMS
Serial Data In
Serial Data Out
CLK
A
0
SDO
Serial Data Out
t
A0H
t
A0S
D
0
D
14
D
15
t
CLK
t
CH
t
CL
t
DS
t
DSOP
t
DSOP
CLK
A
0
SDI
Serial Data Input
MSB First
Latch Data
In D/A Latch
A
1
t
A0H
D
0
D
14
D
15
t
A1S
t
A1H
t
DH
t
DS
t
A0S
t
CLK
t
CP
t
CH
t
CL
CLR