Burr Brown Corporation AFE1205E-1K, AFE1205 Datasheet

®

©

1998 Burr-Brown Corporation PDS-1461A Printed in U.S.A. September, 1998

2Mbps, Single Pair HDSL ANALOG FRONT END

FEATURES

● E1/T1 SINGLE PAIR 2B1Q OPERATION

● COMPLETE ANALOG INTERFACE

● 385mW POWER DISSIPATION

● PROGRAMMABLE POWER

AFE1205

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone] • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: [phone] (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

DESCRIPTION

Burr-Brown’s Analog Front End greatly reduces the size and
cost of a single pair HDSL (High bit rate Digital Subscriber
Line) system by providing all of the active analog circuitry
needed to connect an HDSL digital signal processor to an
external compromise hybrid and an HDSL line transformer.
The transmit and receive filter responses automatically change
with clock frequency, allowing the AFE1205 to operate over a
wide range of data rates. The power dissipation of the device
can be reduced under digital control for operation at lower
speeds. The AFE1205 will operate at bit rates from 160kbps to

2.3Mbps. It meets ETSI PSD specifications for single pair E1,
as well as ETSI and ANSI PSD specifications for two pair E1
and T1.

Functionally, this unit consists of a transmit and a receive
section. The transmit section generates, filters, and buffers
outgoing 2B1Q data. The receive section filters and digitizes
the symbol data received on the telephone line. This IC operates

Pulse

Former

PLL

OUT

PLL

IN

txDAT
txCLK

rxSYNC

rxLOOP

rxGAIN

rxD13 - rxD0

Line

Driver

Voltage

Reference

Delta-Sigma

Modulator

Transmit

Control

Receive

Control

Decimation

Filter

14

2

txLINE

N

txLINE

P

REF

P

V

CM

REF

N

rxLINE

P

rxLINE

N

rxHYB

P

rxHYB

N

Patents Pending

D/A

Converter

● 48-LEAD SSOP PACKAGE

● SCALEABLE DATA RATE

● OPERATION FROM 2.3Mbps TO 160kbps

● +5V ONLY (5V OR 3.3V DIGITAL)

● –40°C TO +85°C OPERATION

on a single 5V supply. The digital circuitry in the unit can be
connected to a supply from 3.3V to 5V. The chip uses only
385mW for full-speed operation. It is housed in a small 48-lead
SSOP package.

The receive channel is designed around a fourth-order delta­sigma analog-to-digital converter. It includes a difference am­plifier designed to be used with an external compromise hybrid
for first-order analog echo cancellation. A programmable gain
amplifier with gains 0dB to +9dB is also included. The delta­sigma modulator, operating at a 24X oversampling ratio, pro­duces a 14-bit output at symbol rates up to 1168kHz (for

2.3Mbps operation).
The transmit channel consists of a digital-to-analog converter and

switched-capacitor pulse forming network followed by a differ­ential line driver. The pulse forming network receives symbol
data and generates a standard 2B1Q output waveform. The
differential line driver uses a composite output stage combining
class B operation (for high efficiency driving large signals) with
class AB operation (to minimize crossover distortion).

AFE1205

2

®

AFE1205

SPECIFICATIONS

Typical at 25°C, AVDD = +5V, DVDD = +3.3V, ftx = 1168kHz (E1 single pair rate) and Normal Power mode, unless otherwise specified.

AFE1205E
PARAMETER COMMENTS MIN TYP MAX UNITS
RECEIVE CHANNEL

Number of Inputs Differential 2
Input Voltage Range Balanced Differential

(1)

±3.0 V
Common-Mode Voltage 1.5V CMV Recommended +1.5 V
Input Impedance All Inputs See Typical Performance Curves
Input Capacitance 10 pF
Input Gain Matching Line Input vs Hybrid Input ±2%
Resolution 14 Bits
Programmable Gain Four Gains: 0dB, 3.25dB, 6dB, and 9dB
Settling Time Gain, rxSYNC, or Power Mode Change

(8)

6 Symbol

Periods

Gain + Offset Error Tested at Each Gain Range 5 %FSR

(2)

Output Data Coding Binary Two’s Complement
Data Rate Normal Power 384 2320 kbps

Medium Power 192 1168 kbps

Low Power 160 320 kbps

Output Word Rate Normal Power, rxSYNC

(3)

196 1168 kHz

TRANSMIT CHANNEL

Transmit Clock Rate, f

TX

Symbol Rate, Normal Power 196 1168 kHz

Symbol Rate, Medium Power 96 584 kHz

Symbol Rate, Low Power 80 160 kHz

Transmit –3dB Point 2320kbps 485 kHz

1168kbps 292 kHz

784kbps 196 kHz

Transmit Power

(5)

13 13.5 14 dBm
Pulse Output See Typical Performance Curves
Common-Mode Voltage, V

CM

AVDD/2 V

Output Resistance

(5)

DC to 1MHz 1 Ω

TRANSCEIVER PERFORMANCE

Uncancelled Echo

(6)

rxGAIN = 0dB, Loopback Enabled –67 dB

rxGAIN = 0dB, Loopback Disabled –67 dB

rxGAIN = 3.25dB, Loopback Disabled –69 dB

rxGAIN = 6dB, Loopback Disabled –71 dB
rxGAIN = 9dB, Loopback Disabled –73 dB

DIGITAL INTERFACE

(5)

Logic Levels

V

IH

|IIH| < 10µADV

DD

– 1 DVDD + 0.3 V

V

IL

|IIL| < 10µA –0.3 +0.8 V

V

OH

IOH = –20µADV

DD

– 0.5 V

V

OL

IOL = 20µA +0.4 V

POWER

Analog Power Supply Voltage Specification 5 V

Operating Range 4.75 5.25 V

Digital Power Supply Voltage Specification 3.3 V

Operating Range 3.15 5.25 V

Power Dissipation

( 4, 7)

Normal Power, 1:2 Line Transformer 385 mW

Medium Power, 1:2 Line Transformer 300 mW

Low Power, 1:2 Line Transformer 240 mW

Power Dissipation

(7)

Normal Power, DVDD = 5V, 1:2 Line Transformer 415 mW

PSRR 55 dB

TEMPERATURE RANGE

Operating

(5)

–40 +85 °C

NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore the actual voltage swing about the common
mode voltage on each pin is ±1.5V to achieve a differential input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the
symbol rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (27dBm output from
txLINEP and txLINEN). (5) Guaranteed by design and characterization. (6) Uncancelled Echo is a measure of the total analog errors in the transmitter and receiver
sections including the effect of non-linearity and noise. See the Discussion of Specifications section of this data sheet for more information. (7) Power dissipation
includes only the power dissipated within the component and does not include power dissipated in the external loads. The AFE1205 is tested with a 1:2 line
transformer. (8) This is the settling time required for any gain change, change of rxSYNC or any change of power mode.

3

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AFE1205

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

PIN DESCRIPTIONS

PIN # TYPE NAME DESCRIPTION

1 Ground AGND Analog Ground for PLL
2 Power AV

DD

Analog Supply (+5V) for PLL
3 Input txCLK Symbol Clock
4 Ground DGND Digital Ground
5 Input txDAT XMTDA from MtH1210B
6 Output rxD0 ADC Output Bit 0
7 Output rxD1 ADC Output Bit 1
8 Output rxD2 ADC Output Bit 2
9 Output rxD3 ADC Output Bit 3

10 Output rxD4 ADC Output Bit 4
11 Output rxD5 ADC Output Bit 5
12 Ground DGND Digital Ground
13 Power DV

DD

Digital Supply (+3.3V to +5V)

14 Output rxD6 ADC Output Bit 6
15 Output rxD7 ADC Output Bit 7
16 Output rxD8 ADC Output Bit 8
17 Output rxD9 ADC Output Bit 9
18 Output rxD10 ADC Output Bit 10
19 Output rxD11 ADC Output Bit 11
20 Output rxD12 ADC Output Bit 12
21 Output rxD13 ADC Output Bit 13
22 Input PWSEL Power Control
23 Input rxSYNC ADC Sync Signal
24 Input rxGAIN0 Receive Gain Control Bit 0
25 Input rxGAIN1 Receive Gain Control Bit 1
26 Input rxLOOP Loopback Control Signal (loopback is enabled by positive signal)
27 Power AV

DD

Analog Supply (+5V)

28 Input rxHYB

N

Negative Input from Hybrid Network

29 Input rxHYB

P

Positive Input from Hybrid Network

30 Input rxLINE

N

Negative Line Input

31 Input rxLINE

P

Positive Line Input

32 Ground AGND Analog Ground
33 Ground AGND Analog Ground
34 Output REF

P

Positive Reference Output, Nominally 3.5V

35 Output V

CM

Common-Mode Voltage (buffered), Nominally 2.5V

36 Output REF

N

Negative Reference Output, Nominally 1.5V

37 Power AV

DD

Analog Supply (+5V)

38 Ground AGND Analog Ground
39 Output txLINE

N

Transmit Line Output Negative

40 Power AV

DD

Analog Supply (+5V)

41 Output txLINE

P

Transmit Line Output Positive

42 Ground AGND Analog Ground
43 NC NC Connection to Ground Recommended
44 NC NC Connection to Ground Recommended
45 NC NC Connection to Ground Recommended
46 NC NC Connection to Ground Recommended
47 Output PLL

OUT

PLL Filter Output

48 Input PLL

IN

PLL Filter Input