Burr Brown Corporation ADS930E-1K, ADS930 Datasheet

©

1997 Burr-Brown Corporation PDS-1348B Printed in U.S.A. March, 1997

Pipeline

A/D

Internal

Reference

Timing

Circuitry

Error

Correction

3-State

Outputs

T/H

8-Bit

Digital

Data

CLK

ADS930

LV

DD

OEPwrdn1V

REF

LnByCMLpBy

IN

2V

1V

IN

(Opt.)

ADS930

®

FEATURES

● +3V TO +5V SUPPLY OPERATION

● INTERNAL REFERENCE

● SINGLE-ENDED INPUT RANGE: 1V to 2V

● LOW POWER: 66mW at +3V

● HIGH SNR: 46dB

● LOW DNL: 0.4LSB

● 28-LEAD SSOP PACKAGE

DESCRIPTION

The ADS930 is a high speed pipelined analog-to­digital converter specified to operate from nominal
+3V or +5V power supplies with tolerances of up to
10%. This complete converter includes a high band­width track/hold, a 8-bit quantizer and an internal
reference.

The ADS930 employs digital error correction tech­niques to provide excellent differential linearity for
demanding imaging applications. Its low distortion
and high SNR give the extra margin needed for
telecommunications, video and test instrumentation
applications.

This high performance A/D converter is specified for
performance at a 30MHz sampling rate. The ADS930
is available in a 28-lead SSOP package.

8-Bit, 30MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

APPLICATIONS

● BATTERY POWERED EQUIPMENT

● CAMCORDERS

● PORTABLE TEST EQUIPMENT

● COMPUTER SCANNERS

● COMMUNICATIONS

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone] • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: [phone] (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

ADS930E

TM

2

®

ADS930

SPECIFICATIONS

At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

ADS930E

PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS
RESOLUTION 8 Bits

Specified Temperature Range Ambient Air –40 +85 °C

ANALOG INPUT

Differential Full Scale Input Range

0.5Vp-p 1.25 1.75 V
Single-Ended Full Scale Input Range 1Vp-p 1.0 2.0 V
Common-mode Voltage 1.5 V
Analog Input Bias Current 1 µA
Input Impedance 1.25 || 5 MΩ || pF

DIGITAL INPUTS Full
Logic Family TTL/HCT Compatible CMOS
High Input Voltage, V

IH

2.0 V

DD

V

Low Input Voltage, V

IL

0.8 V

High Input Current, I

IH

±10 µA

Low Input Current, I

IL

±10 µA

Input Capacitance 5pF

CONVERSION CHARACTERISTICS

Start Conversion

Rising Edge of Convert Clock
Sample Rate Full 10k 20M Samples/s
Data Latency 5 Clk Cyc

DYNAMIC CHARACTERISTICS

Differential Linearity Error

f = 500kHz Largest Code Error Full ±0.4 ±1 LSB
f = 12MHz Largest Code Error Full ±0.4 ±1 LSB

No Missing Codes Full Guaranteed
Integral Nonlinearity Error, f = 500kHz Full ±1.0 ±2.5 LSB

Spurious Free Dynamic Range

(1)

f = 500kHz (–1dBFS input) Full 46 51 dBFS

(2)

f = 12MHz (–1dB input) Full 46 50 dBFS

Two-Tone Intermodulation Distortion

(3)

f = 3.4MHz and 3.5MHz

(–7dBFS each tone)

54 dBc

Signal-to-Noise Ratio (SNR)

f = 500kHz (–1dBFS input) Full 44 46 dB
f = 12MHz (–1dBFS input) Full 44 46 dB

Signal-to-(Noise + Distortion) (SINAD)

f = 500kHz (–1dBFS input) Full 43 45 dB
f = 3.58MHz (–1dBFS input) Full 42 45 dB

f = 12MHz (–1dBFS input) Full 42 45 dB
Differential Gain Error NTSC, PAL 2.3 %
Differential Phase Error NTSC, PAL 1 degrees
Output Noise Input Grounded 0.2 LSBs rms
Aperture Delay Time 2ns
Aperture Jitter 7 ps rms
Analog Input Bandwidth

Small Signal –20dBFS Input 350 MHz

Full Power 0dBFS Input 100 MHz
Overvoltage Recovery Time

(4)

2ns

DIGITAL OUTPUTS C

L

= 15pF
Logic Family TTL/HCT
Logic Coding Straight Offset Binary
High Output Voltage, V

OH

+2.4 LV

DD

V

Low Output Voltage, V

OL

0.4 V
3-State Enable Time OE = L 20 40 ns
3-State Disable Time OE = H 2 10 ns

Internal Pull-Down 50 kΩ
Power-Down Enable Time PwrDn = L 133 ns
Power-Down Disable Time PwrDn = H 18 ns

Internal Pull-Down 50 kΩ

3

®

ADS930

SPECIFICATIONS (CONT)

At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.

ADS930E

PARAMETER CONDITIONS TEMP MIN TYP MAX UNITS

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

+VS....................................................................................................... +6V

Analog Input...............................................................................+V

S

+0.3V

Logic Input .................................................................................+V

S

+0.3V

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature..................................................................... +150°C

ABSOLUTE MAXIMUM RATINGS

PACKAGE
DRAWING TEMPERATURE

PRODUCT PACKAGE NUMBER

(1)

RANGE

ADS930E 28-Lead SSOP 324 –40°C to +85°C

NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.

PACKAGE/ORDERING INFORMATION

ACCURACY

Gain Error Full 5.9 10 %FS
Input Offset Referred to Ideal Midscale Full ±10 ±60 mV
Power Supply Rejection (Gain) ∆ V

S

= +10% Full 42 56 dB
Power Supply Rejection (Offset) Full 42 56 dB
Internal Positive Reference Voltage Full +1.75 V
Internal Negative Reference Voltage Full +1.25 V

POWER SUPPLY REQUIREMENTS

Supply Voltage: +V

S

Operating Full +2.7 +3.0 +5.25 V

Supply Current: +I

S

Operating, +3V Full 22 mA

Power Dissipation Operating, +3V Full 66 84 mW

Operating, +5V Full 168 mW

Power Dissipation (Power Down) Operating, +3V Full 10 mW

Operating, +5V Full 15 mW

Thermal Resistance,

θ

JA

28-Lead SSOP 50 °C/W

NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to full scale. (3) Two-tone intermodulation
distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (4) No
"Rollover" of bits.

4

®

ADS930

PIN CONFIGURATION

PIN DESIGNATOR DESCRIPTION

1+V

S

Analog Supply

2LV

DD

Output Logic Driver Supply Voltage
3 NC No Connection
4 NC No Connection
5 Bit 8 (LSB) Data Bit 8 (D7)
6 Bit 7 Data Bit 7 (D6)
7 Bit 6 Data Bit 6 (D5)
8 Bit 5 Data Bit 5 (D4)
9 Bit 4 Data Bit 4 (D3)

10 Bit 3 Data Bit 3 (D2)
11 Bit 2 Data Bit 2 (D1)
12 Bit 1(MSB) Data Bit 1 (D0)
13 GND Analog Ground
14 GND Analog Ground
15 CLK Convert Clock Input
16 OE Output Enable, Active Low
17 Pwrdn Power Down Pin
18 +V

S

Analog Supply

19 GND Analog Ground
20 GND Analog Ground
21 LpBy Positive Ladder Bypass
22 NC No Connection
23 1V

REF

1V Reference Output

24 IN Complementary Input
25 LnBy Negative Ladder Bypass
26 CM Common-Mode Voltage Output
27 +IN Analog Input
28 +V

S

Analog Supply

PIN DESCRIPTIONS

TIMING DIAGRAM

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

CONV

Convert Clock Period 33 100µsns

t

L

Clock Pulse Low 15.5 16.5 ns

t

H

Clock Pulse High 15.5 16.5 ns

t

D

Aperture Delay 2 ns

t

1

Data Hold Time, CL = 0pF 3.9 ns

t

2

New Data Delay Time, CL = 15pF max 12 ns

5 Clock Cycles

Data Invalid

t

D

tLt

H

t

CONV

N–5 N–4 N–3 N–2 N–1 N N+1 N+2Data Out

Clock

Analog In

N

t

2

N+1

N+2

N+3

N+4

N+5

N+6

N+7

t

1

Top View SSOP

+V

S

LV

DD

NC
NC

LSB Bit 8

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2

MSB Bit 1

GND
GND

+V

S

+IN
CM
LnBy
IN
1V

REF

NC
LpBy
GND
GND
+V

S

Pwrdn
OE
CLK

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

ADS930