Burr Brown Corporation ADS902E-1K, ADS902 Datasheet

1

ADS902

®

Pipeline

A/D

Reference

Ladder

Timing

Circuitry

Error

Correction

Logic

3-State

Outputs

T/H

10-Bit
Digital

Data

CLK

ADS902

LV

DD

OEPwrdn

REFBCMREFT

IN

ADS902

®

FEATURES

● HIGH SNR: 57dB

● EXTERNAL REFERENCE

● LOW POWER: 140mW

● ADJUSTABLE FULL SCALE RANGE

● POWER DOWN

● 28-PIN SSOP PACKAGE

DESCRIPTION

The ADS902 is a high speed pipelined analog-to­digital converter that is specified to operate from a
single +5V supply. This converter includes a wide
bandwidth track/hold and a 10-bit quantizer. The per­formance is specified with a single-ended input range
of 2.25V to 3.25V, or 2V to 4V. The input range is set
by the external reference values.

The ADS902 employs digital error correction tech­niques to provide excellent differential linearity for
demanding imaging applications. Its low distortion
and high SNR give the extra margin needed for tele­communications, video and test instrumentation appli­cations. This high performance A/D converter is speci­fied to operate at a 30MHz sampling rate. The ADS902
is available in a 28-pin SSOP package.

10-Bit, 30MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone] • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: [phone] (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

TM

APPLICATIONS

● BATTERY POWERED EQUIPMENT

● CAMCORDERS

● PORTABLE TEST EQUIPMENT

● COMPUTER SCANNERS

● COMMUNICATIONS

ADS902E

©

1996 Burr-Brown Corporation PDS-1359B Printed in U.S.A., February, 1997

2

®

ADS902

SPECIFICATIONS

At TA = +25°C, VS = LVDD = +5V, REFB = +2.25V, REFT = +3.25V, Sampling Rate = 30MHz, unless otherwise specified.

ADS902E

PARAMETER CONDITIONS TEMP MIN TYP MAX MIN TYP MAX UNITS

Resolution 10 10 Bits
Specified Temperature Range Ambient Air –40 +85 –40 +85 °C

ANALOG INPUT

Specified Full Scale Input Range

(1)

1 2 Vp-p
Common-Mode Voltage (Midscale) +2.75 3 V
Track-Mode Input Bandwidth 350

✻

MHz

Analog Input Bias Current 1

✻

µA

Input Impedance 1.25 || 5

✻

MΩ || pF

DIGITAL INPUTS

Logic Family
High Input Voltage, V

IH

+2.0 +V

S

✻✻

V

Low Input Voltage, V

IL

+0.8

✻

V

High Input Current, I

IH

±10

✻

µA

Low Input Current, I

IL

±10

✻

µA

Input Capacitance 5

✻

pF

CONVERSION CHARACTERISTICS

Sample Rate Full 10k 30M

✻✻

Samples/s

Data Latency 5

✻

Clk Cyc

DYNAMIC CHARACTERISTICS

Differential Linearity Error (Largest Code Error)

f = 500kHz Full ±0.3 ±1.0

✻✻

LSB

f = 12.5MHz Full ±0.3 ±1.0

✻✻

LSB

No Missing Codes Full

Guaranteed Guaranteed

Spurious-Free Dynamic Range

f = 12.5MHz (–1dBFS

(2)

input) Full 53 50 58 dB

Integral Nonlinearity Error, f = 500kHz Full ±2.0 ±4.5

✻✻

LSB

Signal-to-Noise Ratio (SNR)

Referred to Sinewave Input Signal
f = 500kHz (–1dBFS input) Full 48 53 dB
f = 12.5MHz (–1dBFS input) Full 48 53 52 57 dB

Maximum SNR Referred to DC FS Input Signal

f = 9MHz (–1dBFS input) 62 66 dB

Signal-to-(Noise + Distortion) (SINAD)

f = 500kHz (–1dBFS input) Full 46 50 dB
f = 3.58MHz (–1dBFS input) Full 45 50 dB
f = 12.5MHz (–1dBFS) input) Full 45 49 47 53 dB

Effective Number of Bits

(3)

, f =12.5MHz 7.8 Bits

Output Noise Input Grounded 0.2

✻

LSB rms

Aperture Delay Time 4

✻

ns

Aperture Jitter 7

✻

ps rms

DIGITAL OUTPUTS C

L

= 15pF
Logic Family
Logic Coding
High Output Voltage, V

OH

+2.4 LV

DD

✻✻

V

Low Output Voltage, V

OL

+0.4

✻

V

3-State Enable Time OE = L 20 40

✻✻

ns

3-State Disable Time OE = H 18 10

✻✻

ns

OE Internal Pull-Down to Gnd 50

✻

kΩ

Power-Down Enable Time Pwrdn = L 133

✻

ns

Power-Down Disable Time Pwrdn = H 18

✻

ns

Power-Down Internal Pull-Down to Gnd 50

✻

kΩ

ACCURACY

Gain Error Full 0.5 1 %FS
Input Offset Error

(4)

Full 1.4

✻

%FS

Power Supply Rejection (Gain) ∆ V

S

= ±5% Full 42 56

✻✻

dB

Power Supply Rejection (Offset) ∆ V

S

= ±5% Full 42 68

✻✻

dB

External REFT Voltage Range Full

REFB +0.5

+3.25 VS–0.8

✻

+4

✻

V

External REFB Voltage Range Full +0.8 +2.25

REFT –0.5

✻

+2

✻

V

Reference Input Resistance REFT to REFB 4

✻

kΩ

1Vp-p 2Vp-p

TTL/HCT Compatible CMOS

TTL/HCT Compatible CMOS

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility
for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights
or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life
support devices and/or systems.

TTL/HCT Compatible CMOS

Straight Offset Binary

TTL/HCT Compatible CMOS

Straight Offset Binary

3

ADS902

®

SPECIFICATIONS (CONT)

At TA = +25°C, VS = LVDD = +5V, REFB = +2.25V, REFT = +3.25V, Sampling Rate = 30MHz, unless otherwise specified.

ADS902E

PARAMETER CONDITIONS TEMP MIN TYP MAX MIN TYP MAX UNITS

1Vp-p 2Vp-p

POWER SUPPLY REQUIREMENTS

Supply Voltage: +V

S

Full +4.25 +5.0 +5.25

✻✻✻

V

Supply Current: +I

S

Full 28

✻

mA

Power Dissipation Full 140 160

✻✻

mW

Power Dissipation (Power Down) Full 15

✻

mW

Thermal Resistance,

θ

JA

28-Pin SSOP 50

✻

°C/W

✻ Specification same as 1Vp-p.

NOTES: (1) The single-ended input range is set by REFB and REFT values. (2) dBFS means dB relative to Full Scale. (3) Effective number of bits (ENOB) is defined
by (SINAD – 1.76)/6.02. (4) Offset deviation from ideal negative full scale.

PACKAGE
DRAWING TEMPERATURE

PRODUCT PACKAGE NUMBER

(1)

RANGE

ADS902E 28-Pin SSOP 324 –40°C to +85°C

NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

PIN CONFIGURATION

Top VIew SSOP

PIN DESIGNATOR DESCRIPTION

1+V

S

Analog Supply

2LV

DD

Output Logic Driver Supply Voltage
3 Bit 10 Data Bit 10 (D0, LSB)
4 Bit 9 Data Bit 9 (D1)
5 Bit 8 Data Bit 8 (D2)
6 Bit 7 Data Bit 7 (D3)
7 Bit 6 Data Bit 6 (D4)
8 Bit 5 Data Bit 5 (D5)
9 Bit 4 Data Bit 4 (D6)

10 Bit 3 Data Bit 3 (D7)
11 Bit 2 Data Bit 2 (D8)
12 Bit 1 Data Bit 1 (D9, MSB)
13 GND Analog Ground
14 GND Analog Ground
15 CLK Convert Clock Input
16 OE Output Enable, Active Low
17 Pwrdn Power Down Pin
18 +V

S

Analog Supply

19 GND Analog Ground
20 GND Analog Ground
21 LpBy Positive Ladder Bypass
22 REFT Top Reference
23 NC No Connection
24 REFB Bottom Reference
25 LnBy Negative Ladder Bypass
26 CM Common-Mode Voltage Output
27 IN Analog Input
28 +V

S

Analog Supply

PIN DESCRIPTIONS

PACKAGE/ORDERING INFORMATION

+VS, LV

DD

.................................................................................................................................. +6V

Analog Input ...............................................................................+V

S

+0.3V

Logic Input .................................................................................+V

S

+0.3V

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature ..................................................................... +150°C

ABSOLUTE MAXIMUM RATINGS

+VS

LV

DD



(LSB) Bit 10

Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2

(MSB) Bit 1

GND
GND

+V

S

IN
CM
LnBY
REFB
NC
REFT
LpBY
GND
GND
+V

S


Pwrdn
OE
CLK

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

ADS902

4

®

ADS902

5 Clock Cycles

Data Invalid

t

D

tLt

H

t

CONV

N–5 N–4 N–3 N–2 N–1 N N+1 N+2Data Out

Clock

Analog In

N

t

2

N+1

N+2

N+3

N+4

N+5

N+6

N+7

t

1

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

CONV

Convert Clock Period 33 100µsns

t

L

Clock Pulse Low 15.5 16.5 ns

t

H

Clock Pulse High 15.5 16.5 ns

t

D

Aperture Delay 2 ns

t

1

Data Hold Time, CL = 0pF 4 ns

t

2

New Data Delay Time, CL = 15pF max 12 ns

TIMING DIAGRAM