Burr Brown Corporation ADS830E-2K5, ADS830 Datasheet

8-Bit, 60MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● HIGH SNR: 49.5dB

● INTERNAL/ EXTERNAL REFERENCE

OPTION

● SINGLE-ENDED OR

DIFFERENTIAL ANALOG INPUT

● PROGRAMMABLE INPUT RANGE:

1Vp-p/ 2Vp-p

● LOW POWER: 170mW

● LOW DNL: 0.2LSB

● SINGLE +5V SUPPLY OPERATION

● 20-PIN SSOP PACKAGE

APPLICATIONS

● MEDICAL IMAGING

● VIDEO DIGITIZING

● COMMUNICATIONS

● DISK-DRIVE CONTROL

DESCRIPTION

The ADS830 is a pipeline, CMOS analog-to-digital con­verter that operates from a single +5V power supply. This
converter provides excellent performance with a single­ended input and can be operated with a differential input
for added spurious performance. This high performance
converter includes an 8-bit quantizer, high bandwidth
track/hold, and a high accuracy internal reference. It also
allows for the user to disable the internal reference and
utilize external references. This external reference option
provides excellent gain and offset matching when used in
multi-channel applications or in applications where DC full
scale range adjustment is required.

The ADS830 employs digital error correction techniques to
provide excellent differential linearity for demanding im­aging applications. Its low distortion and high SNR give
the extra margin needed for medical imaging, communica­tions, video, and test instrumentation.

The ADS830 is specified at a maximum sampling fre­quency of 60MHz and a single-ended input range of 1.5V
to 3.5V. The ADS830 is available in a 20-lead SSOP
package and is pin-for-pin compatible with the 8-bit, 80MHz
ADS831.

TM

ADS830

®

¤

ADS830

©

1998 Burr-Brown Corporation PDS-1429B Printed in U.S.A. October, 1998

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone]

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8-Bit
Pipelined
A/D Core

Internal

Reference

Optional External

Reference

Timing

Circuitry

Error

Correction

Logic

3-State

Outputs

T/H

CLK VDRV

ADS830

+V

S

Int/Ext

D0

D7

•

•

•

INV

IN

IN

(Opt)

2

®

ADS830

SPECIFICATIONS

At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, and external reference, unless otherwise noted.

ADS830E

PARAMETER CONDITIONS MIN TYP MAX UNITS
RESOLUTION 8 Guaranteed Bits

SPECIFIED TEMPERATURE RANGE Ambient Air –40 to +85 °C
ANALOG INPUT

Standard Single-Ended Input Range 2Vp-p 1.5 3.5 V
Optional Single-Ended Input Range 1Vp-p 2 3 V
Common-Mode Voltage 2.5 V
Optional Differential Input Range 2Vp-p 2 3 V
Analog Input Bias Current 1 µA
Input Impedance 1.25 || 5 MΩ || pF
Track-Mode Input Bandwidth –3dBFS 300 MHz

CONVERSION CHARACTERISTICS

Sample Rate 10k 60M Samples/s
Data Latency 4 Clk Cyc

DYNAMIC CHARACTERISTICS

Differential Linearity Error (Largest Code Error)

f = 1MHz ±0.1 ±1.0 LSB

f = 10MHz ±0.2 LSB
No Missing Codes Guaranteed
Integral Nonlinearity Error, f = 1MHz ±0.3 ±1.5 LSBs
Spurious Free Dynamic Range

(1)

f = 1MHz (–1dB input) 67 dBFS

(2)

f = 10MHz (–1dB input) 54 65 dBFS
Two-Tone Intermodulation Distortion

(3)

f = 9.5MHz and 9.9MHz (–7dB each tone) –60 dBc
Signal-to-Noise Ratio (SNR) Referred to Full Scale

f = 1MHz 49.5 dB

f = 10MHz 47 49.5 dB
Signal-to-(Noise + Distortion) (SINAD) Referred to Full Scale

f = 1MHz 48 dB

f = 10MHz 45 48 dB
Effective Number of Bits

(4)

, f = 1MHz 7.7 Bits
Differential Gain Error NTSC, PAL 0.2 %
Differential Phase Error NTSC, PAL 0.2 degrees
Output Noise Input Tied to Common-Mode 0.2 LSBs rms
Aperture Delay Time 3ns
Aperture Jitter 1.2 ps rms
Overvoltage Recovery Time 2ns
Full-Scale Step Acquisition Time 2.5 ns

DIGITAL INPUTS

Logic Family
Convert Command Start Conversion
High Level Input Current

(5)

(VIN = 5V) 100 µA

Low Level Input Current (V

IN

= 0V) 10 µA
High Level Input Voltage +2.4 V
Low Level Input Voltage +1.0 V
Input Capacitance 5pF

DIGITAL OUTPUTS

Logic Family
Logic Coding
Low Output Voltage (I

OL

= 50µA) VDRV = 5V +0.1 V

Low Output Voltage, (I

OL

= 1.6mA) +0.2 V

High Output Voltage, (I

OH

= 50µA) +4.9 V
High Output Voltage, (IOH = 0.5mA) +4.8 V
Low Output Voltage, (I

OL

= 50µA) VDRV = 3V +0.1 V

High Output Voltage, (I

OH

= 50µA) +2.8 V
Output Capacitance 5pF

ACCURACY (External Reference, 2Vp-p, Unless Otherwise Noted)

Zero Error (Referred to –FS) at 25°C –2.5 ±0.25 +2.5 %FS
Zero Error Drift (Referred to –FS) ±53 ppm/°C
Gain Error

(6)

at 25°C –2.5 ±0.3 +2.5 %FS

Gain Error Drift

(6)

±75 ppm/°C

Power Supply Rejection of Gain ∆ V

S

= ±5% 58 dB
Internal REFT Tolerance Deviation from Ideal 3.0V ±10 ±100 mV
Internal REFB Tolerance Deviation from Ideal 2.0V ±10 ±100 mV
External REFT Voltage Range REFB + 0.8 3.0 V

S

– 1.25 V
External REFB Voltage Range 1.25 2.0 REFT – 0.8 V
Reference Input Resistance REFT to REFB 800 kΩ

CMOS/TTL Compatible

Rising Edge of Convert Clock

CMOS/TTL Compatible

Straight Offset Binary

3

®

ADS830

SPECIFICATIONS

At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, and external reference, unless otherwise noted.

ADS830E

PARAMETER CONDITIONS MIN TYP MAX UNITS

PIN CONFIGURATION

Top View SSOP

POWER SUPPLY REQUIREMENTS

Supply Voltage: +V

S

Operating +4.75 +5.0 +5.25 V

Supply Current: +I

S

Operating 37 45 mA

Power Dissipation: VDRV = 5V External Reference 185 225 mW

VDRV = 3V External Reference 170 mW
VDRV = 5V Internal Reference 215 mW
VDRV = 3V Internal Reference 200 mW

Thermal Resistance,

θ

JA

20-Lead SSOP 115 °C/W

NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full Scale. (3) Two-tone
intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental
envelope. (4) Effective number of bits (ENOB) is defined by (SINAD – 1.76) /6.02. (5) A 50k Ω pull-down resistor is inserted internally. (6) Excludes internal
reference.

PIN DESIGNATOR DESCRIPTION

1 GND Ground
2 Bit 1 Data Bit 1 (D7) (MSB)
3 Bit 2 Data Bit 2 (D6)
4 Bit 3 Data Bit 3 (D5)
5 Bit 4 Data Bit 4 (D4)
6 Bit 5 Data Bit 5 (D3)
7 Bit 6 Data Bit 6 (D2)
8 Bit 7 Data Bit 7 (D1)

9 Bit 8 Data Bit 8 (D0) (LSB)
10 CLK Convert Clock
11 RSEL Input Range Select: HI = 2V; LO = 1V
12 INT/EXT Reference Select: HI = External; LO = Internal
13 REFB Bottom Reference
14 REFT Top Reference
15 CM Common-Mode Voltage Output
16 IN Complementary Input
17 IN Analog Input
18 GND Ground
19 +VS +5V Supply
20 VDRV Output Logic Drive Supply Voltage

PIN DESCRIPTIONS

GND

Bit 1 (MSB)

Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7

Bit 8 (LSB)

CLK

VDRV
+V

S

GND
IN
IN
CM
REFT
REFB
INT/EXT
RSEL

1
2
3
4
5
6
7
8
9

10

20
19
18
17
16
15
14
13
12
11

ADS830

PACKAGE SPECIFIED
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE NUMBER

(1)

RANGE MARKING NUMBER MEDIA

ADS830E 20-Lead SSOP (QSOP) 349 –40°C to +85°C ADS830E ADS830E Rails

" " " " " ADS830E/1K Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. For detailed Tape and Reel
mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

PACKAGE/ORDERING INFORMATION

+VS....................................................................................................... +6V

Analog Input............................................................. –0.3V to (+V

S

+ 0.3V)

Logic Input ............................................................... –0.3V to (+V

S

+ 0.3V)

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature..................................................................... +150°C

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown recom­mends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

PRODUCT DEMO BOARD

ADS830 DEM-ADS830E

DEMO BOARD ORDERING INFORMATION

4

®

ADS830

TIMING DIAGRAM

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

CONV

Convert Clock Period 16.6 100µsns

t

L

Clock Pulse Low 7.3 8.3 ns

t

H

Clock Pulse High 7.3 8.3 ns

t

D

Aperture Delay 3 ns

t

1

Data Hold Time, CL = 0pF 3.9 ns

t

2

New Data Delay Time, CL = 15pF max 5.9 12 ns

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility
for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights
or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life
support devices and/or systems.

4 Clock Cycles

Data Invalid

t

D

tLt

H

t

CONV

N–4 N–3 N–2 N–1 N N+1 N+2 N+3Data Out

Clock

Analog In

N

t

2

N+1

N+2

N+3

N+4

N+5

N+6

N+7

t

1