Burr Brown Corporation ADS824E-1K, ADS824 Datasheet

ADS824

®

10-Bit, 70MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

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FEATURES

● HIGH SNR: 59dB

● HIGH SFDR: 70dB

● LOW POWER: 315mW

● INTERNAL/EXTERNAL REFERENCE

OPTION

● SINGLE-ENDED OR DIFFERENTIAL

ANALOG INPUT

● PROGRAMMABLE INPUT RANGE:

1Vp-p or 2Vp-p

● LOW DNL: 0.3LSB

● SINGLE +5V SUPPLY OPERATION

● +3V DIGITAL OUTPUT CAPABILITY

● POWER DOWN: 20mW

● 28-LEAD SSOP PACKAGE

APPLICATIONS

● MEDICAL IMAGING

● HDTV VIDEO DIGITIZING

● COMMUNICATIONS

● TEST EQUIPMENT

DESCRIPTION

The ADS824 is a pipeline, CMOS analog-to-digital converter
that operates from a single +5V power supply. This converter
provides excellent performance with a single-ended input and
can be operated with a differential input for added spurious
performance. This high performance converter includes a 10-bit
quantizer, high bandwidth track/hold, and a high accuracy
internal reference. It also allows for the user to disable the
internal reference and utilize external references. This external
reference option provides excellent gain and offset matching
when used in multi-channel applications or in applications
where full scale range adjustment is required.

The ADS824 employs digital error correction techniques to
provide excellent differential linearity for demanding imaging
applications. Its low distortion and high SNR give the extra
margin needed for medical imaging, communications, video,
and test instrumentation. The ADS824 offers power dissipa­tion of 315mW and also provides a power-down mode, thus
reducing power dissipation to only 20mW.

The ADS824 is specified at a maximum sampling frequency of
70MHz and a single-ended input range of 1.5V to 3.5V. The
ADS824 is available in a 28-lead SSOP package and is pin
compatible with the 10-bit, 40MHz ADS822 and the 10-bit,
60MHz ADS823.

ADS824E

TM

©

1997 Burr-Brown Corporation PDS-1403C Printed in U.S.A. April, 1999

10-Bit
Pipelined
A/D Core

Internal

Reference

Optional External

Reference

Timing

Circuitry

Error

Correction

Logic

3-State

Outputs

T/H

CLK VDRV

ADS824

+V

S

OEPDInt/Ext

D0

D9

•

•

•

INV

IN

IN

CM

2

®

ADS824

SPECIFICATIONS

At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 70MHz, external reference, unless otherwise noted.

CMOS-Compatible

Rising Edge of Convert Clock

CMOS-Compatible

Straight Offset Binary

ADS824E

PARAMETER CONDITIONS MIN TYP MAX UNITS
RESOLUTION 10 Guaranteed Bits

SPECIFIED TEMPERATURE RANGE Ambient Air –40 to +85 °C
ANALOG INPUT

Standard Single-Ended Input Range 2Vp-p 1.5 3.5 V
Optional Single-Ended Input Range 1Vp-p 2 3 V
Common-Mode Voltage 2.5 V
Optional Differential Input Range 2Vp-p 2 3 V
Analog Input Bias Current 1 µA
Input Impedance 1.25 || 5 MΩ || pF
Track-Mode Input Bandwidth –3dBFS 300 MHz

CONVERSION CHARACTERISTICS

Sample Rate 10k 70M Samples/s
Data Latency 5 Clk Cyc

DYNAMIC CHARACTERISTICS

Differential Linearity Error (largest code error)

f = 1MHz ±0.3 ±1.0 LSB

f = 10MHz ±0.3 LSB
No Missing Codes Guaranteed
Integral Nonlinearity Error, f = 1MHz ±0.5 ±3.0 LSBs
Spurious Free Dynamic Range

(1)

Referred to Full Scale

f = 1MHz 70 dBFS

(2)

f = 10MHz 60 68 dBFS
Two-Tone Intermodulation Distortion

(3)

f = 4.5MHz and 5.5MHz (–7dB each tone) –63.4 dBc
Signal-to-Noise Ratio (SNR) Referred to Full Scale

f = 1MHz 59 dB

f = 10MHz 55 59 dB
Signal-to-(Noise + Distortion) (SINAD) Referred to Full Scale

f = 1MHz 58 dB

f = 10MHz 50 58 dB
Effective Number of Bits

(4)

, f = 1MHz 9.3 Bits
Output Noise Input Grounded 0.2 LSBs rms
Aperture Delay Time 3ns
Aperture Jitter 1.2 ps rms
Overvoltage Recovery Time 2ns
Full-Scale Step Acquisition Time 5ns

DIGITAL INPUTS

Logic Family
Convert Command Start Conversion
High Level Input Current

(5)

(VIN = 5V) 100 µA
Low Level Input Current (VIN = 0V) 10 µA
High Level Input Voltage +3.5 V
Low Level Input Voltage +1.0 V
Input Capacitance 5pF

DIGITAL OUTPUTS

Logic Family
Logic Coding
Low Output Voltage (I

OL

= 50µA) VDRV = 5V +0.1 V

Low Output Voltage, (I

OL

= 1.6mA) +0.2 V

High Output Voltage, (I

OH

= 50µA) +4.9 V

High Output Voltage, (I

OH

= 0.5mA) +4.8 V

Low Output Voltage, (I

OL

= 50µA) VDRV = 3V +0.1 V
High Output Voltage, (IOH = 50µA) +2.8 V
3-State Enable Time OE = L 20 40 ns
3-State Disable Time OE = H 2 10 ns
Output Capacitance 5pF

ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted)

Zero Error (Referred to –FS) at 25°C ±0.5 ±3.0 %FS
Zero Error Drift (Referred to –FS) 12 ppm/°C
Gain Error

(6)

at 25°C ±1.5 ±2.5 %FS

Gain Error Drift

(6)

38 ppm/°C

Gain Error

(7)

at 25°C ±0.75 ±1.5 %FS

Gain Error Drift

(7)

20 ppm/°C

Power Supply Rejection of Gain ∆ V

S

= ±5% 68 dB
REFT Tolerance Deviation from Ideal 3.5V ±10 ±25 mV
REFB Tolerance Deviation From Ideal 1.5V ±10 ±25 mV
External REFT Voltage Range REFB + 0.8 3.5 V

S

– 1.25 V
External REFB Voltage Range 1.25 1.5 REFT – 0.8 V
Reference Input Resistance 1.6 kΩ

3

®

ADS824

PIN DESIGNATOR DESCRIPTION

1 GND Ground
2 Bit 1 Data Bit 1 (D9) (MSB)
3 Bit 2 Data Bit 2 (D8)
4 Bit 3 Data Bit 3 (D7)
5 Bit 4 Data Bit 4 (D6)
6 Bit 5 Data Bit 5 (D5)
7 Bit 6 Data Bit 6 (D4)
8 Bit 7 Data Bit 7 (D3)

9 Bit 8 Data Bit 8 (D2)
10 Bit 9 Data Bit 9 (D1)
11 Bit 10 Data Bit 10 (D0) (LSB)
12 OE Output Enable. HI = high impedance state.

LO = normal operation (internal pull-

down resistor)
13 PD Power Down. HI = power down; LO = normal
14 CLK Convert Clock Input
15 +V

S

+5V Supply
16 GND Ground

17 RSEL Input Range Select. HI = 2Vp-p; LO = 1Vp-p
18 INT/EXT Reference Select. HI = external; LO = internal
19 REFB Bottom Reference
20 ByB Bottom Ladder Bypass
21 ByT Top Ladder Bypass
22 REFT Top Reference
23 CM Common-Mode Voltage Output
24 IN Complementary Input (–)
25 IN Analog Input (+)
26 GND Ground
27 +V

S

+5V Supply
28 VDRV Output Logic Driver Supply Voltage

POWER SUPPLY REQUIREMENTS

Supply Voltage: +V

S

Operating +4.75 +5.0 +5.25 V

Supply Current: +I

S

Operating 66 mA
Output Driver Supply Current (VDRV) 9mA
Power Dissipation: VDRV = 5V External Reference 330 375 mW

VDRV = 3V External Reference 315 mW
VDRV = 5V Internal Reference 345 mW
VDRV = 3V Internal Reference 335 mW
Power Down Operating 20 mW

Thermal Resistance,

θ

JA

28-Lead SSOP 89 °C/W

NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full Scale. (3) Two-tone
intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental
envelope. (4) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (5) A 50kΩ pull-down resistor is inserted internally. (6) Includes internal
reference. (7) Excludes internal reference.

SPECIFICATIONS (CONT)

At TA = full specified temperature range, single-ended input range = 1.5V to 3.5V, sampling rate = 70MHz, external reference, unless otherwise noted.

ADS824E

PARAMETER CONDITIONS MIN TYP MAX UNITS

PIN DESCRIPTIONS

PIN CONFIGURATION

Top View SSOP

GND

Bit 1 (MSB)

Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9

Bit 10 (LSB)

OE
PD

CLK

VDRV
+V

S

GND
IN
IN
CM
REFT
ByT
ByB
REFB
INT/EXT
RSEL
GND
+V

S

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

ADS824

4

®

ADS824

TIMING DIAGRAM

5 Clock Cycles

Data Invalid

t

D

tLt

H

t

CONV

N–5 N–4 N–3 N–2 N–1 N N+1 N+2

Data Out

Clock

Analog In

N

t

2

N+1

N+2

N+3

N+4

N+5

N+6

N+7

t

1

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

CONV

Convert Clock Period 13.4 100µsns

t

L

Clock Pulse Low 6.4 6.7 ns

t

H

Clock Pulse High 6.4 6.7 ns

t

D

Aperture Delay 3 ns

t

1

Data Hold Time, CL = 0pF 3.9 ns

t

2

New Data Delay Time, CL = 15pF max 12 ns

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility
for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights
or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life
support devices and/or systems.

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

PACKAGE SPECIFIED
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE NUMBER

(1)

RANGE MARKING NUMBER

(2)

MEDIA

ADS824E SSOP-28 324 –40°C to +85°C ADS824E ADS824E Rails

" " " " " ADS824E/1K Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/ ) are
available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of ADS824E/iK” will get a single 1000­piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

PACKAGE/ORDERING INFORMATION

+VS....................................................................................................... +6V

Analog Input............................................................. –0.3V to (+V

S

+ 0.3V)

Logic Input ............................................................... –0.3V to (+V

S

+ 0.3V)

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature..................................................................... +150°C

ABSOLUTE MAXIMUM RATINGS

PRODUCT DEMO BOARD

ADS824E DEM-ADS824E

DEMO BOARD ORDERING INFORMATION