BURR-BROWN PCM3793A, PCM3794A User Manual

    

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

16-Bit, Low-Power Stereo Audio CODEC With Microphone Bias, Headphone, and Digital

Speaker Amplifier

PCM3793A PCM3794A

FEATURES

• 2 (I2C) or 3 (SPI) Wire Serial Control

• Analog Front End: • Programmable Function by Register Control:

– Stereo Single-Ended Input With Multiplexer – Digital Attenuation of DAC: 0 dB to –62 dB – Mono Differential Input – Digital Gain of DAC: 0, 6, 12, 18 dB – Stereo Programmable Gain Amplifier – Power Up/Down Control for Each Module – Microphone Amplifier (20 dB) and Bias – 6-dB to –70-dB Gain for Analog Outputs

• Analog Back End: – 30-dB to –12-dB Gain for Analog Inputs

– Stereo/Mono Line Output With Volume – 0/20 dB Selectable for Microphone Input – Stereo/Mono Headphone Amplifier With – 0-dB to –21-dB Gain for Analog Mixing

Volume and Capless Mode

– Stereo/Mono Digital Speaker Amplifier

(BTL) With Volume

• Analog Performance:

– Dynamic Range: 93 dB (DAC) – Dynamic Range: 90 dB (ADC) – 40-mW + 40-mW Headphone Output at

= 16 Ω

– 700-mW + 700-mW Speaker Output at

= 8 Ω

• Power Supply Voltage

– 1.71 V to 3.6 V for Digital I/O Section – 1.71 V to 3.6 V for Digital Core Section – 2.4 V to 3.6 V for Analog Section

– Parameter Settings for ALC – Three-Band Tone Control and 3D Sound – High-Pass Filter: 4-, 120-, 240-Hz – Two-Stage Programmable Notch Filter – Analog Mixing Control

• Pop-Noise Reduction Circuit

• Short and Thermal Protection Circuit

• Package: 5-mm × 5-mm QFN Pacakge

• Operation Temperature Range: –40 ° C to 85 ° C

APPLICATIONS

• Portable Audio Player, Cellular Phone

• Video Camcorder, Digital Movie/Still Camera

• PMP/DMB

– 2.4 V to 3.6 V for Power Amplifier Section

• Low Power Dissipation:

– 7 mW in Playback, 1.8 V/2.4 V, 48 kHz – 13 mW in Record, 1.8 V/2.4 V, 48 kHz – 3.3 µ W in Power Down

• Sampling Frequency: 5 kHz to 50 kHz

• Automatic Level Control for Recording

• Operation From a Single Clock Input Without

PLL

• System Clock:

– Common-Audio Clock (256 fS/384 fS), 12/24,

13/26, 13.5/27, 19.2/38.4, 19.68/39.36 MHz

• Headphone Plug Insert Detection

DESCRIPTION

The PCM3793A/94A is a low-power stereo CODEC designed for portable digital audio applications. The device integrates stereo digital speaker amplifier, headphone amplifier, line amplifier, line input, boost amplifier, microphone bias, programmable gain control, analog mixing, sound effects, and automatic level control (ALC). It is available in a small-footprint, 5-mm × 5-mm QFN package. The PCM3793A/94A supports right-justified, left-justified, I2S, and DSP formats, providing easy interfacing to audio DSP and decoder/encoder chips. Sampling rates up to 50 kHz are supported. The user-programmable functions are accessible through a two- or three-wire serial control port.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage VDD, VIO, VCC, V Ground voltage differences: DGND, AGND, PGND ± 0.1 V Input voltage –0.3 to 4 V Input current (any pins except supplies and SPK out) ±10 mA Ambient temperature under bias –40 to 110 ° C Storage temperature –55 to 150 ° C Junction temperature 150 ° C Lead temperature (soldering) 260 ° C, 5 s Package temperature (reflow, peak) 260 ° C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(1)

MAX UNIT

–0.3 to 4 V

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

VCC, V VDD, V

Analog supply voltage 2.4 3.3 3.6 V

Digital supply voltage 1.71 3.3 3.6 V

Digital input logic family CMOS

Digital input clock frequency

Analog output load resistance HPOL and HPOR 16 Ω

Analog output load capacitance 30 pF Digital output load capacitance 10 pF Operating free-air temperature –40 85 ° C

SCKI system clock 3.072 18.432 MHz LRCK sampling clock 8 48 kHz LOL and LOR 10 k Ω

SPOLP, SPOLN, SPORP and SPORN 8 Ω

MIN NOM MAX UNIT

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PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

ELECTRICAL CHARACTERISTICS

All specifications at TA= 25 ° C, V otherwise noted).

PARAMETER TEST CONDITIONS UNIT

Audio Data Characteristics DATA FORMAT

Resolution 16 Bits

Audio data interface format

Audio data bit length 16 Bits

Audio data format 2s

Sampling frequency (fS) 5 50 kHz

System clock MHz

Digital Input/Output

Logic family

V I

V V

Digital Input to Line Output Through DAC (LOL, LOR, and MONO)

RL= 10 k Ω , ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = disabled

DYNAMIC PERFORMANCE

SNR Signal-to-noise ratio EIAJ, A-weighted 86 93 dB

THD+N Total harmonic distortion + noise 0 dB 0.008%

Line Input to Line Output Through Mixing Path (LOL, LOR, and MONO)

RL= 10 k Ω , ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = enabled

DYNAMIC PERFORMANCE

SNR Signal-to-noise ratio EIAJ, A-weighted 84 93 dB

Input logic level VDC

Input logic current µ A

Output logic level VDC

Full-scale output voltage 0 dB

Dynamic range EIAJ, A-weighted 93 dB

Channel separation 91 dB

Load resistance 10 k Ω

Full-scale input and output voltage

= V

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data (unless

PCM3793ARHB, PCM3794ARHB

MIN TYP MAX

I2S, left-,

right-

justified,

DSP

MSB first,

complement

< 2 V 27

> 2 V 40

CMOS

compatible

0.7 V

0.3 V

VIN= 3.3 V 10 VIN= 0 V –10 IOH= –2 mA 0.75 V IOL= 2 mA 0.25 V

2.828 Vp-p 1 Vrms

0 dB

2.828 Vp-p 1 Vrms

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PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= 25 ° C, V otherwise noted).

PARAMETER TEST CONDITIONS UNIT

Digital Input to Headphone Output Through DAC (HPOL and HPOR)

RL= 16 Ω or 32 Ω , ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = disabled, not capless mode

DYNAMIC PERFORMANCE

Full-scale output voltage 0 dB

SNR Signal-to-noise ratio EIAJ, A-weighted 84 93 dB

THD+N Total harmonic distortion + noise

Load resistance 16 Ω

PSRR Power-supply rejection ratio 1 kHz, 140 mVp-p –45 dB

Line Input to Headphone Output Through Mixing Path (HPOL and HPOR)

RL= 16 Ω or 32 Ω , ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = enabled, not capless mode

DYNAMIC PERFORMANCE

Full-scale output voltage 0 dB

SNR Signal-to-noise ratio EIAJ, A-weighted 84 93 dB

Load resistance 16 Ω

Digital Input to Speaker Output Through DAC (SPOLP, SPOLN, SPORP, and SPORN): PCM3793A

RL= 8 Ω , ALC = OFF, volume = 0 dB, headphone = powered down, analog mixing = disabled

DYNAMIC PERFORMANCE

Full-scale output voltage 0 dB

SNR Signal-to-noise ratio EIAJ, A-weighted 84 93 dB THD+N Total harmonic distortion + noise 400 mW, RL= 8 Ω , volume = 0 dB 0.3%

Load resistance 8 Ω

PSRR Power-supply rejection ratio 1 kHz, 140 mVp-p –45 dB

Line Input to Speaker Output Through Mixing Path (SPOLP, SPOLN, SPORP, and SPORN): PCM3793A

RL= 8 Ω , ALC = OFF, volume = 0 dB, headphone = powered down, analog mixing = enabled

DYNAMIC PERFORMANCE

Full-scale output voltage 0 dB

SNR Signal-to-noise ratio EIAJ, A-Weighted 84 93 dB

= V

30 mW, RL= 32 Ω , volume = 0 dB 0.1% 40 mW, RL= 16 Ω , volume = –1 dB 0.03%

200 Hz, 140 mVp-p –40

20 kHz, 140 mVp-p –32

200 Hz, 140 mVp-p –50

20 kHz, 140 mVp-p –25

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data (unless

PCM3793ARHB, PCM3794ARHB

MIN TYP MAX

2.828 Vp-p

2.52 Vp-p

0.9 Vrms

2.52 Vp-p

0.9 Vrms

1 Vrms

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PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= 25 ° C, V otherwise noted).

PARAMETER TEST CONDITIONS UNIT

Line Input to Digital Output Through ADC (AIN1L/R, AIN2L/R, AIN3L, and AIN3L/R)

ALC = OFF, microphone boost = 0 dB, PGA = 0 dB, speaker and headphone = powered down, analog mixing = disabled

DYNAMIC PERFORMANCE

Full-scale input voltage 0 dB

Dynamic range EIAJ, A-weighted 90 dB

SNR Signal-to-noise ratio EIAJ, A-weighted 83 90 dB

Channel separation 87 dB

THD+N Total harmonic distortion + noise –1 dB 0.009%

ANALOG INPUT

Center voltage 0.5 V Input impedance 10 20 k Ω

Microphone Bias

ALC = OFF, microphone boost = 0 dB, PGA = 0 dB, speaker and headphone = powered down, analog mixing = disabled

Bias voltage 0.75 V Bias source current 2 mA Output noise 6.5 µ V

Filter Characteristics INTERPOLATION FILTER FOR DAC

Pass band 0.454 f Stop band 0.546 f Pass-band ripple ± 0.04 dB Stop-band attenuation –50 dB Group delay 19/f De-emphasis error ± 0.1 dB

ANALOG FILTER FOR DAC

Frequency response f = 20 kHz ± 0.2 dB

DECIMATION FILTER FOR ADC

Pass band 0.408 f Stop band 0.591 f Pass-band ripple ± 0.02 dB Stop-band attenuation f < 3.268 f Group delay 17/f

HIGH-PASS FILTER FOR ADC

Frequency response Hz

= V

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data (unless

PCM3793ARHB, PCM3794ARHB

MIN TYP MAX

2.828 Vp-p 1 Vrms

–60 dB

–3 dB, fc= 4 Hz 3.74 –0.5 dB, fc= 4 Hz 10.66 –0.1 dB, fc= 4 Hz 24.2 –3 dB, fc= 240 Hz 235.68 –0.5 dB, fc= 240 Hz 609.95 –0.1 dB, fc= 240 Hz 2601.2

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PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= 25 ° C, V otherwise noted).

PARAMETER TEST CONDITIONS UNIT

Power Supply and Supply Current

V V

Temperature Condition

Voltage range VDC

CC PA

Supply current

Power dissipation

Operation temperature –40 85 ° C Thermal resistance 30 ° C/W

= V

BPZ input, all active, no load 24.3 35 mA All inputs are held static 1 10 µ A BPZ input 80.2 115.5 mW All inputs are held static 3.3 33 µ W

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data (unless

PCM3793ARHB, PCM3794ARHB

MIN TYP MAX

1.71 3.3 3.6

2.4 3.3 3.6

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P0048-05

HPOR/LORAIN2L

BCK

AIN2R

24123222321420519618717

1130

1031

932

SPOLP

AIN3L

SPOLN

AIN3R

PGND

MICB

SPORP

AGND

SPORN

COM

HPCOM/MONO

HPOL/LOL

PCM3793ARHB

(TOP VIEW)

AIN1R

DIN

AIN1L

DOUT

MODE

MS/ADR

MD/SDA

DGND

MC/SCL

SCKI

LRCK

HDTI

P0048-06

HPOR/LORAIN2L

BCK

AIN2R

24123222321420519618717

1130

1031

932

AIN3LNCAIN3R

PGND

MICB

AGNDNCV

COM

HPCOM/MONO

HPOL/LOL

PCM3794ARHB

(TOP VIEW)

AIN1R

DIN

AIN1L

DOUT

MODE

MS/ADR

MD/SDA

DGND

MC/SCL

SCKI

LRCK

HDTI

PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

PIN ASSIGNMENTS

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PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

Table 1. TERMINAL FUNCTIONS

TERMINAL

NAME PCM3793ARHB PCM3794ARHB

AGND 19 19 – Ground for analog AIN1L 27 27 I Analog input 1 for L-channel AIN1R 26 26 I Analog input 1 for R-channel AIN2L 25 25 I Analog input 2 for L-channel AIN2R 24 24 I Analog input 2 for R-channel AIN3L 23 23 I Analog input 3 for L-channel AIN3R 22 22 I Analog input 3 for R-channel BCK 1 1 I/O Serial bit clock DGND 6 6 – Digital ground DIN 2 2 I Serial audio data input DOUT 3 3 O Serial audio data output HDTI 8 8 I Headphone plug insertion detection HPCOM/MONO 9 9 O Headphone common/mono line output HPOL/LOL 17 17 O Headphone/lineout for R-channel HPOR/LOR 16 16 O Headphone/lineout for L-channel LRCK 32 32 I/O Left and right channel clock MC/SCL 31 31 I Mode control clock for three-wire/two-wire interface MD/SDA 30 30 I/O Mode control data for three-wire/two-wire interface MICB 21 21 O Microphone bias source output MODE 28 28 I Two- or three-wire interface selection (LOW: SPI, HIGH: I2C) MS/ADR 29 29 I Mode control select for three-wire/two-wire interface PGND 13 13 – Ground for speaker power amplifier SCKI 7 7 I System clock SPOLN 14 – O Speaker output L-channel for negative (PCM3793A) SPOLP 15 – O Speaker output L-channel for positive (PCM3793A) SPORN 10 – O Speaker output R-channel for negative (PCM3793A) SPORP 11 – O Speaker output R-channel for positive (PCM3793A) V

COM

20 20 – Analog power supply 18 18 – Analog common voltage

5 5 – Power supply for digital core 4 4 – Power supply for digital I/O

12 12 – Power supply for power amplifier

I/O DESCRIPTION

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FUNCTIONAL BLOCK DIAGRAM

AIN3L

AIN2L

AIN1L

AIN1R

AIN2R

AIN3R

BCK

DOUT

LRCK

S/ADRMC/SCL

D/SDA

MODE

rial Interface (SPI/I C)

SCKI

Audio Interface

PGND

AGND

DGND

COM

MICB

SPOLP

SPOLN

SPORP

SPORN

HDTI

0181-02

6to –70dB

+6to –70dB

SPL

SPR

MUX1

DAL

ADL

DAR

COM

HPR

ROUT

MON

Mic Bias

PG4

0/+

20dB

0/+

20dB

0to –21dB

+30to –12dB

0to –12dB

MONO

lock

anager

wer On

set

Power Up/Down

Manager

ADR

D2S

MUX3

MUX2

MUX4

PG6

PG2

Anal

og Input L-ch

Analog Input R-ch

MXL

HPOL

ossible for Power Up/Down

CM3794 has no Speaker Output

SW2

SW6

SW5

SW4

HPOL/

LOL

HPOR/

LOR

HPCOM

/MONO

ADC

DAC

Digital

Filter

(1)

Digital

Filter

(1)

Digital

Filter

(1)

Digital

Filter

(1)

ATR

Mute

DGC

0,+6,+12,+18dB

0to –62dB,Mute

(1)

DecimationFilter

InterpolationFilter

3-DEnhancement

3-Band

oneControl

NotchFilter

PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

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–120

–100

–80

–60

–40

–20

0 1 2 3 4

Frequency [ f ]´

Amplitude – dB

G001

Frequency [ f ]´

Amplitude – dB

–0.2

–0.1

0.1

0.2

0 0.1 0.2 0.3 0.4 0.5

G002

Frequency [ f ]´

Amplitude – dB

G003

–120

–100

–80

–60

–40

–20

0 1 2 3 4

Frequency [ f ]´

Amplitude – dB

–0.2

–0.1

0.1

0.2

0 0.1 0.2 0.3 0.4 0.5

G004

PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

All specifications at TA= 25 ° C, V

INTERPOLATION FILTER, STOP BAND INTERPOLATION FILTER, PASS BAND

TYPICAL PERFORMANCE CURVES

= V

= 3.3 V, fS= 8 to 48 kHz, system clock = 256 fS, and 16-bit data,

unless otherwise noted.

Figure 1. Figure 2.

DECIMATION FILTER, STOP BAND DECIMATION FILTER, PASS BAND

Figure 3. Figure 4.

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Frequency [ f ]´

Amplitude – dB

G005

–20

–15

–10

–5

0 0.0005 0.001 0.0015 0.002

Frequency [ f ]´

Amplitude – dB

G025

–20

–15

–10

–5

0 0.005 0.01 0.015 0.02

Frequency [ f ]´

Amplitude – dB

G006

–20

–15

–10

–5

0 0.01 0.02 0.03 0.04

All specifications at TA= 25 ° C, V unless otherwise noted.

TYPICAL PERFORMANCE CURVES (continued)

= V

= 3.3 V, fS= 8 to 48 kHz, system clock = 256 fS, and 16-bit data,

PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

HIGH-PASS FILTER PASS-BAND CHARACTERISTICS HIGH-PASS FILTER PASS-BAND CHARACTERISTICS

(fC= 4 Hz at fS= 48 kHz) (fC= 120 Hz at fS= 48 kHz)

Figure 5. Figure 6.

HIGH-PASS FILTER PASS-BAND CHARACTERISTICS

(fC= 240 Hz at fS= 48 kHz)

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Figure 7.

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Frequency – Hz

Amplitude – dB

G007

–15

–10

–5

0.01 0.1 1 10 1k100 10k

100k

Frequency – Hz

Amplitude – dB

G008

–15

–10

–5

200

600400 800

Frequency – Hz

mplitude – dB

G009

–15

–10

–5

3k2k 4k

Frequency – Hz

Amplitude – dB

G010

–15

–10

–5

8k6k 10k

12k 14k

PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

TYPICAL PERFORMANCE CURVES (continued)

All specifications at TA= 25 ° C, V

= V

= 3.3 V, fS= 44.1 kHz, system clock = 256 fS, and 16-bit data, unless

otherwise noted.

THREE-BAND TONE CONTROL (BASS, MIDRANGE,

TREBLE) THREE-BAND TONE CONTROL (BASS)

Figure 8. Figure 9.

THREE-BAND TONE CONTROL (MIDRANGE) THREE-BAND TONE CONTROL (TREBLE)

Figure 10. Figure 11.

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PG3/PG4 Gain – dB

SNR – dB

G011

100

1510 20

25 30

Single Input

Differential Input

f = 1 kHz

PG3/PG4 Gain – dB

SNR – dB

G012

1510 20

25 30

Single Input

Differential Input

f = 1 kHz

Power Supply – V

THD+N – %

SNR – dB

G013

0.2

0.4

0.6

0.8

2 2.5 3.53 4

f = 1 kHz

THD+N

SNR

Power Supply – V

THD+N – %

SNR – dB

G014

0.01

0.02

0.03

0.04

0.05

2 2.5 3.53 4

f = 1 kHz

THD+N

SNR

All specifications at TA= 25 ° C, V

ADC SNR AT HIGH GAIN (PG1/PG2 = 0 dB) ADC SNR AT HIGH GAIN (PG1/PG2 = 20 dB)

TYPICAL PERFORMANCE CURVES (continued)

= V

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data, unless

otherwise noted.

PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

THD+N/SNR vs POWER SUPPLY THD+N/SNR vs POWER SUPPLY DAC TO SPEAKER OUTPUT, 8- Ω DAC TO HEADPHONE OUTPUT, 16- Ω

Figure 12. Figure 13.

Figure 14. Figure 15.

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Power Supply – V

THD+N – %

SNR – dB

G015

0.007

0.008

0.009

0.010

0.011

0.012

2 2.5 3.53 4

f = 1 kHz

THD+N

SNR

Power Supply – V

THD+N – %

SNR – dB

G016

0.007

0.008

0.009

0.010

0.011

0.012

2 2.5 3.53 4

f = 1 kHz

THD+N

SNR

2 2.5 3.5 43

100

120

Power Supply – V

utput Power – mW

G017

Vol = 6 dB

Vol = 0 dB

f = 1 kHz

Power Supply – V

tput Power – mW

G018

400

300

200

100

500

600

700

800

900

2.5 3

3.5 4

Vol = +6 dB

Vol = 0 dB

f = 1 kHz

PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

TYPICAL PERFORMANCE CURVES (continued)

All specifications at TA= 25 ° C, V otherwise noted.

THD+N/SNR vs POWER SUPPLY THD+N/SNR vs POWER SUPPLY

DAC TO LINE OUTPUT, 10-k Ω ADC TO DIGITAL OUTPUT

= V

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data, unless

OUTPUT POWER vs POWER SUPPLY OUTPUT POWER vs POWER SUPPLY

(HEADPHONE, 16- Ω ) (SPEAKER, 8- Ω )

Figure 16. Figure 17.

Figure 18. Figure 19.

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Output Power – mW

HD+N – %

G019

0.01

0.1

100

6040 80

100 120

f = 1 kHz

2.4 V

2.7 V

3.3 V

3.6 V

Output Power – mW

HD+N – %

G020

0.01

0.1

6040

f = 1 kHz

2.4 V

2.7 V

3.3 V

3.6 V

Output Power – mW

THD+N – %

G021

0.01

0.1

100

200

600400 800

1000

f = 1 kHz

2.4 V

2.7 V

3.3 V

3.6 V

Output Power – mW

THD+N – %

G022

0.01

0.1

100 200 300

500400

600

2.4 V

2.7 V

3.3 V

3.6 V

f = 1 kHz

All specifications at TA= 25 ° C, V otherwise noted.

THD+N vs OUTPUT POWER THD+N vs OUTPUT POWER

(HEADPHONE, 16- Ω , VOLUME = 6 dB) (HEADPHONE, 16- Ω , VOLUME = 0 dB)

TYPICAL PERFORMANCE CURVES (continued)

= V

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data, unless

PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

Figure 20. Figure 21.

THD+N vs OUTPUT POWER THD+N vs OUTPUT POWER

(SPEAKER, 8- Ω , VOLUME = 6 dB) (SPEAKER, 8- Ω , VOLUME = 0 dB)

Figure 22. Figure 23.

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Frequency – kHz

Amplitude – dB

G023

–140

0 20

155 10

–120

–100

–80

–60

–40

–20

f = 1 kHz/–60 dB

Frequency – kHz

mplitude – dB

G024

–140

0 20

155 10

–120

–100

–80

–60

–40

–20

f = 1 kHz/–60 dB

PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

TYPICAL PERFORMANCE CURVES (continued)

All specifications at TA= 25 ° C, V otherwise noted.

= V

= 3.3 V, fS= 48 kHz, system clock = 256 fS, and 16-bit data, unless

OUTPUT SPECTRUM (DAC TO HEADPHONE OUTPUT,

16- Ω ) OUTPUT SPECTRUM (DAC TO SPEAKER OUTPUT, 8- Ω )

Figure 24. Figure 25.

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PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

PCM3793A/94A DESCRIPTION

Analog Input

The AIN1L, AIN1R, AIN2L, AIN2R, AIN3L, and AIN3R pins can be used as microphone or line inputs with selectable 0- or 20-dB boost and 1-Vrms input. All of these analog inputs have high input impedance (20 k Ω ), which is not changed by gain settings. One pair of inputs is selected by register 87 (AIL[1:0], AIR[1:0]). AIN1L and AIN1R can be used as a monaural differential input.

Gain Settings for Analog Input

The gain of the analog signals can be adjusted from 30 dB to –12 dB in 1-dB steps following the 0- or 20-dB boost amplifier. The gain level can be set for each channel by registers 79 and 80 (ALV[5:0], ARV[5:0]).

A/D Converter

The ADC includes a multilevel delta-sigma modulator, aliasing filter, decimation filter, high-pass filter, and notch filter and can accept a 1-Vrms full-scale voltage input. The decimation filter has a digital soft mute controlled by register 81 (RMUL, RMUR). The high-pass filter can be disabled by register 81 (HPF[1:0]), and the notch filter can be disabled by registers 96 to 104 if it is not necessary to cancel a dc offset or compensate for wind noise.

D/A Converter

The DAC includes a multilevel delta-sigma modulator and an interpolation filter. These can be used to obtain high PSRR, low jitter sensitivity, and low out-of-band noise quickly and easily. The interpolation filter includes digital attenuator, digital soft mute, three-band tone control (bass, midrange and treble), and 3-D sound controlled by registers 92 to 95. The de-emphasis filter (32, 44.1 and 48 kHz) is controlled by registers 68 to 70 (ATL[5:0], ATR[5:0], PMUL, PMUR, DEM[1:0]). Oversampling rate control can reduce out-of-band noise when operating at low sampling rates by using register 70 (OVER).

Common Voltage

The V

pin is normally biased to 0.5 V

COM

, and it provides the common voltage to internal circuitry. It is

recommended that a 4.7- µ F capacitor be connected between this pin and AGND to provide clean voltage and avoid pop noise. The PCM3793A/94A may have a little pop noise on each analog output if a capacitor smaller than 4.7 µ F is used.

Line Output

The HPOL/LOL, HPOR/LOR, and HPCOM/MONO pins can drive a 10-k Ω load and be configured by register 74 (HPS[1:0]) as a monaural single-ended, monaural differential, or stereo single-line output with 1-V

output.

rms

These outputs, except for the HPCOM/MONO pin, include an analog volume amplifier that can be set from 6 dB to –70 dB and mute in steps of 0.5-, 1-, 2- or 4-dB. Each output is controlled by registers 64 and 65 (HLV[5:0], HRV[5:0], HMUL, HMUR). No dc blocking capacitor is required when connecting an external speaker amplifier with monaural differential input. The center voltage is 0.5 V

with zero data input.

Headphone Output

The HPOL/LOL, HPOR/LOR, and HPCOM/MONO pins can be configured as a stereo, monaural, or monaural differential headphone output by register 74 (HPS[1:0]). These pins have more than 30 or 40 mWrms output power into a 32- or 16- Ω load, either through a dc blocking capacitor or without a capacitor. These outputs, except for the HPCOM/MONO pin, include an analog volume amplifier that can be set from 6 dB to –70 dB in steps of 0.5, 1, 2, or 4 dB. Each is controlled by registers 64 and 65 (HLV[5:0], HRV[5:0], HMUL, HMUR). The center voltage is 0.5 V

with zero data input.

Headphone Plug Insertion Detection

The HDTI pin detects the insertion status of headphone plug and writes the status to register 77 (HPDS), which can be read by the I2C interface. The polarity of the status indication can be inverted by register 75 (HPDP). The headphone and speaker amplifiers are disabled or enabled automatically by headphone plug insertion/extractrion if register 75, HPDE = 1. They follow the register settings if register 75, HPDE = 0. HPCOM/MONO is not affected by the status when register 74, CMS[0] = 1.

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PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

Speaker Output (Class-D, PCM3793A)

The SPOLP/SPOLN and SPORP/SPORN pins are stereo or mono speaker differential outputs (BTL) pairs with a maximum of 700 mWrms (V maximum battery life, minimum heat, and elimination of LC low-pass filtering. The speaker amplifier includes an analog volume control with 6 dB to –70 dB in steps of 0.5, 1, 2 or 4 dB steps for each output, which can be set by registers 66 (SLV[5:0] and 67 SRV[5:0]). Spectrum spreading technology and selectable switching frequency to reduce EMI noise are controlled by register 71 (DFQ[2:0], SPS[1:0] and SPSE). This digital amplifier has a thermal shutdown circuit that detects when the device temperature reaches approximately 150 ° C; then the speaker amplifier is shut down.

Analog Mixing and Bypass

Mixing amplifiers (MXL, MXR) mix inputs from the AIN pins. The analog inputs are selected by register 87 (AD2S, AIR[1:0],AIL[1:0]) and can bypass the ADC/DAC and connect the mixed signal to the headphone or speaker outputs by register 88 (MXR[2:0], MXL[2:0]). The gain of the analog inputs is controlled by register 89 (GMR[2:0], GML[2:0]). These functions are suitable for FM radio, headset, and other analog sources without an ADC.

Microphone Bias

The MICB pin is the microphone bias source for an external microphone. MICB can provide 2 mA (typical) of bias current.

= 3.6 V, volume = 6 dB) into an 8- Ω load. The digital speaker amplifier offers

Digital Gain Control

A portable application with small speakers may be require a high sound level when playing back audio data recorded at low level. Digital gain control (DGC) can be used to amplify the digital input data by 0, 6, 12 or 18 dB by setting register 70 (SPX[1:0]).

Automatic Level Control (ALC) for Recording

The sound for microphone recording should be expanded to a suitable level without saturation. The digitally controlled automatic level control (ALC) provides automatic expansion for small input signals and compression for large input signals while recording. The expansion level, compression level, attack time, and recovery time can be selected by register 83. The register 83 description explains the details of these settings.

3-D Sound

A 3-D sound effect is provided by mixing L-channel and R-channel data with a band-pass filter with two parameters, mixing ratio and band pass filter characteristic, that can be controlled by register 95 (3DP[3:0], 3FLO). The 3-D sound effect uses the DAC digital input or ADC digital output selected by register 95 (SDAS).

Three-Band Tone Control

Tone control has bass, midrange, and treble controls that can be adjusted from 12 dB to –12 dB in 1-dB steps by registers 92 to 94 (LGA[4:0], MGA[4:0] and HGA[4:0]). Register 92 (LPAE) attenuates the digital input signal automatically to prevent clipping of the output signal at settings above 0 dB for bass control. LPAE has no effect on midrange and treble controls.

High-Pass Filter and Two-Stage Programmable Notch Filter

The high-pass filter eliminates the dc offset of the ADC analog signal and can be set for a cutoff frequency of 4 Hz, 120 Hz, or 240 Hz at the 48-kHz sampling frequency by register 81 (HPF[1:0]). A register 95 (SDAS) selection applies the filter to either the DAC digital input or the ADC digital output.

Notch filters are provided to remove noise of a particular frequency, such as CCD noise, motor noise, or other mechanical noise in a particualr application. The PCM3793A/94A has two notch filters for which the center frequency and frequency bandwidth can be programmed by registers 96 to 104. A register 95 (SDAS) selection applies the filter to either the DAC digital input or the ADC digital output.

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PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

Digital Monaural Mixing

The audio data can be converted from stereo digital data to mixed monaural digital data. The conversion occurs in the internal audio interface section and is controlled by register 96 (MXEN).

Zero-Cross Detection

Zero-cross detection minimizes audible zipper noise while changing analog volume and digital attenuation. This function applies to the digital input or digital output as defined by register 86 (ZCRS).

Short Protection

The short-circuit protection on each headphone output prevents damage to the device while an output is shorted to V

, an output is shorted to PGND, or any two outputs are shorted together. When the short circuit is detected

on the outputs, the PCM3793A/94A powers down the shorted amplifier immediately. The short-protection status can be monitored by reading register 77 (STHC, STHL, SCHR) through the I2C interface. Short-circuit protection operates in any enabled headphone amplifier.

Thermal Protection

The thermal protection on the speaker amplifier prevents damage to the device when the internal die temperature exceeds approximately 150 ° C. Once the die temperature exceeds the thermal set point, all analog outputs are powered down. This status can be reset by setting register 76 (RLSR, RLSL) and can be watched by reading register 77 (STSR, STSL) through the two-wire (I2C) interface. Thermal protection operates in any enabled speaker amplifier.

Pop-Noise Reduction Circuit

The pop-noise reduction circuit prevents audible noise when turning the power supply on/off and powering the device up/down in portable applications. It is recommended to establish the register settings in the sequence that is shown in Table 3 and Table 4 . No particular external parts are required.

Power Up/Down for Each Module

Using register 72 (PMXL, PMXR), register 73 (PBIS, PDAR, PDAL, PHPC, PHPR, PHPL, PSPR, PSPL), register 82 (PAIR, PAIL, PADS, PMCB, PADR, PADL), and register 90 (PCOM), unused modules can be powered down to minimize power consumption (7 mW during playback only and 13 mW when recording only).

Digital Audio Interface

The PCM3793A/94A can receive I2S, right-justified, left-justified, and DSP formats in both master and slave modes. These options can be selected in register 70 (PFM[1:0]), register 81 (RFM[1:0]) and register 84 (MSTR).

Digital Interface

All digital I/O pins can interface at various power supply voltages. V

pin can be connected to a 1.71-V to 3.6-V

power supply.

Power Supply

The V The V these pins (for example, V

pin and the V

pin can be connected to 2.4 V to 3.6 V. The same voltage must be applied to both pins.

pin can be connected to 1.71 V to 3.6 V. A different voltage can be applied to each of

= 1.8 V, V

= 3.3 V).

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w(SCKH)

SCKI

w(SCKL)

0.7V

0.3V

T0005-12

PCM3793A PCM3794A

SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

DESCRIPTION OF OPERATION

System Clock Input

The PCM3793A/94A can accept clocks of various frequencies without a PLL. They are used for clocking the digital filters and automatic level control and delta-sigma modulators and are classified as common-audio and application-specific clocks. Table 2 shows frequencies of the common-audio clock and application-specific clock.

Figure 26 shows the timing requirements for system clock inputs. The sampling rate and frequency of the

system clocks are determined by the settings of register 86 (MSR[2:0]) and register 85 (NPR[5:0]). Note that the sampling rate of the application-specific clock has a little sampling error. The details are shown in Table 12 .

Table 2. System Clock Frequencies

CLOCK FREQUENCIES

Common-audio clock 11.2896, 12.288, 16.9344, 18.432 MHz

Application-specific clock 12, 13, 13.5, 24, 26, 27, 19.2, 19.68, 38.4, 39.36 MHz

PARAMETERS SYMBOL MIN UNITS

System-clock pulse duration, high t

System-clock pulse duration, low t

w(SCKH) w(SCKL)

7 ns 7 ns

Figure 26. System Clock Timing

Power-On Reset and System Reset

The power-on-reset circuit outputs a reset signal, typically at V the voltage of other power supplies (V

, V

, and V

). Internal circuits are cleared to default status, then

= 1.2 V, and this circuit does not depend on

signals are removed from all analog and digital outputs. The PCM3793A/94A does not require any power supply sequencing. Register data must be written after turning all power supplies on.

System reset is enabled by setting register 85 (SRST = 1). After the reset sequence, the register data is reset to SRST = 0 automatically. All circuits are cleared to their default status at once by the system reset. Note that the PCM3793A/94A has audible pop noise on the analog outputs when enabling SRST.

Power On/Off Sequence

To reduce audible pop noise, a sequence of register settings is required after turning all power supplies on when powering up, or before turning the power supplies off when powering down. If some modules are not required for a particular application or operation, they should be placed in the power-down state after performing the power-on sequence. The recommended power-on and power-off sequences are shown in Table 3 and Table 4 , respectively.

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SLAS529A – JANUARY 2007 – REVISED FEBRUARY 2007

Table 3. Recommended Power-On Sequence

STEP NOTE

1 – Turn on all power supplies 2 4027h Headphone amplifier L-ch volume (–6 dB) 3 4127h Headphone amplifier R-ch volume (–6 dB) 4 4227h Speaker amplifier L-ch volume (–6 dB) 5 4327h Speaker amplifier R-ch volume (–6 dB) 6 4427h Digital attenuator L-ch (–24 dB) 7 4527h Digital attenuator R-ch (–24 dB) 8 4620h DAC audio interface format (left-justified)

9 4BC0h Headphone detection enable and inverting polarity. Short and thermal detection enable 10 5102h ADC audio interface format (left-justified) 11 5A10h V 12 49E0h DAC (DAL, DAR) and analog bias power up 13 5601h Zero-cross detection enable 14 4803h Analog mixer (MXL, MXR) power up 15 5811h Analog mixer input (SW2, SW5) select 16 49FCh Headphone amplifier (HPL, HPR, HPC) power up 17 4C03h Speaker amplifier shut down release 18 4A01h V 19 523Fh Analog front end (ADL, ADR, D2S, MCB, PG1, 2, 5, 6) power up 20 5711h Analog input (MUX3, MUX4) select. Analog input (MUX1, MUX2) select 21 4F0Ch Analog input L-ch (PG3) volume (0 dB) 22 500Ch Analog input R-ch (PG4) volume (0 dB) 23 – Any settings for other devices or wait time, 450 ms 24 49FFh Speaker amplifier (SPL, SPR) power up

(1) V

should be turn on prior to or simultaneously with the other power supplies. It is recommended to set register data with the system

clock input after turning all power supplies on. (2) Any level is acceptable for volume or attenuation. Level should be resumed by register data recorded when system power off. (3) Audio interface format should be set to match the DSP or decoder being used. (4) The PCM3793A requires time for V

and the setting of register 125 PTM[1:0], RES[4:0]. The default setting is 450 ms at V (5) The PCM3794A does not require this setting because it has no speaker output.

(1)

(2)

(3)

ramp up/down time control. PG1, PG2 gain control (0 dB)

COM

power up

COM

(2)

(4) (5)

(5)

to reach the common level from GND level. The delay depends on the capacitor value for V

COM

= 4.7 µ s.

COM

PCM3793A PCM3794A

COM

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+ 48 hidden pages

BURR-BROWN PCM3793A, PCM3794A User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

PIN ASSIGNMENTS

FUNCTIONAL BLOCK DIAGRAM

TYPICAL PERFORMANCE CURVES

PCM3793A/94A DESCRIPTION

Analog Input

Gain Settings for Analog Input

A/D Converter

D/A Converter

Common Voltage

Line Output

Headphone Output

Headphone Plug Insertion Detection

Speaker Output (Class-D, PCM3793A)

Analog Mixing and Bypass

Microphone Bias

Digital Gain Control

Automatic Level Control (ALC) for Recording

3-D Sound

Three-Band Tone Control

High-Pass Filter and Two-Stage Programmable Notch Filter

Digital Monaural Mixing

Zero-Cross Detection

Short Protection

Thermal Protection

Pop-Noise Reduction Circuit

Power Up/Down for Each Module

Digital Audio Interface

Digital Interface

Power Supply

DESCRIPTION OF OPERATION

System Clock Input

Power-On Reset and System Reset

Power On/Off Sequence