BURR-BROWN PCM3500 User Manual

®

For most current data sheet and other product

information, visit www.burr-brown.com

Low Voltage, Low Power, 16-Bit, Mono

PCM3500

PCM3500

VOICE/MODEM CODEC

TM

FEATURES

● 16-BIT DELTA-SIGMA DAC AND ADC

● DESIGNED FOR MODEM ANALOG FRONT END:

Supports up to 56kbps Operation

● ANALOG PERFORMANCE:

Sampling Frequency: 7.2kHz to 26kHz
Dynamic Range: 88dB (typ) at fS = 8kHz, fIN = 1kHz

● SYSTEM CLOCK: 512f

S

● MASTER OR SLAVE OPERATION

● ON-CHIP CRYSTAL OSCILLATOR CIRCUIT

● ADC-TO-DAC LOOP-BACK MODE

● TIME SLOT MODE SUPPORTS UP TO

FOUR CODECs ON A SINGLE SERIAL
INTERFACE

● POWER-DOWN MODE: 60µA (typ)

DESCRIPTION

The PCM3500 is a low cost, 16-bit CODEC designed
for modem Analog Front End (AFE) and speech pro­cessing applications. The PCM3500’s low power op­eration from +2.7V to +3.6V power supplies, along
with an integrated power-down mode, make it ideal for
portable applications.

The PCM3500 integrates all of the functions needed for
a modem or voice CODEC, including delta-sigma

● POWER SUPPLY: Single +2.7V to +3.6V

● SMALL PACKAGE: SSOP-24

APPLICATIONS

● SOFTWARE MODEMS FOR:

Personal Digital Assistant
Notebook and Hand-Held PCs
Set-Top Box
Digital Television
Embedded Systems

● PORTABLE VOICE RECORDER/PLAYER

● SPEECH RECOGNITION/SYNTHESIS

● TELECONFERENCING PRODUCTS

digital-to-analog and analog-to-digital converters, in­put anti-aliasing filter, digital high-pass filter for DC
blocking, and an output low-pass filter. The synchro­nous serial interface provides for a simple, or glue-free
interface to popular DSP and RISC processors. The
serial interface also supports Time Division Multiplex­ing (TDM), allowing up to four CODECs to share a
single 4-wire serial bus.

SBAS117

V

IN

AGND

V

1

REF

V

COM

V

2

REF

V

OUT

AGND

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone]

Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

© 1999 Burr-Brown Corporation PDS-1524B Printed in U.S.A. February, 2000

AAF HPF

Reference

SMF

∆Σ

Modulator

(ADC)

Multi-Level

DAC

AGND V

V

CC

Power

DGND

Decimation

Digital Filter

Loop

Serial I/O Interface

Interpolation
Digital Filter

Mode Control

M/S

HPFD TSC

Clock
Gen/
OSC

XTIXTOLOOP

DD

∆Σ

Modulator

PDWN

1 PCM3500

FS

BCK

DIN

DOUT

FSO

SCKIO

®

SPECIFICATIONS

All specifications at +25°C, VDD = V

PARAMETER CONDITIONS MIN TYP MAX UNITS
RESOLUTION 16 Bits

DATA FORMAT

Serial Data Interface Format DSP Format
Serial Data Bit Length 16 Bits
Serial Data Format
Sampling Frequency, f

S

System Clock Frequency, 512f

DIGITAL INPUT/OUTPUT

Logic Family CMOS
Input Logic Level: V

Input Logic Current: I

Output Logic Level: V

(1)

IH

(1)

V

IL

(2)

IN

(3)

I

IN

(4)

OH

(4)

V

OL

ADC CHARACTERISTICS
DC ACCURACY

Input Voltage 0.6 V
Gain Error ±2 ±5 % of FSR
Offset Error High-Pass Filter Disabled ±2 % of FSR
Input Resistance 50 kΩ

AC ACCURACY

THD+N f
Dynamic Range Without A-Weighting 82 88 dB

Signal-to-Noise Ratio Without A-Weighting 82 88 dB
Crosstalk DAC Channel Idle, 0dB Input 80 85 dB
Passband Ripple (internal HPF enabled) 0.0002f
Passband Ripple (internal HPF disabled) 0fS to 0.425f
Roll-Off at 0.00002f
Roll-Off at 0.56f

S

S

Stopband Rejection 0.58fS to f
Group Delay 18/f

DAC CHARACTERISTICS
DC ACCURACY

Output Voltage 0.6 V
Gain Error ±1 ±5 % of FSR
Offset Error High Pass Filter Disabled ±1 % of FSR
Load Resistance 10 kΩ

AC ACCURACY

THD+N f
Dynamic Range Without A-Weighted 84 92 dB
Signal-to-Noise Ratio Without A-Weighted 84 92 dB
Crosstalk ADC Channel Idle, 0dB Input 84 92 dB
Passband Ripple 0f
Group Delay 12/f

POWER SUPPLY REQUIREMENTS

Voltage Range VCC, V
Supply Current, I
Total Supply Current in Power-Down Mode V

+ I

CC

DD

Total Power Dissipation V

TEMPERATURE RANGE

Operating –25 +85 °C
Storage –55 +125 °C
Thermal Resistance,

Θ

JA

= 3.3V, fS = 8kHz, and nominal system clock (XTI) = 512fS, unless otherwise noted. Measurement band is 100Hz to 0.425fS.

CC

PCM3500E

MSB-First, Binary Two’s Complement

ADC and DAC 7.2 8 26 kHz

S

3.686 4.096 13.312 MHz

0.7 • V

DD

0.3 • V

DD

±1 µA

100 µA

I

= –1mA V

OUT

I

= +1mA 0.3 VDC

OUT

= 1kHz, VIN = –0.5dB –85 –80 dB

IN

to 0.425f

S

S

S

– 0.3 VDC

DD

CC

±0.05 dB
±0.05 dB

High-Pass Filter Enabled –3 dB
High-Pass Filter Enabled –30 dB

S

= 1kHz, V

IN

S

VCC = 3.3V 9 12 mA

= VDD = 3.3V, XTI Stopped 60 µA

CC

= VDD = 3.3V 30 40 mW

CC

= 0dB –90 –82 dB

OUT

to 0.425f

S

DD

2.7 3.3 3.6 VDC

–65 dB

S

CC

4m sec

±0.4 dB

S

4m sec

100 °C/W

VDC
VDC

Vp-p

Vp-p

NOTES: (1) Pins 6, 7, 8, 9, 10, 15, 17, 18, 19, 20 (M/S, TSC, BCK, FS, DIN, SCKIO, XTI, HPFD, LOOP, PDWN). (2) Pins 8, 9, 10, 15, 17 (BCK, FS, DIN, SCKIO
(Schmitt-Trigger input) XTI. (3) Pins 6, 7, 18, 19, 20 (M/S, TSC, HPFD, LOOP, PDWN; Schmitt-Trigger input with internal pull-down). (4) Pins 8, 9, 11, 12, 15,
16 (BCK, FS, DOUT, FSO, SCKIO, XTO).

®

PCM3500

2

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, +VDD, +VCC............................................................. +6.5V

Supply Voltage Differences...............................................................±0.1V

GND Voltage Differences..................................................................±0.1V

Digital Input Voltage................................................... –0.3V to V

Input Current (any pins except supply) ........................................... ±10mA

Power Dissipation .......................................................................... 300mW

Operating Temperature Range ......................................... –25°C to +85°C

Storage Temperature...................................................... –55°C to +125°C

Junction Temperature ...................................................................... 150°C

Lead Temperature (soldering, 5s).................................................. +260°C

(reflow, 10s) ................................................................................ +235°C

DD

+ 0.3V

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degrada­tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its

ELECTROSTATIC
DISCHARGE SENSITIVITY

published specifications.

PACKAGE/ORDERING INFORMATION

PACKAGE SPECIFIED

PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER

DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PCM3500E 24-Lead SSOP 338 –25°C to +85°C PCM3500E PCM3500E Rails

" " " " " PCM3500E/2K Tape and Reel

NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2,000 pieces
of “PCM3500E/2K” will get a single 2000-piece Tape and Reel.

(1)

MEDIA

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN
product for use in life support devices and/or systems.

3 PCM3500

®

PIN CONFIGURATION

Top View SSOP

PCM3500

1

V

COM

2

V

1

REF

3

V

2

REF

4

V

IN

5

AGND

6

M/S

7

TSC

8

BCK

9

FS

10

DIN

11

DOUT

12

FSO

V

AGND

V

OUT

AGND

PDWN

LOOP
HPFD

XTI

XTO

SCKIO

DGND

V

24

CC

23
22
21
20
19
18
17
16
15
14
13

DD

PIN ASSIGNMENTS

PIN NAME I/O DESCRIPTION

1V
2V
3V
4V
5 AGND — Analog Ground for the ADC Input Signal.
6 M/S IN Master/Slave Select. This pin is used to determine the operating mode for the serial interface. A logic ‘0’ on this pin selects the Slave

7 TSC IN Time Slot Mode Control. This pin is used to select the time slot operating mode. A logic ‘0’ on this pin disables Time Slot Mode. A

8 BCK I/O Bit Clock. This pin serves as the bit (or shift) clock for the serial interface. This pin is an input in Slave Mode and an output in Master

9 FS I/O Frame Sync. This pin serves as the frame synchronization clock for the serial interface. This pin is an input in Slave Mode and an

10 DIN IN Serial Data Input. This pin is used to write 16-bit data to the DAC.
11 DOUT OUT Serial Data Output. The ADC outputs 16-bit data on this pin.
12 FSO OUT Frame Sync Output. Active only when Time Slot Mode is enabled. This pin is set to a high impedance state when Time Slot mode

13 V

14 DGND — Digital Ground. Internally connected through the substrate to analog ground.
15 SCKIO I/O System Clock Input/Output. This pin is a system clock output when using the crystal oscillator or XTI as the system clock input; when

16 XTO OUT Crystal Oscillator Output.
17 XTI IN Crystal Oscillator Input or an External System Clock Input.
18 HPFD IN High-Pass Filter Disable. When this pin is set to a logic ‘1’, the HPF function in the ADC is disabled.
19 LOOP IN ADC-to-DAC Loop-Back Control. When this pin is set to logic ‘1’, the ADC data is fed to the DAC input.
20 PDWN IN Power Down and Reset Control. When this pin is logic ‘0’, Power-Down Mode is enabled. The PCM3500 is reset on the rising edge

21 AGND — Analog Ground for the DAC Output Signal.
22 V
23 AGND — Analog Ground. This is the ground for the internal analog circuitry.
24 V

NOTES: (1) Schmitt-Trigger input. (2) Schmitt-Trigger input with an internal pull-down resistor. (3) Tri-state output in Time Slot Mode.

OUT Common-Mode Voltage (0.5V

COM

1 — Decouple Pin for Reference Voltage 1 (0.99VCC). This pin should be connected to ground through a capacitor.

REF

2 — Decouple Pin for Reference Voltage 2 (0.2VCC). This pin should be connected to ground through a capacitor.

REF

IN Analog Input for the ADC.

IN

Mode. A logic ‘1’ on this pin selects the Master Mode.

logic ‘1’ on this pin enables Time Slot Mode.

(1)

Mode.

output in Master Mode.

. This pin should be connected to ground through a capacitor.

CC)

(2)

(2)

(1)

(1)

(3)

is disabled (TSC = 0).

— Digital Power Supply. Used to power the digital section of the ADC and DAC, as well as the serial interface and mode control logic.

DD

This pin is not internally connected to V

XTI is connected to ground, this pin is a system clock input.

of this signal.

OUT Analog Output from the DAC Output Filter.

OUT

— Analog Power Supply. Used to power the analog circuitry of the ADC and DAC.

CC

(2)

.

CC

(1)

(2)

(2)

®

PCM3500

4

TYPICAL PERFORMANCE CURVES
DAC SECTION

DIGITAL FILTER

INTERPOLATION FILTER FREQUENCY RESPONSE

0
–10
–20
–30
–40
–50
–60

Amplitude (dB)

–70
–80
–90

–100

0

ANALOG FILTER

1

Normalized Frequency (• f

23

4

)

S

INTERPOLATION FILTER

0.2

0.0

–0.2

–0.4

Amplitude (dB)

–0.6

–0.8

–1.0

PASSBAND RIPPLE CHARACTERISTICS

0 0.1 0.2 0.3 0.4 0.5

Normalized Frequency (• fS Hz)

OUTPUT FILTER FREQUENCY RESPONSE

0
–10
–20
–30
–40
–50
–60

Amplitude (dB)

–70
–80
–90

–100

100 1k 10k 100k 1M 10M

STOPBAND CHARACTERISTICS

Frequency (Hz)

0
–1
–2
–3
–4
–5
–6
–7

Amplitude (dB)

–8
–9

–10

OUTPUT FILTER FREQUENCY RESPONSE

PASSBAND CHARACTERISTICS

100101 1k 10k 100k

Frequency (Hz)

5 PCM3500

®

TYPICAL PERFORMANCE CURVES (Cont.)

TA = +25°C, VCC = VDD = +3.3V, fS = 8kHz, and f

= 1kHz, unless otherwise specified.

SIGNAL

DAC SECTION

DAC OUTPUT SPECTRA

0

–20

–40

–60

–80

Amplitude (dB)

–100

–120

–140

0

–20

–40

–60

THD+N (dB)

–80

–100

DAC OUTPUT SPECTRUM (–0dB, N = 8192)

12340

Frequency (kHz)

TOTAL HARMONIC DISTORTION + NOISE

vs SIGNAL NOISE

THD+N fluctuates with signal level

as harmonics are limited to second

and third components.

–84 –72 –60 –48 –36 –24 –12 0–96

Signal Level (dB)

0

–20

–40

–60

–80

Amplitude (dB)

–100

–120

–140

0

–20

–40

–60

–80

Amplitude (dB)

–100

–120

–140

DAC OUTPUT SPECTRUM (–60dB, N = 8192)

12340

Frequency (kHz)

DAC OUT-OF-BAND NOISE SPECTRUM

(BPZ, N = 2048)

8 162432 404856640

Frequency (kHz)

®

PCM3500

6

TYPICAL PERFORMANCE CURVES (Cont.)

Dynamic Range and SNR (dB)

DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO

vs TEMPERATURE

(T

A

= –25°C to +85°C)

Temperature (°C)

96

94

92

90

88

–25 0 25 50 75 100–50

Dynamic Range

SNR

Dynamic Range and SNR (dB)

DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO

vs SUPPLY VOLTAGE

(V

CC

= VDD = +2.7V to +3.6V)

Supply Voltage (V)

96

94

92

90

88

2.7 3.0 3.3 3.6 3.92.4

Dynamic Range

SNR

Dynamic Range and SNR (dB)

DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO

vs SAMPLING FREQUENCY

(f

S

= 8kHz to 26kHz)

f

S

(kHz)

96

94

92

90

88

81624320

BW = 3.4kHz

Dynamic Range

SNR

DAC SECTION

DAC CHARACTERISTICS vs TEMPERATURE, SUPPLY, AND SAMPLING FREQUENCY

TOTAL HARMONIC DISTORTION + NOISE

–88

–90

–92

THD+N at –0dB (dB)

–94

–96

–88

–90

–25 0 25 50 75 100–50

TOTAL HARMONIC DISTORTION + NOISE

vs TEMPERATURE

(T

= –25°C to +85°C)

A

Temperature (°C)

vs SUPPLY VOLTAGE

(V

= VDD = +2.7V to +3.6V)

CC

–92

THD+N at –0dB (dB)

–94

–96

–88

–90

–92

THD+N at –0dB (dB)

–94

–96

2.7 3.0 3.3 3.6 3.92.4

TOTAL HARMONIC DISTORTION + NOISE

Supply Voltage (V)

vs SAMPLING FREQUENCY

(f

= 8kHz to 26kHz)

S

81624320

f

(kHz)

S

BW = 3.4kHz

®

7 PCM3500

TYPICAL PERFORMANCE CURVES
ADC SECTION

DIGITAL FILTER

0
–20
–40
–60
–80

–100
–120

Amplitude (dB)

–140
–160
–180
–200

0.2

0.0

–0.2

–0.4

Amplitude (dB)

–0.6

–0.8

–1.0

DECIMATION FILTER FREQUENCY RESPONSE

81624320

Normalized Frequency (• f

DECIMATION FILTER

PASSBAND RIPPLE CHARACTERISTICS

0.1 0.2 0.3 0.4 0.50
Normalized Frequency (• f

S

S

Hz)

Hz)

STOPBAND ATTENUATION CHARACTERISTICS

0
–10
–20
–30
–40
–50
–60

Amplitude (dB)

–70
–80
–90

–100

0
–1
–2
–3
–4
–5
–6

Amplitude (dB)

–7
–8
–9

–10

0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55

DECIMATION FILTER

0.2 0.4 0.6 0.8 1.00
Normalized Frequency (• f

DECIMATION FILTER TRANSITION

BAND CHARACTERISTICS

–4.13dB at 0.5 • f

Normalized Frequency (• f

S

S

Hz)

Hz)

S

0
–10
–20
–30
–40
–50
–60

Amplitude (dB)

–70
–80
–90

–100

HIGH-PASS FILTER FREQUENCY RESPONSE

STOPBAND CHARACTERISTICS

0.1 0.2 0.3 0.4 0.50
Normalized Frequency (• f

®

/1000 Hz)

S

PCM3500

8

0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6

Amplitude (dB)

–0.7
–0.8
–0.9

–10

HIGH-PASS FILTER FREQUENCY RESPONSE

PASSBAND CHARACTERISTICS

12340

Normalized Frequency (• f

/1000 Hz)

S

TYPICAL PERFORMANCE CURVES (Cont.)

ANTI-ALIASING FILTER

PASSBAND CHARACTERISTICS

Frequency (Hz)

Amplitude (dB)

0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0

1k100101 10k 100k

TA = +25°C, VCC = VDD = +3.3V, fS = 8kHz, and f

= 1kHz, unless otherwise specified.

SIGNAL

ADC SECTION

ANALOG FILTER

ANTI-ALIASING FILTER

0

–5
–10
–15
–20
–25
–30

Amplitude (dB)

–35
–40
–45
–50

ADC OUTPUT SPECTRA

STOPBAND CHARACTERISTICS

1k100 10k 100k 1M 10M

Frequency (Hz)

0

–20

–40

–60

–80

Amplitude (dB)

–100

–120

–140

ADC OUTPUT SPECTRUM (–0.5dB, N = 8192)

12340

Frequency (kHz)

0

–20

–40

–60

THD+N (dB)

–80

–100

0

–20

–40

–60

–80

Amplitude (dB)

–100

–120

–140

TOTAL HARMONIC DISTORTION + NOISE

THD+N fluctuates with signal level

as harmonics are limited to second

and third components.

–84 –72 –60 –48 –36 –24 –12 0–96

vs SIGNAL NOISE

Signal Level (dB)

9 PCM3500

ADC OUTPUT SPECTRUM (–60dB, N = 8192)

12340

Frequency (kHz)

®

TYPICAL PERFORMANCE CURVES (Cont.)

TA = +25°C, VCC = VDD = +3.3V, fS = 8kHz, and f

= 1kHz, unless otherwise specified.

SIGNAL

ADC SECTION

ADC CHARACTERISTICS vs TEMPERATURE, SUPPLY AND SAMPLING FREQUENCY

TOTAL HARMONIC DISTORTION + NOISE

–84

–86

–88

THD+N at –0.5dB (dB)

–90

–92

–84

–86

–88

–25 0 25 50 75 100–50

TOTAL HARMONIC DISTORTION + NOISE

vs TEMPERATURE

(T

= –25°C to +85°C)

A

Temperature (°C)

vs SUPPLY VOLTAGE

= VDD = +2.7V to +3.6V)

(V

CC

DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO

92

90

88

86

Dynamic Range and SNR (dB)

84

92

90

88

–25 0 25 50 75 100–50

DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO

vs TEMPERATURE

(T

vs SUPPLY VOLTAGE

= VDD = +2.7V to +3.6V)

(V

CC

= –25°C to +85°C)

A

SNR

Dynamic Range

Temperature (°C)

Dynamic Range

SNR

THD+N at –0.5dB (dB)

–90

–92

–84

–86

–88

THD+N at –0.5dB (dB)

–90

–92

2.7 3.0 3.3 3.6 3.92.4

TOTAL HARMONIC DISTORTION + NOISE

Supply Voltage (V)

vs SAMPLING FREQUENCY

= 8kHz to 26kHz)

(f

S

81624320

(kHz)

f

S

BW = 3.4kHz

86

Dynamic Range and SNR (dB)

84

96

94

92

90

Dynamic Range and SNR (dB)

88

2.7 3.0 3.3 3.6 3.92.4

DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO

vs SAMPLING FREQUENCY

(f

81624320

Supply Voltage (V)

= 8kHz to 26kHz)

S

SNR

Dynamic Range

f

(kHz)

S

BW = 3.4kHz

®

PCM3500

10

I

CC

, I

DD

and I

CC

+ I

DD

(mA)

SUPPLY CURRENT vs SUPPLY VOLTAGE

Supply Voltage (V)

12

10

8

6

4

2

0

2.7 3.0 3.3 3.6 3.92.4

ICC + I

DD

ICC + I

DD

at Power Down

I

CC

I

DD

TYPICAL PERFORMANCE CURVES (Cont.)

TA = +25°C, VCC = VDD = +3.3V, fS = 8kHz, and f

SUPPLY CURRENT vs SUPPLY VOLTAGE AND SAMPLING FREQUENCY

= 1kHz, unless otherwise specified.

SIGNAL

12

10

(mA)

DD

8

+ I

CC

6

and I

DD

4

, I

CC

I

2

0

SUPPLY CURRENT vs SUPPLY VOLTAGE

ICC + I

DD

I

CC

I

DD

ICC + I

at Power Down

DD

2.7 3.0 3.3 3.6 3.92.4
Supply Voltage (V)

®

11 PCM3500

SYSTEM CLOCK AND RESET/
POWER DOWN

SYSTEM CLOCK INPUT AND OUTPUT

The PCM3500 requires a system clock for operating the
digital filters and delta-sigma data converters.

The system clock may be supplied from an external master
clock or generated using the on-chip crystal oscillator cir­cuit. Figure 1 shows the required connections for external
and crystal clock operation. The system clock must operate
at 512 times the sampling frequency, fS, with sampling
frequencies from 7.2kHz to 26kHz. This gives an effective
system clock frequency range of 3.6864MHz to 13.312MHz.

Table I shows system clock frequencies for common sam­pling frequencies.

For external clock operation, XTI (pin 17) or SCKIO (pin 15)
is driven by a master clock source. If SCKIO is used as the
system clock input, then XTI must be connected to ground.

SAMPLING FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (MHz)

8 4.096

11.025 5.6448
16 8.192

22.05 11.2896
24 12.288

TABLE I. System Clock Frequencies for Common Sam-

pling Frequencies.

For either case, XTO (pin 16) should be left open. The system
clock source should be free of noise and exhibit low phase
jitter in order to obtain optimal dynamic performance from
the PCM3500. Figure 2 shows the system clock timing
requirements associated with an external master clock.

For crystal oscillator operation, a crystal is connected be­tween XTI (pin 17) and XTO (pin 16), along with the
necessary load capacitors (10pF to 33pF per pin, as shown
in Figure 1). A fundamental-mode, parallel resonant crystal
is required.

External

Clock

SCKIO

XTI

R

XTO

PCM3500

EXTERNAL CLOCK INPUT-SCKIO

(XTO must be open)

FIGURE 1. System Clock Generation.

External

Clock

SCKIO

XTI

R

XTO

PCM3500

EXTERNAL CLOCK INPUT-XTI

(XTO must be open)

C

1

Crystal

C

2

C1, C2 = 10pF to 33pF

SCKIO

XTI

R

XTO

PCM3500

CRYSTAL RESONATOR

CONNECTION

t

"H"

XTI

or

SCKIO

"L"

t

CLKIL

System Clock Pulse Width HIGH t
System Clock Pulse Width LOW t

FIGURE 2. External System Clock Timing Requirements.

®

PCM3500

CLKIH

12

CLKIH

CLKIL

1/512f

S

20ns (min)
20ns (min)

0.7V

0.3V

DD

DD

Reset and Power Down

The PCM3500 supports power-on reset, external reset, and
power-down operations. Power-on reset is performed by
internal circuitry automatically at power up, while the exter­nal reset is initiated using the PDWN input (pin 20).

Power-on reset occurs when power and system clock are
initially applied to the PCM3500. The internal reset cir­cuitry requires that the system clock be active at power up,
with at least three system clock cycles occurring prior to
VDD = 2.2V. When VDD exceeds 2.2V, the power-on reset
comparator enables the initialization sequence, which re­quires 1024 system clock periods for completion. During
the initialization sequence, the DAC output is forced to
AGND, and the ADC output is forced to a high impedance
state. After the initialization sequence has completed, the
DAC and ADC outputs experience a delay before they
output a valid signal or data. Refer to Figures 3 and 5 for
power-on reset and post-reset delay timing.

External reset is performed by first setting PDWN = ‘0’ and
then setting PDWN = ‘1’. The LOW to HIGH transition on

2.4V

V

2.2V

DD

2.0V

Internal Reset

1024 System Clock Periods

System Clock

PDWN causes the reset initialization sequence to start.
During the initialization sequence, the DAC output is forced
to AGND, and the ADC output is forced to a high impedance
state. After the initialization sequence has completed, the
DAC and ADC outputs experience a delay before they
output a valid signal or data. Refer to Figures 4 and 5 for
external reset and post-reset delay timing.

Power-down mode is enabled by setting PDWN = ‘0’.
During power-down mode, minimum current is drawn when
the system clock is removed, resulting in 60µA (typical)
power supply current. The PDWN input includes an internal
pull-down resistor, which places the PCM3500 in power­down mode at power-up if the PDWN pin is left uncon­nected. Ideally, the PDWN input should be driven by active
logic in order to control reset and power-down operation. If
the PDWN pin is to be unused in the system application, it
should be connected to VDD to enable normal operation. By
setting PDWN = ‘1’ when exiting power-down mode, the
PCM3500 will initiate an external reset as described earlier
in this section.

Reset

Reset Removal

FIGURE 3. Power-On Reset Timing.

PDWN

Internal Reset

System Clock

FIGURE 4. External Reset Timing.

Internal Reset

or Power Down

DAC V

OUT

ADC DOUT

Reset

Power Down

GND

PWDN = LOW Pulse Width

t

= 40ns minimum

RST

t

RST

Reset

1024 System Clock Periods

Reset Removal or Power Down OFF

Ready/Operation

(2048/fS)

t

DACDLY1

V

COM

(0.5VCC)

t

(2304/fS)

ADCDLY1

High Impedance

Reset Removal

(1)

NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR with 200ms time constant) appears initially.

FIGURE 5. DAC and ADC Output for Reset and Power Down.

13 PCM3500

®

SERIAL INTERFACE

The serial interface of the PCM3500 is a 4-wire synchronous
serial port. It includes FS (pin 9), BCK (pin 8), DIN (pin 10)
and DOUT (pin 11). FS is the frame synchronization clock,
BCK is the serial bit or shift clock, DIN is the serial data input
for the DAC, and DOUT is the serial data output for the ADC.

The frame sync, FS, operates at the sampling frequency (fS).
The bit clock, BCK, operates at 16fS for normal operation.
DIN and DOUT also operate at the bit clock rate. Both FS
and BCK must be synchronous with the system clock (guar-

FS

BCK

anteed in Master Mode). Data for DIN is clocked into the
serial interface on the rising edge of BCK, while data for
DOUT is clocked out of the serial interface on the falling
edge of BCK.

Figure 6 shows the serial interface format for the PCM3500.
The serial data for DIN and DOUT must be in Binary Two’s
Complement, MSB-first format. Figures 7 and 8 show the
timing specifications for the serial interface when used in
Slave and Master Modes.

DIN

DOUT

15 14 13 12 11 210543 151413 12 11

15 14 13 12 11 210543 151413 12 11

FIGURE 6. Serial Interface Format.

FS

(input)

t

FSSU

BCK

(input)

DIN

(input)

t

DISU

DOUT

(output)

NOTES: Timing measurement reference level is (VIH/VIL)/2. RIsing and falling time is measured
from 10% to 90% of IN/OUT signal swing. Load capacitance of DOUT signal is 50pF.

t

FSW

1/f

S

16-Bit/Frame

t

FSHD

t

DIHD

t

MSBMSB LSB LSB

MSBMSB LSB LSB

FSP

t

BCKP

t

BCKH

t

BCKL

t

CKDO

210543

210543

0.5V

DD

0.5V

DD

0.5V

DD

0.5V

DD

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

BCKP

t

BCKH

t

BCKL

t

FSW

t

FSP

t

FSSU

t

FSHD

t

DISU

t

DIHD

t

CKDO

t

R

t

F

BCK Period 2400 ns
BCK Pulse Width HIGH 800 ns
BCK Pulse Width LOW 800 ns
FS Pulse Width HIGH t
FS Period 1/f
FS Set Up Time to BCK Rising Edge 60 ns
FS Hold Time to BCK Rising Edge 60 ns
DIN Set Up Time to BCK Rising Edge 60 ns
DIN Hold Time to BCK Rising Edge 60 ns
Delay Time BCK Falling Edge to DOUT 0 80 ns
Rising Time of All Signals 30 ns
Falling Time of All Signals 30 ns

FIGURE 7. Serial Interface Timing for Slave Mode.

®

PCM3500

14

BCKP

– 60 t

BCKPtBCKP

S

+ 60 ns

t

FSP

t

FSW

FS

(output)

t

CKFS

BCK

(output)

DIN

(input)

t

DISU

DOUT

(output)

NOTES: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from
10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, FS, BCK signal is 50pF.

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

BCKP

t

BCKH

t

BCKL

t

CKFS

t

FSW

t

FSP

t

DISU

t

DIHD

t

CKDO

t

R

t

F

BCK Period 2400 16000 ns
BCK Pulse Width HIGH 1200 8000 ns
BCK Pulse Width LOW 1200 8000 ns
Delay Time BCK Falling Edge to FS – 40 40 ns
FS Pulse Width HIGH t
FS Period 1/f
DIN Set Up Time to BCK Rising Edge 60 ns
DIN Hold Time to BCK Rising Edge 60 ns
Delay Time BCK Falling Edge to DOUT 0 80 ns
Rising Time of All Signals 30 ns
Falling Time of All Signals 30 ns

t

DIHD

t

BCKH

BCKP

t

BCKP

t

BCKL

– 60 t

t

CKDO

BCKPtBCKP

S

+ 60 ns

0.5V

0.5V

0.5V

0.5V

DD

DD

DD

DD

FIGURE 8. Serial Interface Timing for Master Mode.

System

Clock

Controller

PCM3500

XTI
FS
BCK
DIN
DOUT

M/S

TSC

GND
GND

Slave Mode

FIGURE 9. Slave and Master Mode Connections.

MASTER/SLAVE OPERATION

The serial interface supports both Slave and Master Mode
operation. The mode is selected by the M/S input (pin 6).
Table II shows mode and pin settings corresponding to the
M/S input selection. Figure 9 shows connections for Slave
and Master mode operation.

SERIAL

M/S (PIN 6) MODE FS (PIN) BCK (PIN 8)

0 Slave Input Input
1 Master Output Output

INTERFACE

TABLE II. Master/Slave Mode Selection.

System

Clock

Controller

PCM3500

XTI
FS
BCK
DIN
DOUT

M/S

TSC

V

DD

GND

Master Mode

Slave Mode Operation

In Slave Mode, the FS and BCK pins are inputs to the
PCM3500. Both FS and BCK should be derived from the
system clock signal (XTI or SCKIO) to ensure proper
synchronization. Slave Mode is best suited for applications
where the DSP or controller is capable of generating the FS,
BCK, and system clocks using an on-chip serial port and/or
timing generator.

Master Mode Operation

In Master Mode operation, both FS and BCK are clock
outputs generated by the PCM3500 from the system clock
input (XTI, SCKIO, or a crystal). In Master Mode, the timing
and phase relationships between system clock, FS, and BCK
are managed internally to provide optimal synchronization.

15 PCM3500

®

SYNCHRONIZATION REQUIREMENTS

The PCM3500 requires that FS and BCK be synchronous
with the system clock. Internal circuitry is included to detect
a loss of synchronization between FS and the system clock
input. If the phase relationship between FS and the system
clock varies more than ± 1.5 BCK periods, the PCM3500
will detect a loss of synchronization. Upon detection, the
DAC output is forced to 0.5VCC and the DOUT pin is forced
to a high impedance state. This occurs within one sampling
clock (FS) period of initial detection. Figure 10 shows the
loss of synchronization operation and the DAC and ADC
output delays associated with it.

TIME SLOT OPERATION

The PCM3500 serial interface supports Time Division
Multiplexing (TDM) using the Time Slot Mode. Up to four
PCM3500s may be connected on the same 4-wire serial

Synchronization

Lost

interface bus. This is useful for system applications that
require multiple modem or voice channels. Figure 11 shows
examples of Time Slot Mode connections.

Time Slot Mode defines a 64-bit long frame, composed of
four time slots. Each slot is 16 bits long and corresponds to
one of four CODECs. The FS pin on the first PCM3500
(CODEC A, Slot 0) is used as the master frame sync, and
operates at the sampling frequency, fS. The bit clock, BCK,
operates at 64fS. DIN and DOUT of each CODEC also
operate at 64fS. Figure 12 shows the operation of the Time
Slot Mode.

Time Slot operation is enabled or disabled using the TSC
input (pin 7). The state of the TSC pin is updated at power­on reset, or on the rising edge of PWDN input (if using
external reset or power-down mode). A forced reset is
required when changing from Slave to Master Mode, or visa
versa, in real time.

Resynchronization

State of

Synchronization

DAC V

ADC DOUT

NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.

Synchronous Asynchronous

within

1/f

Undefined Data

OUT

Normal

Undefined Data

Normal

S

High Impedance

V

COM

(0.5 VCC)

FIGURE 10. Loss of Synchronization Operation and Timing.

Controller

t

DACDLY2

(0.5 VCC)

PCM3500

(CODEC A, Slot 0)

FS
BCK

DIN
DOUT
FSO

Synchronous

(32/fS)

V

COM

t

ADCDLY2

SCKIO

XTI

XTO

M/S

TSC

(32/fS)

Normal

(1)

Normal

V

DD

V

DD

FIGURE 11. Time Slot Mode Connections.

®

PCM3500

To Two PCM3500s

PCM3500

(CODEC B, Slot 1)

FS
BCK

DIN
DOUT
FSO

16

SCKIO

XTI

XTO

M/S

TSC

GND
V

DD

One Frame = 1/f

, 64 Bits per Frame, 16 Bits per Slot

S

FS

BCK

FS (A)

FSO (A)

FS (B)

FSO (B)

FS (C)

FSO (C)

FS (D)

FSO (D)

DIN

DOUT (A)

DOUT (B)

CODEC A CODEC B

Slot 0, 16 Bits Slot 1, 16 Bits Slot 2, 16 Bits Slot 3, 16 Bits

MSB LSB

CODEC C CODEC D

High Impedance

High Impedance

DOUT (C)

DOUT (D)

FIGURE 12. Time Slot Mode Operation.

High ImpedanceHigh Impedance

High Impedance

17 PCM3500

®

Table III shows the TSC pin settings and corresponding
mode selections. When Time Slot Mode is enabled, FSO
(pin 12) is used as a frame sync output, which is connected
to the FS input of the next PCM3500 in the Time Slot
sequence. Figures 13 and 14 provide detailed timing for
Time Slot Mode operation.

TSC (PIN 7) TIME SLOT MODE

0 Time Slot Mode Disabled, Normal Operation
1 Time Slot Operation Enable

TABLE III. Time Slot Mode Selection.

ADC-TO-DAC LOOP BACK

The PCM3500 includes a Loop-Back Mode, which directly
feeds the ADC data to the DAC input. This mode is designed
for diagnostic testing and system adjustment. Loop-Back
Mode is enabled and disabled using the LOOP input (pin

19). Table IV shows the LOOP pin settings and correspond­ing mode selections. The serial interface continues to oper-

t

FSW

FS

(input)

BCK

(input)

DIN

(input)

DOUT

(output)

FSO

(output)

t

FSSU

t

DISU

High Impedance

t

FSHD

t

DIHD

t

HZDO

ate in Loop-Back Mode, allowing the host to read the ADC
data at the DOUT pin.

LOOP (PIN 19) LOOP-BACK MODE

0 Loop-Back Mode Disabled, Normal Operation
1 Loop-Back Mode Enabled

TABLE IV. Loop-Back Mode Selection.

HIGH-PASS FILTER

The PCM3500 includes a digital high-pass filter in the ADC
which may be used to remove the DC offset created by the
analog front-end (AFE) section. The high-pass filter response
is shown in Figure 15. The high-pass filter may be enabled or
disabled using the HPFD input (pin 18). Table V shows the
HPFD pin settings and corresponding mode selections.

HPFD (PIN 18) HIGH-PASS FILTER MODE

0 High-Pass Filter On
1 High-Pass Filter Off

TABLE V. High-Pass Filter Mode Selection.

t

FSP

0.5V

DD

t

BCKP

0.5V

DD

t

BFSO

t

BCKL

t

CKDO

t

FSOW

t

BCKH

0.5V

DD

High Impedance

0.5V

DD

t

DOHZ

0.5V

DD

NOTES: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from
10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, and FSO signal is 50pF.

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

BCKP

t

BCKH

t

BCKL

t

FSW

t

FSP

t

FSSU

t

FSHD

t

DISU

t

DIHD

t

CKDO

t

HZDO

t

DOHZ

t

FSOW

t

BFSO

t

R

t

F

BCK Period 600 ns
BCK Pulse Width HIGH 200 ns
BCK Pulse Width LOW 200 ns
FS Pulse Width HIGH t

BCKP

– 60 t

BCKPtBCKP

FS Period 1/f
FS Set Up TIme to BCK Rising Edge 60 ns
FS Hold TIme to BCK RIsing Edge 60 ns
DIN Set Up Time to BCK Rising Edge 60 ns
DIN Hold Time to BCK Rising Edge 60 ns
Delay Time BCK Falling Edge to DOUT 0 80 ns
Delay Time BCK Falling Edge to DOUT Active 20 ns
Delay Time BCK Falling Edge to DOUT Inactive 19.5 ns
FSO Pulse Width HIGH t

BCKP

– 60 t

BCKPtBCKP

Delay Time BCK Falling Edge to FSO 0 80 ns
Rising Time of All Signals 30 ns
Falling Time of All Signals 30 ns

FIGURE 13. Serial Interface Timing for Time Slot Mode Operation (Slave Mode).

®

PCM3500

18

+ 60 ns

S

+ 60 ns

t

FSP

t

FSW

FS

(output)

t

BCKP

BCK

(output)

t

BCKL

t

BCKH

DIN

(input)

t

DIHD

DOUT

t

DISU

High Impedance

(output)

t

HZDO

t

CKDO

FSO

(output)

t

BFSO

t

FSOW

NOTES: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from
10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, FSO, FS, and BCK signal is 50pF.

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

BCKP

t

BCKH

t

BCKL

t

CKFS

t

FSW

t

FSP

t

DISU

t

DIHD

t

CKDO

t

HZDO

t

DOHZ

t

FSOW

t

BFSO

t

R

t

F

BCK Period 600 4000 ns
BCK Pulse Width HIGH 300 2000 ns
BCK Pulse Width LOW 300 2000 ns
Delay Time BCK Falling Edge to FS –40 40 ns
FS Pulse Width HIGH t
FS Period 1/f

BCKP

– 60 t

BCKPtBCKP

S

+ 60 ns

DIN Set Up Time to BCK Rising Edge 60 ns
DIN Hold Time to BCK Rising Edge 60 ns
Delay Time BCK Falling Edge to DOUT 0 80 ns
Delay Time BCK Falling Edge to DOUT Active 20 ns
Delay Time BCK Falling Edge to DOUT Inactive 19.5 ns
FSO Pulse Width HIGH t

BCKP

– 60 t

BCKPtBCKP

+ 60 ns
Delay Time BCK Falling Edge to FSO 0 80 ns
Rising Time of All Signals 30 ns
Falling Time of All Signals 30 ns

0.5V

DD

t

CKFS

0.5V

DD

0.5V

DD

High Impedance

0.5V

DD

t

DOHZ

0.5V

DD

FIGURE 14. Serial Interface Timing for Time Slot Mode Operation (Master Mode).

0
–10
–20
–30
–40
–50
–60

Amplitude (dB)

–70
–80
–90

–100

HIGH-PASS FILTER FREQUENCY RESPONSE

STOPBAND CHARACTERISTICS

0.1 0.2 0.3 0.4 0.50
Normalized Frequency (• f

/1000 Hz)

S

0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6

Amplitude (dB)

–0.7
–0.8
–0.9

–10

HIGH-PASS FILTER FREQUENCY RESPONSE

PASSBAND CHARACTERISTICS

12340

Normalized Frequency (• f

FIGURE 15. High-Pass Filter Response.

19 PCM3500

/1000 Hz)

S

®

APPLICATIONS INFORMATION

BASIC CIRCUIT CONNECTIONS

The basic connection diagram for the PCM3500 is shown in
Figure 16. Included are the required power supply bypass and
reference decoupling capacitors. The DAC output, V
the ADC input, VIN, should be AC-coupled to external cir­cuitry.

Reference Pin Connections

The V

voltage is used internally to bias the input and

COM

output amplifier stages of the PCM3500. It is brought out

OUT

, and

unbuffered on pin 1 for decoupling. A 1µF to 10µF alumi­num electrolytic or tantalum capacitor is recommended for
decoupling purposes. This capacitor should be located as
close as possible to pin 1.

The V

voltage is typically equal to VCC/2, and may be

COM

used to bias external input and output circuitry. However,
since the V

pin is not a buffered output, it must drive a

COM

high impedance load to avoid excessive loading. Buffering
the V

pin with an external op amp configured as a

COM

voltage follower is recommended when driving multiple bias
nodes. Figure 17 shows examples of using V

COM

with

external circuitry.

C

3

+

C

4

+

C

5

+

Serial

Interface

+

C

6

C1, C2: Power supply bypass capacitors. Parallel combination of a 1µF to 10µF aluminum electrolytic capacitor and 0.1µF ceramic capacitor.

, C4, C5: V

C

3

C

, C7: Input/output AC-coupling capacitors. Use a 0.1µF to 10µF aluminum electrolytic capacitor.

6

REF

and V

bypass capacitors. Use a 1µF to 10µF aluminum electrolytic capacitor.

COM

1

V

2

V

3

V

4

V

5

AGND

6

M/S

7

TSC

8

BCK

9

FS

10

DIN

11

DOUT

12

FSO

PCM3500

COM

1

REF

2

REF

IN

Analog Line Interface Circuit

Telecom Line

AGND

V

AGND

PDWN

LOOP

HPFD

XTO

SCKIO

DGND

V

OUT

XTI

V

24

CC

23
22
21
20
19
18
17
16
15
14
13

DD

+

C

1

C

2

+

+3.3V

External Reset

Power-Down Control

External Clock System

+

C

7

FIGURE 16. Basic Connection Diagram.

(a) Biasing an External Active Filter Stage

Non-Polarized

PCM3500

V

OUT

V

COM

FIGURE 17. Using V

1µF

+

4.7µF

to Bias External Circuitry.

®

COM

PCM3500

V

CC

OPA343

20

(b) Using a Buffer to Provide Bias for Multiple or
Low Input Impedance Nodes

Use voltage follower

PCM3500

V

COM

+

4.7µF

to buffer V

OPA340

COM

To Bias

Nodes

V

1 (pin 2) and V

REF

2 (pin 3) are reference voltages used

REF

by the delta-sigma modulators. They are brought out strictly
for decoupling purposes. V

1 and V

REF

2 are not to be

REF

used to bias external circuits. A 1µF to 10µF aluminum
electrolytic or tantalum capacitor is recommended for
decoupling on each pin. These capacitors should be located
as close as possible to pins 2 and 3.

Power Supplies and Grounding

VCC (pin 24) and VDD (pin 13) should be connected directly
to the +2.7V to +3.6V analog power supply, as shown in
Figure 16. The AGNDs (pins 5, 21, and 23) and DGND (pin

14) should be connected directly to the analog ground.
Power supply bypass capacitors should be located as close
to the power supply pins as possible in order to ensure a low
impedance connection. A combination of a 10µF aluminum
electrolytic or tantalum capacitor in parallel with a 0.1µF
ceramic capacitor is recommended for both VCC and VDD.

VDD and VCC should not be connected to separate digital and
analog power supplies. This can lead to an SCR latch-up
condition, which can cause either degraded device perfor­mance or catastrophic failures.

PCB LAYOUT GUIDELINES

The recommended PCB layout technique is shown in Figure

18. The analog and digital section of the board are separated

by a split ground plane, with the PCM3500 positioned
entirely over the analog section of the board. The AGNDs
(pins 5, 20, and 23) and DGND (pin 14) are connected
directly to the analog ground plane. The power supply pins,
VCC (pin 13) and VDD (pin 24), are routed directly to the
+2.7V to +3.6V analog power supply using wide copper
traces (100 mils or wider recommended) or a power plane.
Power supply bypass and reference decoupling capacitors
are shown located as close as possible to the PCM3500.

The PCM3500 is oriented so that the digital pins are facing
the ground plane split. Digital connections should be made
as short and direct as possible to limit high frequency
radiation and coupling. Series resistors (from 20Ω to 100Ω)
may be put in series with the system clock, FS, BCK, and
FSO lines to reduce or eliminate overshoot on clock edges,
further reducing radiated emissions. The split ground plane
should be connected at one point by a trace, wire, or ferrite
bead. Often the board will be designed to have several
jumper points for the common ground connection, so that
the best performance can be derived through experimenta­tion.

An alternative technique, using a single power supply or
battery, is shown in Figure 19. This technique is more
suitable for portable applications.

Digital Power

Supply

+3.3V

Host

and

Logic

Digital I/Os

DIGITAL SECTION ANALOG SECTION

Common

Connection

Split Grounds

Analog Power

Supply

+3.3V

V

CCVDD

PCM3500

AGND

DGND

Analog
Ground

Digital

Ground

FIGURE 18. Recommended PCB Layout Technique.

Common

Supply

V

Host

and

Logic

Digital I/Os

DIGITAL SECTION ANALOG SECTION

Split Grounds

CC

PCM3500

AGND

Analog

Ground

V

DD

DGND

Ferrite
Beads

Digital

Ground

FIGURE 19. PCB Layout Using a Single-Supply or Battery.

21 PCM3500

®

OUTPUT FILTER CIRCUITS FOR THE DAC

The PCM3500’s DAC uses delta-sigma conversion tech­niques. It uses oversampling and noise shaping to improve
in-band (f = fS/2) signal-to-noise performance at the expense
of increased out-of-band noise. The DAC output must be
low-pass filtered to attenuate the out-of-band noise to a
reasonable level.

The PCM3500 includes a low-pass filter in the on-chip
output amplifier circuit. The frequency response for this
filter is shown in Figure 20. Although this filter helps to
lower the out-of-band noise, it is not adequate for many
applications. This is especially true for applications where
the sampling frequency is below 16kHz, since the out-of­band noise above fS/2 is in the audio spectrum. An external
filter circuit, either passive or active, is required to provide
additional attenuation of the out-of-band noise. The low­pass filter order will be dependent upon the out-of-band

noise requirements for a particular system. Generally, a 2nd­order or better low-pass circuit will be required, with the
cut-off frequency set to fS/2 or less.

Burr-Brown Application Bulletin AB-034 provides infor­mation for designing both Multiple Feedback and Sallen­Key active filter circuits using software available from Burr­Brown’s web site. Another excellent reference for both
passive and active filter design is the “Electronic Filter
Design Handbook, Third Edition” by Williams and Taylor,
published by McGraw-Hill.

ON-CHIP ANALOG FRONT END FOR THE ADC

The PCM3500 A/D converter includes a fully differential
input delta-sigma modulator. In order to simplify connection
for single-ended applications, an analog front end (AFE)
circuit has been included on the PCM3500 just prior to the
modulator. The AFE circuit is shown in Figure 21.

0
–10
–20
–30
–40
–50
–60

Amplitude (dB)

–70
–80
–90

–100

100 1k 10k 100k 1M 10M

STOPBAND FREQUENCY RESPONSE

OUTPUT FILTER

Frequency (Hz)

FIGURE 20. DAC Output Amplifier Filter Response.

1.0µF

V

+

IN

50kΩ

4

0
–1
–2
–3
–4
–5
–6
–7

Amplitude (dB)

–8
–9

–10

PASSBAND FREQUENCY RESPONSE

OUTPUT FILTER

100101 1k 10k 100k

Frequency (Hz)

(+)

V

COM

1

V

+

+

1

REF

2

2

V

REF

3

+

FIGURE 21. On-Chip AFE Circuit for the ADC.

®

PCM3500

Reference

22

(–)

Delta-Sigma

Modulator

The AFE circuit consists of a single-ended-to-differential

Host
CPU

Controls (ring detect, off hook, etc.)

Modem

Software

PCM3500

CODEC

Data

Access

Arrangement

(DAA)

Data

Tip
Ring

converter, with the first stage of the circuit doubling as a
low-pass, anti-alias filter. The frequency response for the
filter is shown in Figure 22. Since the delta-sigma modulator
oversamples the input at 64fS, the anti-alias filter require­ments are relaxed, with only a single-pole filter being re­quired. If an application requires further band limiting of the
input signal, a simple RC filter at the VIN input (pin 4) can
be used, as shown in Figure 23.

SOFTWARE MODEM
APPLICATIONS

The PCM3500 was designed to meet the requirements for
software-based analog modems, supporting up to 56kbps
In a software modem application, the PCM3500 is paired
with a Data Access Arrangement (DAA) and a host CPU to

(1)

provide the complete modem function. Figure 24 shows a
simplified block diagram of a software modem using the
PCM3500.

The DAA provides the interface between the CODEC and
two-wire telephone line. The DAA provides numerous
functions, including two-to-four wire conversion, modem­side to line-side isolation, ring detection, hook switch con­trol, line current compensation, and overvoltage protection.

The host CPU provides the data pump and supervisory
functions for the software modem application. The host
executes modem software code, which includes the neces­sary routines for transmit and receive functions, error detec­tion and correction, echo cancellation, and CODEC/DAA
control and supervision.

NOTE: (1) Data transmission is limited to 53kbps over standard telephone

.

lines. Actual transmission rates vary depending upon the quality of the
lines and switching equipment for a given connection.

ANTI-ALIASING FILTER

0

–5
–10
–15
–20
–25
–30
–35

Amplitude (dB)

–40
–45
–50

STOPBAND CHARACTERISTICS

1k100 10k 100k 1M 10M

Frequency (Hz)

FIGURE 22. Anti-Alias Filter Frequency Response.

PCM3500

=

1

2π RC

R

+

V

IN

C

Analog

Input

f

–3dB

0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7

Amplitude (dB)

–0.8
–0.9
–1.0

ANTI-ALIASING FILTER

PASSBAND CHARACTERISTICS

1k100101 10k 100k

Frequency (Hz)

FIGURE 23. Optional External Low-Pass Filter for the

ADC.

FIGURE 24. Software Modem Block Diagram.

®

23 PCM3500

HLDR

LEDCT

HLDCAP

HKP

HKN

LINPWR

HLFWV

LR1

LR2

END

CEN

C1A

V

DD

V

SS

SRVCT

SRVAN

HIN

VFCAP

ONHKMC

TXAN

TXCT

C2

BIASEN

C1B

123456789

101112

2423222120191817161514

13

U1

DL207

IL388

876

5

123

4

R

5

150kΩ

R

6

150kΩ

C

1

15nF

C

1

15nF

C

3

150nF

C

4

27nF

R

2

10MΩ

D2 Bridge

R

1

✽

16.5Ω

1%

R

9

3.9Ω

R

4

356kΩ

Q

2

TN2540

SOT89

Q

1

MMBT6520

SOT23

R

3

10MΩ

C

23

✽

0.33µF

250V

R

20

✽

15kΩ

C

15

1nF

L

2

LI0805D121R

P3100BA70

✽

RV

1

L

1

LI0805D121R

D

1

CMPZDA18V

C

14

1nF

C

8

✽

15nF

C

2

150nF

C

9

470pF

C

7

68nF

C

10

470pF

IL388

U4

U3

123

4

876

5

RING

TIP

F1

F1250T

R

19

✽

2.4kΩ
1W, 2010

R

16

✽

6.8MΩ

R

18

✽

12Ω

Q

3

✽

FZT605

Q

4

✽

BC817-40

C

22

22µF, 35V

R

14

✽

0Ω

+

+

C1B

V

REF

C2

RXCT

RXAN

ONHKML

ONHKM

HIN

SRVAN

SRVCT

TXMP

V

DD

C1A

LSTAT

RNG

OFFHKL

OFFHK

RXOUT

ACREF

TXBIAS

AUDIN

AUDOUT

V

SS

LEDCT

123456789

101112

2423222120191817161514

13

U2

DM207

V

INVOUTVCOM

4

22

1

U5

PCM3500

R

10

10kΩ

R

7

25.5kΩ

R

13

✽

27kΩ

C

17

✽

4.7nF

R

14

22kΩ

RINGD

+3.3V to 7V

OH–

R

8

121kΩ

C

5

15nF

C

18

1µF

C

20

10µF

ISOLATION BARRIERISOLATION BARRIER

NOTES: All resistors are 0.1W, 5%, 0805, unless otherwise noted.

All capacitors values are 10%, unless otherwise noted.

✽ Optional components.

®

PCM3500

FIGURE 25. Modem AFE Application Circuit.

24

Software Modem AFE Application Circuit

Figure 25 shows an applications circuit which utilizes the
PCM3500 and the DAA2000 from Infineon Technologies
(Siemens) to implement a complete modem AFE. The
DAA2000 provides modem-side (DM207) and line-side
(DL207) interfaces, with optical isolation separating the
functions. The PCM3500 is connected to the modem-side of
the DAA2000. The PCM3500’s serial interface and hard­ware mode controls are connected to the host CPU.

THEORY OF OPERATION

ADC SECTION

The PCM3500 A/D converter consists of two reference
circuits, a mono single-to-differential converter, a fully dif­ferential 5th-order delta-sigma modulator, a decimation fil­ter (including digital high pass), and a serial interface circuit.
The block diagram on the front page of this data sheet
illustrates the architecture of the ADC section, Figure 21
shows the single-to-differential converter, and Figure 26
illustrates the architecture of the 5th-order delta-sigma modu­lator and transfer functions.

An internal reference circuit with three external capacitors
provides all reference voltages which are required by the
ADC, which defines the full-scale range for the converter.
The internal single-to-differential voltage converter saves
the design, space and extra parts needed for external cir­cuitry required by many delta-sigma converters. The internal
full-differential signal processing architecture provides a

wide dynamic range and excellent power supply rejection
performance. The input signal is sampled at a 64x
oversampling rate, eliminating the need for a sample-and­hold circuit, and simplifying anti-alias filtering require­ments. The 5th-order delta-sigma noise shaper consists of
five integrators which use a switched-capacitor topology, a
comparator, and a feedback loop consisting of a one-bit
DAC. The delta-sigma modulator shapes the quantization
noise, shifting it out of the audio band in the frequency
domain. The high order of the modulator enables it to
randomize the modulator outputs, reducing idle tone levels.

The 64fS one-bit data stream from the modulator is con­verted to 1fS, 16-bit data words by the decimation filter,
which also acts as a low-pass filter to remove the shaped
quantization noise. The DC components can be removed by
a high-pass filter function contained within the decimation
filter.

DAC SECTION

The delta-sigma DAC section of PCM3500 is based on a 5­level amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled input data to 5-level delta­sigma format. A block diagram of the 5-level delta-sigma
modulator is shown in Figure 27. This 5-level delta-sigma
modulator has the advantage of stability and clock jitter
sensitivity over the typical one-bit (2 level) delta-sigma
modulator. The combined oversampling rate of the delta­sigma modulator and the internal 8x interpolation filter is
64fS for a 512fS system clock. The theoretical quantization
noise performance of the 5-level delta-sigma modulator is

shown in Figure 28.

Analog In

X(z)

+
–

1st SW-CAP

Integrator

+

1-Bit
DAC

–

2nd SW-CAP

Integrator

3rd SW-CAP

Integrator

+

+

Y(z) = STF(z) • X(z) + NTF(z) • Qn(z)
Signal Transfer Function
Noise Transfer Function

FIGURE 26. Simplified 5th-Order Delta-Sigma Modulator.

H(z)

–

+

+

+

4th SW-CAP

Integrator

+

STF(z) = H(z)/[1 + H(z)]
NTF(z) = 1/[1 + H(z)]

5th SW-CAP

Integrator

+

25 PCM3500

+

+

Comparator

Qn(z)

Digital Out

Y(z)

®

In

18-Bit

+

+

8f

S

–

–1

Z

+

+

–

–1

Z

+

++

+

+

–1

Z

Out

64f

S

FIGURE 27. 5-Level Delta-Sigma Modulator Block Digram.

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

Gain (–dB)

–100
–110
–120
–130
–140
–150

0 5 10 15 20 25 30

3rd-ORDER ∆Σ MODULATOR

Frequency (kHz)

5-level Quantizer

4
3
2
1
0

FIGURE 28. Quantization Noise Spectrum.

®

PCM3500

26

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