Page 1
®
PCM1728
49%
PCM1728
FPO
24-Bit, 96kHz Sampling
TM
CMOS Delta-Sigma Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
FEATURES
● ENHANCED MULTI-LEVEL DELTA-SIGMA DAC
● SAMPLING FREQUENCY (fS): 16kHz - 96kHz
● INPUT AUDIO DATA WORD:
16-, 20-, 24-Bit
● HIGH PERFORMANCE:
THD+N: –96dB
Dynamic Range: 106dB
SNR: 106dB
Analog Output Range: 0.62 x VCC (Vp-p)
● 8x OVERSAMPLING DIGITAL FILTER:
Stop Band Attenuation: –82dB
Passband Ripple: ±0.002dB
● MULTI FUNCTIONS:
Digital De-emphasis
Soft Mute
Zero Flag
● +5V SINGLE SUPPLY OPERATION
● SMALL 28-LEAD SSOP PACKAGE
DESCRIPTION
The PCM1728 is designed for mid- to high-grade
digital audio applications which achieve 96kHz sampling rates with 24-bit audio data. PCM1728 uses a
newly developed, enhanced multi-level delta-sigma
modulator architecture that improves audio dynamic
performance and reduces jitter sensitivity in actual
applications. The internal digital filter operates at 8X
oversampling at a 96kHz sampling rate.
The PCM1728 has superior audio dynamic performance, 24-bit resolution, and 96kHz sampling, making it ideal for mid- to high-grade audio applications
such as CD, DVD, and musical instruments.
L
R
CC2
CC2
V
V
AGND2L
AGND2L
V
BCKIN
LRCIN
DIN
2
S
I
DM1
DM0
IW0
IW1
MUTE
RST
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1998 Burr-Brown Corporation PDS-1453A Printed in U.S.A. April, 1998
Serial
Input
I/F
Mode
Control
DAC
8X Oversampling
Digital Filter with
Function
Controller
I/F
SCK
XTI
Crystal/OSC
XTO CLKO V
Enhanced
Multi-level
Delta-Sigma
Modulator
DAC
Power Supply
AGND1 VDDDGND
CC1
Low-pass
Filter
Low-pass
Filter
Open Drain
OUT
EXTL
V
OUT
EXTR
ZERO
L
R
Page 2
SPECIFICATIONS
All specifications at +25°C, +VCC = +V
PARAMETER CONDITIONS MIN TYP MAX UNITS
RESOLUTION 24 Bits
DATA FORMAT
Audio Data Interface Format Standard/I2S
Data Bit Length 16/20/24 Selectable
Audio Data Format MSB-First, Two’s Binary Comp
Sampling Frequency (f
System Clock Frequency
) 16 96 kHz
S
(1)
DIGITAL INPUT/OUTPUT LOGIC LEVEL
Input Logic Level V
V
Output Logic Level (CLKO) V
CLKO PERFORMANCE
OH
V
(2)
Output Rise Time 20 ~ 80% VDD, 10pF 5.5 ns
Output Fall Time 80 ~ 20% V
Output Duty Cycle 10pF Load 37 %
DYNAMIC PERFORMANCE
(3)
THD+N V
V
Dynamic Range f
Signal-to-Noise Ratio f
Channel Separation fS = 44.1kHz 96 102 dB
DYNAMIC PERFORMANCE
(3)
THD+N V
Dynamic Range f
DC ACCURACY
Gain Error ±1.0 ±3.0 % of FSR
Gain Mismatch: Channel-to-Channel ±1.0 ±3.0 % of FSR
Bipolar Zero Error V
ANALOG OUTPUT
Output Voltage Full Scale (0dB) 0.62 V
Center Voltage 0.5 V
Load Impedance AC Load 5 kΩ
DIGITAL FILTER PERFORMANCE
Filter Characteristics
Passband ±0.002dB 0.454f
Stopband 0.546f
Passband Ripple ±0.002 dB
Stopband Attenuation Stop Band = 0.546f
Delay Time 30/f
De-emphasis Error ±0.1 dB
INTERNAL ANALOG FILTER
–3dB Bandwidth 100 kHz
Passband Response f = 20kHz –0.16 dB
POWER SUPPLY REQUIREMENTS
Voltage Range V
Supply Current: I
CC +IDD
Power Dissipation f
TEMPERATURE RANGE
Operation –25 +85 °C
Storage –55 +100 °C
NOTES: (1) Refer section of system clock. (2) External buffer is recommended. (3) Dynamic performance specs are tested with 20kHz low pass filter and THD+N
specs are tested with 30kHz LPF, 400Hz HPF, Average Mode.
= +5V, fS = 44.1kHz, and 24-bit input data, SYSCLK = 384fS, unless otherwise noted.
DD
PCM1728
256/384/512/768f
IH
IL
OL
I
= 2mA 4.5 V
OH
I
= 4mA 0.5 V
OL
, 10pF 4 ns
DD
2.0 V
S
0.8 V
(24-Bit Data)
= 0dB fS = 44.1kHz –97 –90 dB
O
= –60dB fS = 44.1kHz –42 dB
O
fS = 96kHz –94 dB
=44.1kHz EIAJ A-weighted 98 106 dB
S
f
= 96kHz A-weighted 103 dB
S
=44.1kHz EIAJ A-weighted 98 106 dB
S
f
= 96kHz A-weighted 103 dB
S
f
= 96kHz 101 dB
S
(16-Bit Data)
= 0dB fS = 44.1kHz –94 dB
O
f
= 96kHz –92 dB
S
= 44.1kHz EIAJ A-weighted 98 dB
S
fS = 96kHz A-weighted 97 dB
= 0.5VCC at Bipolar Zero ±30 ±60 mV
O
CC
CC
–3dB 0.490f
S
Stop Band = 0.567f
DD, VCC
fS = 44.1kHz 32 45 mA
f
= 96kHz 45 mA
S
= 44.1kHz 160 225 mW
S
f
= 96kHz 225 mW
S
S
S
–75 dB
–82 dB
S
4.5 5 5.5 VDC
S
S
Vp-p
V
sec
®
PCM1728
2
Page 3
LRCIN
DIN
BCKIN
CLKO
XTI
XTO
DGND
V
VCC2R
AGND2R
EXTR
NC
V
OUT
AGND1
1
2
3
4
5
6
7
8
DD
9
10
11
12
13
R
14
PCM1728E
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
I
S
DM1
DM0
MUTE
IW1
IW0
RST
ZERO
V
2L
CC
AGND2L
EXTL
NC
V
L
OUT
V
1
CC
PACKAGE INFORMATION
PRODUCT PACKAGE NUMBER
PACKAGE DRAWING
PCM1728E 28-Pin SSOP 324
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
(1)
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage ...................................................................... +6.5V
+V
to +VDD Difference ................................................................... ±0.1V
CC
Input Logic Voltage .................................................. –0.3V to (V
Input Current (except power supply)............................................... ±10mA
Power Dissipation .......................................................................... 400mW
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s)................................................. +260°C
+ 0.3V)
DD
PIN ASSIGNMENTSPIN CONFIGURATION
PIN NAME I/O DESCRIPTION
1 LRCIN IN Left and Right Clock Input. This clock is equal to
2 DIN IN Serial Audio Data Input
3 BCKIN IN Bit Clock Input for Serial Audio Data.
4 CLKO OUT Buffered Output of Oscillator. Equivalent to
5 XTI IN Oscillator Input (External Clock Input)
6 XTO OUT Oscillator Output
7 DGND — Digital Ground
8V
9V
10 AGND2R — Analog Ground
11 EXTR OUT Rch, Common Pin of Analog Output Amp
12 NC — No Connection
13 V
14 AGND1 — Analog Ground
15 V
16 V
17 NC — No Connection
18 EXTL OUT Lch, Common Pin of Analog Output Amp
19 AGND2L — Analog Ground
20 V
21 ZERO OUT Zero Data Flag
22 RST IN Reset. When this pin is LOW, the DF and
23 IW0 IN Input Format Selection
24 IW1 IN Input Format Selection
25 MUTE IN Mute Control
26 DM0 IN De-emphasis Selection 1
27 DM1 IN De-emphasis Selection 2
28 I2S IN Input Format Selection
NOTES: (1) Pins 1, 2, 3; Schmitt Trigger input. (2) Pins 22, 25, 26, 27, 28;
Schmitt Trigger input with pull-up resister. (3) Pins 23, 24; Schmitt Trigger
input with pull-down resister.
DD
2R — Analog Power +5V
CC
R OUT Rch, Analog Voltage Output of Audio Signal
OUT
1 — Analog Power +5V
CC
L OUT Lch, Analog Voltage Output of Audio Signal
OUT
2L — Analog Power +5V
CC
the sampling rate - fS.
System Clock.
— Digital Power +5V
modulators are held in reset.
(1)
(1)
(1)
(2)
(3)
(3)
(2)
(2)
(2)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
3 PCM1728
®
Page 4
TYPICAL PERFORMANCE CURVES
All specifications at +25°C, +VCC = +V
= +5V, fS = 44.1kHz, and 24-bit input data, SYSCLK = 384fS, unless otherwise noted.
DD
88
91
94
97
THD+N at F/S (dB)
100
103
32 44.1 48 96
DYNAMIC RANGE vs SAMPLING FREQUENCY
110
108
THD+N vs SAMPLING FREQUENCY
= VDD = 5V, 24-Bit)
(V
CC
256fs
384fs
Sampling Frequency f
(V
= VDD = 5V, 24-Bit)
CC
(kHz)
S
10
1
0.1
THD+N (%)
0.010
0.001
110
108
THD+N vs LEVEL
= 44.1kHz)
(f
S
16-Bit
24-Bit
–50–60 –40 –30 –20 –10 0
Amplitude (dB)
SNR vs SAMPLING FREQUENCY
(V
= VDD = 5V, 24-Bit)
CC
–20
–30
–40
–50
–60
–70
–80
–90
–100
THD+N (dB)
106
256/384f
104
S
102
Dynamic Range (A-weighted) (dB)
100
32 44.1 48 96
Sampling Frequency f
(kHz)
S
–60dB OUTPUT SPECTRUM
–60
(f = 1kHz, f
= 44.1kHz, 16-Bit Data)
S
–70
–80
–90
–100
–110
–120
Amplitude (dB)
–130
–140
–150
202468101214161820
Frequency (Hz)
106
256/384f
104
SNR (A-weighted) (dB)
102
100
32 44.1 48 96
Sampling Frequency f
S
(kHz)
S
–60dB OUTPUT SPECTRUM
–60
(f = 1kHz, f
= 44.1kHz, 24-Bit Data)
S
–70
–80
–90
–100
–110
–120
Amplitude (dB)
–130
–140
–150
202468101214161820
Frequency (Hz)
®
PCM1728
4
Page 5
TYPICAL PERFORMANCE CURVES (CONT)
0 0.1 0.2 0.3 0.4 0.5
0.003
0.002
0.001
0
–0.001
–0.002
–0.003
Amplitude (dB)
PASSBAND RIPPLE CHARACTERISTIC
Frequency (x f
S
)
0
–20
–40
–60
–80
–100
Amplitude (dB)
–120
–140
–160
0
–2
–4
–6
Level (dB)
–8
–10
0
–2
–4
–6
Level (dB)
–8
–10
0
–2
–4
–6
Level (dB)
–8
–10
OVERALL FREQUENCY CHARACTERISTIC
0 0.5 1 1.5 2 2.5 3 3.5 4
Frequency (x f
DE-EMPHASIS FREQUENCY RESPONSE (fS = 32kHz)
02468101214
Frequency (kHz)
DE-EMPHASIS FREQUENCY RESPONSE (fS = 44.1kHz)
02468101214161820
Frequency (kHz)
DE-EMPHASIS FREQUENCY RESPONSE (fS = 48kHz)
0246810121416182022
Frequency (kHz)
)
S
0.5
0.3
0.1
–0.1
Level (dB)
–0.3
–0.5
02468101214
0.5
0.3
0.1
–0.1
Level (dB)
–0.3
–0.5
02468101214161820
0.5
0.3
0.1
–0.1
Level (dB)
–0.3
–0.5
0246810121416182022
DE-EMPHASIS ERROR (fS = 32kHz)
Frequency (kHz)
DE-EMPHASIS ERROR (fS = 44.1kHz)
Frequency (kHz)
DE-EMPHASIS ERR0R (fS = 48kHz)
Frequency (kHz)
®
5 PCM1728
Page 6
SYSTEM CLOCK
The system clock for PCM1728 must be either 256fS, 384fS,
512fS or 768fS, where fS is the audio sampling frequency
(typically 32kHz, 44.1kHz, 48kHz, or 96kHz). But 768fS at
96kHz is not accepted.
The system clock can be either a crystal oscillator placed
between XTI (pin 5) and XTO (pin 6), or an external clock
input to XTI. If an external system clock is used, XTO is
open (floating). Figure 1 illustrates the typical system clock
connections.
PCM1728 has a system clock detection circuit which automatically senses if the system clock is operating at 256fS ~
768fS. The system clock should be synchronized with LRCIN
(pin 1) clock. LRCIN (left-right clock) operates at the sampling frequency fS. In the event these clocks are not synchronized, PCM1728 can compensate for the phase difference
internally. If the phase difference between left-right and
system clocks is greater than 6-bit clocks (BCKIN), the
synchronization is performed internally. While the synchronization is processing, the analog output is forced to a DC
level at bipolar zero. The synchronization typically occurs in
less than 1 cycle of LRCIN.
Externl Clock Input
4
CLKO
System Clock
(256/384/
512/768f
Crystal Resonator Oscillation
System Clock
Buffer Out
C1 C2 : 10pF ~ 30pF
Buffer
C
C
)
S
1
2
XTAL
5
6
PCM1728
4
5
6
PCM1728
XTI
XTO
CLKO
XTI
XTO
FIGURE 1. System Clock Connection.
Typical input system clock frequencies to the PCM1728 are
shown in Table I, also, external input clock timing requirements are shown in Figure 2.
t
SCKH
“H”
XTI
“L”
t
SCKL
System Clock Pulse Width High t
System Clock Pulse Width Low t
SCKIH
SCKIL
: 7ns MIN
: 7ns MIN
2.0V
0.8V
FIGURE 2. XTI Clock Timing.
DATA INTERFACE FORMATS
Digital audio data is interfaced to PCM1728 on pins 1, 2,
and 3, LRCIN (left-right clock), DIN (data input) and
BCKIN (bit clock). PCM1728 can accept both standard, I2S,
and left justified data formats.
Figure 3 illustrates acceptable input data formats. Figure 4
shows required timing specification for digital audio data.
Reset
PCM1728 has both internal power-on reset circuit and the
RST pin (pin 22), which accepts an external forced reset by
RST = LOW. For internal power on reset, initialization is
done automatically at power on VDD >2.2V (typ). During
internal reset = LOW, the output of the DAC is invalid and
the analog outputs are forced to VCC/ 2. Figure 5 illustrates
the timing of the internal power on reset.
PCM1728 accepts an external forced reset when RST = LOW.
When RST = LOW, the output of the DAC is invalid and the
analog outputs are forced to VCC/2 after internal initialization
(1024 system clocks count after RST = HIGH.) Figure 6
illustrates the timing of the RST pin.
Zero Out (pin 21)
If the input data is continuously zero for 65536 cycles of
BCK, an internal FET is switched to “ON”. The drain of the
internal FET is the zero-pin, it will enable “wired-or” with
external circuit.
SAMPLING RATE FREQUENCY (f
32kHz 8.1920 12.2880 16.3840 24.5760
44.1kHz 11.2896 16.9340 22.5792 33.8688
48kHz 12.2880 18.4320 24.5760 36.8640
96kHz 24.5760 36.8640
NOTE: (1) The internal crystal oscillator frequency cannot be larger than 24.576MHz.
) - LRCIN 256f
S
S
TABLE I. Typical System Clock Frequency.
®
PCM1728
6
SYSTEM CLOCK FREQUENCY - MHz
384f
S
(1)
512f
49.1520
S
(1)
768f
—
S
(1)
(1)
Page 7
LRCIN (pin 1)
BCKIN (pin 3)
(1) 16-Bit Right Justified
DIN (pin 2)
14 15 16 1 2 3
L_ch
14 15
1/f
S
R_ch
16
1 2 3
14 15
16
(2) 20-Bit Right Justified
DIN (pin 2)
(3) 24-Bit Right Justified
DIN (pin 2)
(4) 24-Bit Left Justified
DIN (pin 2)
LRCIN (pin 1)
BCKIN (pin 3)
2
(5) 16-Bit I
S
DIN (pin 2)
(6) 24-Bit I
2
S
DIN (pin 2)
18 19 20 1 2 3
MSB LSB
23 24 1 2 3
MSB LSB
1 2 3
MSB LSB
1 2 3
14 15
MSB LSB
1 2 3
MSB LSB
MSB LSB
L_ch
16
22 23
22 23
24
24
18 19
22 23
1/f
20
24
S
1 2 3
1 2 3
1 2 3
MSB LSB
1 2 3
MSB LSB
1 2 3
MSB LSB
MSB LSB
18 19
MSB LSB
22 23
MSB LSB
22 23
24
R_ch
14 15
16
22 23
24
20
24
21
21
FIGURE 3. Audio Data Input Formats.
LRCKIN
t
BCH
t
BCL
BCKIN
t
BCY
DIN
t
DS
BCKIN Pulse Cycle Time
BCKIN Pulse Width High
BCKIN Pulse Width Low
BCKIN Rising Edge to LRCIN Edge
LRCIN Edge to BCKIN Rising Edge
DIN Set-up Time
DIN Hold Time
FIGURE 4. Audio Data Input Timing Specification.
t
LB
t
BL
t
DH
: 100ns (min)
: t
BCY
: 50ns (min)
: t
BCH
: 50ns (min)
: t
BCL
: 30ns (min)
: t
BL
: 30ns (min)
: t
LB
: 30ns (min)
: t
DS
: 30ns (min)
: t
DH
7 PCM1728
1.4V
1.4V
1.4V
®
Page 8
V
= V
CC
DD
Internal Reset
XTI Clock
FIGURE 5. Internal Power-On Reset Timing.
RST
Internal Reset
XTI Clock
NOTE: (1) t
= 20ns min.
RST
Reset
1024 system (= XTI) clocks
(1)
t
RST
1024 system (XTI) clocks
Reset
Reset Removal
Reset Removal
FIGURE 6. External Forced Reset Timing.
FUNCTIONAL DESCRIPTION
PCM1728 has several built-in functions including digital
input data format selection, soft mute, and digital de-emphasis. These functions are hardware controlled where static
control signals are used on pin 28 (I2S), pin 27 (DM1), pin 26
(DM0), pin 25 (MUTE), pin 24 (IW1), and pin23 (IW0).
DATA FORMAL SELECTION
PCM audio data format can be selected by pin 28 (I2S), pin
24 (IW1), and pin 23 (IW0), as shown in Table II.
IW1 IW0 I2S AUDIO INTERFACE
0 0 0 16-Bit Standard, Right-Justified
0 1 0 20-Bit Standard, Right-Justified
1 0 0 24-Bit Standard, Right-Justified
1 1 0 24-Bit Left-Justified, MSB-First
0 0 1 16-Bit I
0 1 1 24-Bit I2S
1 0 1 Reserved
1 1 1 Reserved
2
S
SOFT MUTE
Soft Mute function can be controlled by MUTE (pin 25).
MUTE (Pin 25) SOFT MUTE
L Mute ON
H Mute OFF (Normal Operation)
TABLE III. Soft Mute Control.
DE-EMPHASIS CONTROL
De-emphasis control can be selected by DM1 (pin 27) and
DM0 (pin 26).
DM1 (Pin 27) DM0 (Pin 26) DE-EMPHASIS
L L OFF
L H 48kHz
H L 44.1kHz
H H 32kHz
TABLE IV. De-emphasis Control.
TABLE II. Data Format Control.
®
PCM1728
8
Page 9
THEORY OF OPERATION
The delta-sigma section of PCM1728 is based on an 8-level
amplitude quantizer and a 4th-order noise shaper. This
section converts the oversampled input data to 8-level deltasigma format.
This newly developed, “Enhanced Multi-level Delta-Sigma”
architecture achieves high-grade audio dynamic performance
and sound quality.
A block diagram of the 8-level delta-sigma modulator is
shown in Figure 7. This 8-level delta-sigma modulator has
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2-level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the internal 8-times interpolation filter is 64fS for
all system clock ratios (256/384/512/768fS).
The theoretical quantization noise performance of the
8-level delta-sigma modulator is shown in Figure 8. This
enhanced multi-level delta-sigma architecture also has advantages for input clock jitter sensitivity due to the multilevel quantizer, simulated jitter sensitivity is shown in
Figure 9.
–
+
–1
+
Z
+
FIGURE 7. 8-Level Delta-Sigma Modulator.
0
–20
–40
–60
–80
–100
Amplitude (dB)
–120
–140
–160
–180
012345678
Frequency (fS)
–1
Z
+
+
8-Level Quantizer
–1
Z
125
120
115
110
105
100
95
Dynamic Range (dB)
90
85
80
0 100 200 300 400 500 600
–1
+
Z
CLOCK JITTER
Jitter (ps)
FIGURE 8. Quantization Noise Spectrum.
FIGURE 9. Jitter Sensitivity.
®
9 PCM1728
Page 10
APPLICATION
CONSIDERATIONS
1
DELAY TIME
There is a finite delay time in delta-sigma converters. In A/D
converters, this is commonly referred to as latency. For a
delta-sigma D/A converter, delay time is determined by the
order number of the FIR filter stage, and the chosen sampling
rate. The following equation expresses the delay time of
PCM1728:
TD = 30 x 1/f
S
For fS = 44.1kHz, TD = 30/44.1kHz = 680µs
Applications using data from a disc or tape source, such as
CD audio, DVD audio, Video CD, DAT, Minidisc, etc.,
generally are not affected by delay time. For some professional applications such as broadcast audio for studios, it is
important for total delay time to be less than 2ms.
OUTPUT FILTERING
For testing purposes all dynamic tests are done on the
PCM1728 using a 20kHz low pass filter. This filter limits
the measured bandwidth for THD+N, etc. to 20kHz. Failure
to use such a filter will result in higher THD+N and lower
SNR and Dynamic Range readings than are found in the
specifications. The low pass filter removes out of band
noise. Although it is not audible, it may affect dynamic
specification numbers.
The performance of the internal low pass filter from DC to
40kHz is shown in Figure 10. The higher frequency roll-off
of the filter is shown in Figure 11. If the user’s application
has the PCM1728 driving a wideband amplifier, it is recommended to use an external low pass filter.
0.5
0
Level (dB)
–0.5
–1
1 10 100 1k 10k 100k
Log Frequency (Hz)
FIGURE 10. Low Pass Filter Response.
20
0
–20
–40
Level (dB)
–60
–80
–100
1 10 100 1k 10k 100k 10M1M
Log Frequency (Hz)
FIGURE 11. Low Pass Filter Response.
BYPASSING POWER SUPPLIES
The power supplies should be bypassed as close as possible
to the unit. Refer to Figure 12 for optimal values of bypass
capacitors.
®
PCM1728
POWER SUPPLY
CONNECTIONS
PCM1728 has four power supply pin for digital (VDD), and
analog (VCC). Each connection also has a separate ground. If
the power supplies turn on at different times, there is a
possibility of a latch-up condition. To avoid this condition,
it is recommended to have a common connection between
the digital and analog power supplies. If separate supplies
are used without a common connection, the delta between
the two supplies during ramp-up time must be less than
0.1V.
10
Page 11
PCM
Audio Data
Input
XTI Buffer Out
System Clock
(256/384/512/768f
To DGND of Digital Source
Low-Pass
)
S
Post
Filter
LRCIN
1
DIN
2
BCKIN
3
CLKO
4
XTI
5
XTO
6
DGND
7
2
4
V
8
DD
9
VCC2R
10
AGND2R
11
EXTR
+
12
NC
13
V
R
OUT
14
AGND1
C
10µF
C
C
6
C1, C2 : 10µF + 0.1µF Ceramic
C
, C4 : 1µF ~ 10µF
3
PCM1728E
IIS
DM1
DM0
MUTE
IW1
IW0
RST
ZERO
V
CC
AGND2L
EXTL
NC
V
OUT
V
CC
28
27
26
25
Mode
Control
24
23
22
21
20
2L
19
18
+
17
16
L
15
1
C
C
10µF
C
3
5
1
External Reset
10kΩ
+5V V
CC
Post
Low-Pass
Filter
Analog
Mute
Rch Audio Out
FIGURE 12. Typical Circuit Connection Diagram.
Analog
Mute
Lch Audio Out
External
Mute Control
11 PCM1728
®
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