BURR-BROWN PCM1609A User Manual
查询PCI4510A供应商
24-Bit, 192-kHz Sampling, 8-Channel, Enhanced Multilevel,
PCM1609A
SLES145 – AUGUST 2005
Delta-Sigma Digital-to-Analog Converter
FEATURES
• 5-V Tolerant Digital Logic Inputs
• 24-Bit Resolution • Package: LQFP-48
• Analog Performance:
– Dynamic Range: 105 dB, Typical
– SNR: 105 dB, Typical
– THD+N: 0.002%, Typical
– Full-Scale Output: 3.1 Vp-p, Typical
• 4 × /8 × Oversampling Interpolation Filter:
– Stop-Band Attenuation: –55 dB
– Pass-Band Ripple: ± 0.03 dB
APPLICATIONS
• Integrated A/V Receivers
• DVD Movie and Audio Players
• HDTV Receivers
• Car Audio Systems
• DVD Add-On Cards for High-End PCs
• Digital Audio Workstations
• Other Multichannel Audio Systems
• Sampling Frequency: 5 kHz to 100 kHz
• Accepts 16-, 18-, 20-, and 24-Bit Audio Data
• Data Formats: Standard, I2S, and
Left-Justified
• System Clock: 128 fS, 192 fS, 256 fS, 384 fS,
512 fS, or 768 f
S
• User-Programmable Functions:
– Digital Attenuation: 0 dB to –63 dB,
0.5 dB/Step
– Soft Mute
– Zero Flags Can Be Used As General-
Purpose Logic Output
– Digital De-Emphasis
– Digital Filter Rolloff: Sharp or Slow
DESCRIPTION
The PCM1609A is a CMOS, monolithic integrated
circuit that features eight 24-bit audio digital-to-analog
converters (DACs) and support circuitry in a small
LQFP-48 package. The DACs use Texas Instruments'
enhanced multilevel, delta-sigma architecture that
employs fourth-order noise shaping and 8-level amplitude quantization to achieve excellent signal-to-noise
performance and a high tolerance to clock jitter.
The PCM1609A accepts industry-standard audio data
formats with 16- to 24-bit audio data. Sampling rates
up to 200 kHz are supported. A full set of
user-programmable functions is accessible through a
4-wire serial control port that supports register write
and read functions.
• Dual-Supply Operation:
– 5-V Analog
– 3.3-V Digital
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FilterPro is a trademark of Texas Instruments.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
www.ti.com
PCM1609A
SLES145 – AUGUST 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
V
DD
V
CC
VCC, V
DD
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Power supply voltage
Supply voltage difference V
Ground voltage differences ± 0.1 V
Digital input voltage –0.3 V to 6.5 V
Input current (except power supply pins) ± 10 mA
Operating temperature under bias –40 ° C to 125 ° C
Storage temperature –55 ° C to 150 ° C
Junction temperature 150 ° C
Lead temperature (soldering) 260 ° C, 5 s
Package temperature (reflow, peak) 260 ° C
–0.3 V to 4 V
–0.3 V to 6.5 V
– V
CC
DD
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range
MIN NOM MAX UNIT
Digital supply voltage, V
Analog supply voltage, V
Digital input logic family TTL
Digital input clock frequency
Analog output load resistance 5 k Ω
Analog output load capacitance 50 pF
Digital output load capacitance 20 pF
Operating free-air temperature, T
DD
CC
System clock 8.192 36.864 MHz
Sampling clock 32 192 kHz
A
3 3.3 3.6 V
4.5 5 5.5 V
–25 85 ° C
< 3 V
2
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PCM1609A
SLES145 – AUGUST 2005
ELECTRICAL CHARACTERISTICS
All specifications at TA= 25 ° C, V
otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION 24 Bits
DATA FORMAT
Audio data interface formats Standard, I2S, left-justified
Audio data bit length 16-, 18-, 20-, 24-bit, selectable
Audio data format MSB-first, binary 2s complement
f
S
DIGITAL INPUT/OUTPUT
V
IH
V
IL
(1)
I
IH
(1)
I
IL
(2)
I
IH
(2)
I
IL
V
OH
V
OL
DYNAMIC PERFORMANCE
THD+N Total harmonic distortion + noise
SNR Signal-to-noise ratio A-weighted, fS= 96 kHz 103 dB
DC ACCURACY
(1) Pins 31, 38, 40, 41, 45–47 (DATA4, SCKI, BCK, LRCK, DATA1, DATA2, DATA3)
(2) Pins 34–37 (MDI, MC, ML, RST)
(3) Analog performance specifications are tested using a System Two™ Cascade audio measurement system by Audio Precision™ with
(4) Conditions in 192-kHz operation are: system clock = 128 fSand oversampling rate = 64 fSin register 12.
Sampling frequency 5 200 kHz
System clock frequency
Logic family TTL-compatible
Input logic level Vdc
Input logic current µ A
Output logic level Vdc
(3) (4)
Dynamic range A-weighted, fS= 96 kHz 103 dB
Channel separation fS= 96 kHz 101 dB
Level linearity error V
Gain error ± 1 ± 6 % of FSR
Gain mismatch, channel-to-channel ± 1 ± 3 % of FSR
Bipolar zero error V
400-Hz HPF on, 30-kHz LPF on, average mode with 20-kHz bandwidth limiting. The load connected to the analog output is 5 k Ω or
larger, via capacitive loading.
CC
= 5 V, V
= 3.3 V, system clock = 384 fS(fS= 44.1 kHz), and 24-bit data, unless
DD
128 fS, 192 fS, 256 fS,
384 fS, 512 fS, 768 f
2
VIN= V
DD
VIN= 0 V –10
VIN= V
DD
65 100
VIN= 0 V –10
IOH= –4 mA 2.4
IOL= 4 mA 1
V
= 0 dB, fS= 44.1 kHz 0.002% 0.008%
OUT
V
= 0 dB, fS= 96 kHz 0.004%
OUT
V
= 0 dB, fS= 192 kHz 0.005%
OUT
V
= –60 dB, fS= 44.1 kHz 0.7%
OUT
V
= –60 dB, fS= 96 kHz 0.9%
OUT
V
= –60 dB, fS= 192 kHz 1%
OUT
EIAJ, A-weighted, fS= 44.1 kHz 98 105
A-weighted, fS= 192 kHz 102
EIAJ, A-weighted, fS= 44.1 kHz 98 105
A-weighted, fS= 192 kHz 102
fS= 44.1 kHz 94 103
fS= 192 kHz 100
= –90 dB ± 0.5 dB
OUT
= 0.5 V
OUT
at bipolar zero ± 30 ± 60 mV
CC
S
0.8
10
3
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PCM1609A
SLES145 – AUGUST 2005
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA= 25 ° C, V
otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG OUTPUT
Output voltage Full scale (–0 dB) 0.62 V
Center voltage 0.5 V
Load impedance AC load 5 k Ω
DIGITAL FILTER PERFORMANCE
Group delay time 20/f
De-emphasis error ± 0.1 dB
Filter Characteristics 1, Sharp Rolloff
Pass band ± 0.03 dB 0.454 f
Pass band –3 dB 0.487 f
Stop band 0.546 f
Pass-band ripple ± 0.03 dB
Stop-band attenuation Stop band = 0.546 f
Stop-band attenuation Stop band = 0.567 f
Filter Characteristics 2, Slow Rolloff
Pass band ± 0.5 dB 0.198 f
Pass band –3 dB 0.39 f
Stop band 0.884 f
Pass-band ripple ± 0.5 dB
Stop-band attenuation Stop band = 0.884 f
ANALOG FILTER PERFORMANCE
Frequency response dB
POWER-SUPPLY REQUIREMENTS
V
DD
V
CC
(6)
I
DD
I
CC
TEMPERATURE RANGE
T
A
θ
JA
Voltage range Vdc
Supply current mA
Power dissipation fS= 96 kHz 312 mW
Operation temperature –25 85 ° C
Thermal resistance 100 ° C/W
CC
= 5 V, V
(5)
= 3.3 V, system clock = 384 fS(fS= 44.1 kHz), and 24-bit data, unless
DD
CC
CC
S
S
S
S
–50 dB
–55 dB
S
–40 dB
f = 20 kHz –0.03
f = 44 kHz –0.2
3 3.3 3.6
4.5 5 5.5
fS= 44.1 kHz 18 25
fS= 96 kHz 40
fS= 192 kHz 40
fS= 44.1 kHz 33 46
fS= 96 kHz 36
fS= 192 kHz 36
fS= 44.1 kHz 224 313
fS= 192 kHz 312
Vp-p
Vdc
S
S
S
S
S
(5) Conditions in 192-kHz operation are: system clock = 128 fSand oversampling rate = 64 fSin register 12.
(6) SCKO is disabled.
4
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Output Amp and
Low-Pass Filter
System Clock
Manager
Enhanced
Multilevel
Delta-Sigma
Modulator
DAC
Serial
Input
I/F
Function
Control
I/F
System Clock
DAC
Output Amp and
DAC
DAC
Output Amp and
DAC
Output Amp and
DAC
Output Amp and
V
OUT
1
V
OUT
2
V
OUT
3
V
COM
V
OUT
4
V
OUT
5
V
OUT
6
Low-Pass Filter
Low-Pass Filter
Low-Pass Filter
Low-Pass Filter
Low-Pass Filter
Output Amp and
BCK
LRCK
DATA1 (1, 2)
DATA2 (3, 4)
DATA3 (5, 6)
DATA4 (7, 8)
SCKI
4× / 8×
Oversampling
Digital Filter
with
Function
Controller
DAC
Output Amp and
DAC
Output Amp and
V
OUT
7
V
OUT
8
Low-Pass Filter
Low-Pass Filter
Zero Detect Power Supply
B0033-03
ZERO1/GPO1
AGND1−6
V
CC
1−5
V
DD
DGND
SCKO
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
ZERO7
ZERO8
TEST
RST
ML
MC
MDI
MDO
FUNCTIONAL BLOCK DIAGRAM
PCM1609A
SLES145 – AUGUST 2005
5
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37
VCC3
AGND3
VCC4
AGND4
V
OUT
8
AGND6
VCC5
AGND5
V
OUT
7
V
COM
V
OUT
1
V
OUT
2
25
24
RST
SCKI
SCKO
BCK
LRCK
TEST
V
DD
DGND
DATA1
DATA2
DATA3
ZEROA
38 23
39 22
40 21
41 20
42 19
43 18
44 17
45 16
46 15
47 14
48 13
12
26
11
27
10
28
9298307316325
33
4343352361
PT PACKAGE
(TOP VIEW)
ZERO1/GPO1
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
NC
NC
V
OUT
6
V
OUT
5
V
OUT
4
V
OUT
3
ML
MC
MDI
MDO
ZERO8
DATA4
ZERO7NCV
CC
1
AGND1
V
CC
2
AGND2
P0028-03
PCM1609A
PCM1609A
SLES145 – AUGUST 2005
TERMINAL FUNCTIONS
TERMINAL
NAME NO.
AGND1 27 – Analog ground
AGND2 25 – Analog ground
AGND3 23 – Analog ground
AGND4 21 – Analog ground
AGND5 17 – Analog ground
AGND6 19 – Analog ground
BCK 40 I Shift clock input for serial audio data. Clock must be one of 32 fS, 48 fS, or 64 fS.
DATA1 45 I Serial audio data input for V
DATA2 46 I Serial audio data input for V
DATA3 47 I Serial audio data input for V
DATA4 31 I Serial audio data input for V
DGND 44 – Digital ground
LRCK 41 I Left and right clock input. This clock is equal to the sampling rate, fS.
MC 35 I Shift clock for serial control port
MDI 34 I Serial data input for serial control port
MDO 33 O Serial data output for serial control port
(1) Schmitt-trigger input, 5-V tolerant
(2) Schmitt-trigger input with internal pulldown, 5-V tolerant
(3) 3-state output
6
I/O DESCRIPTION
1 and V
OUT
3 and V
OUT
5 and V
OUT
7 and V
OUT
(1)
2
OUT
(1)
4
OUT
(1)
6
OUT
(1)
8
OUT
(2)
(2)
(3)
(1)
(1)
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PCM1609A
SLES145 – AUGUST 2005
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME NO.
ML 36 I Latch enable for serial control port
NC 7, 8, 29 – No connection
RST 37 I System reset, active-low
SCKI 38 I System clock input. Input frequency is one of 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, or 768 fS.
SCKO 39 O
TEST 42 – Test pin. This pin should be connected to DGND.
VCC1 28 – Analog power supply, 5-V
VCC2 26 – Analog power supply, 5-V
VCC3 24 – Analog power supply, 5-V
VCC4 22 – Analog power supply, 5-V
VCC5 18 – Analog power supply, 5-V
V
COM
V
DD
V
1 14 O Voltage output of audio signal corresponding to Lch on DATA1
OUT
V
2 13 O Voltage output of audio signal corresponding to Rch on DATA1
OUT
V
3 12 O Voltage output of audio signal corresponding to Lch on DATA2
OUT
V
4 11 O Voltage output of audio signal corresponding to Rch on DATA2
OUT
V
5 10 O Voltage output of audio signal corresponding to Lch on DATA3
OUT
V
6 9 O Voltage output of audio signal corresponding to Rch on DATA3
OUT
V
7 16 O Voltage output of audio signal corresponding to Lch on DATA4
OUT
V
8 20 O Voltage output of audio signal corresponding to Rch on DATA4
OUT
15 O Common voltage output. This pin should be bypassed with a 10- µ F capacitor to AGND.
43 – Digital power supply, 3.3-V
ZERO1/GPO1 1 O Zero-data flag for V
ZERO2/GPO2 2 O Zero-data flag for V
ZERO3/GPO3 3 O Zero-data flag for V
ZERO4/GPO4 4 O Zero-data flag for V
ZERO5/GPO5 5 O Zero-data flag for V
ZERO6/GPO6 6 O Zero-data flag for V
ZERO7 30 O Zero-data flag for V
ZERO8 32 O Zero-data flag for V
ZEROA 48 O Zero-data flag. Logical AND of ZERO1 through ZERO6
I/O DESCRIPTION
(2)
(2)
Buffered clock output. Output frequency is one of 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, or 768
fS, or one-half of 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, or 768 fS.
(2)
1. Can also be used as GPO pin.
OUT
2. Can also be used as GPO pin.
OUT
3. Can also be used as GPO pin.
OUT
4. Can also be used as GPO pin.
OUT
5. Can also be used as GPO pin.
OUT
6. Can also be used as GPO pin.
OUT
7
OUT
8
OUT
(1)
7
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Frequency [× fS]
−140
−120
−100
−80
−60
−40
−20
0
0 1 2 3 4
Amplitude − dB
G001
Frequency [× fS]
−0.05
−0.04
−0.03
−0.02
−0.01
0.00
0.01
0.02
0.03
0.04
0.05
0.0 0.1 0.2 0.3 0.4 0.5
Amplitude − dB
G002
Frequency [× fS]
−140
−120
−100
−80
−60
−40
−20
0
0 1 2 3 4
Amplitude − dB
G003
Frequency [× fS]
−5
−4
−3
−2
−1
0
1
2
3
4
5
0.0 0.1 0.2 0.3 0.4 0.5
Amplitude − dB
G004
PCM1609A
SLES145 – AUGUST 2005
All specifications at TA= 25 ° C, V
Digital Filter (De-Emphasis Off)
FREQUENCY RESPONSE (SHARP ROLLOFF) PASS-BAND FREQUENCY RESPONSE (SHARP ROLLOFF)
TYPICAL PERFORMANCE CURVES
CC
= 5 V, V
= 3.3 V, fS= 44.1 kHz, system clock = 384 fS, and 24-bit input data, unless
DD
otherwise noted
Figure 1. Figure 2.
FREQUENCY RESPONSE (SLOW ROLLOFF) TRANSITION CHARACTERISTICS (SLOW ROLLOFF)
Figure 3. Figure 4.
8
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f − Frequency − kHz
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0 2 4 6 8 10 12 14
Level − dB
G005
f − Frequency − kHz
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
0.1
0.2
0.3
0.4
0.5
0 2 4 6 8 10 12 14
Error − dB
G006
f − Frequency − kHz
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0 2 4 6 8 10 12 14 16 18 20
Level − dB
G007
f − Frequency − kHz
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
0.1
0.2
0.3
0.4
0.5
0 2 4 6 8 10 12 14 16 18 20
Error − dB
G008
f − Frequency − kHz
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0 2 4 6 8 10 12 14 16 18 20 22
Level − dB
G009
f − Frequency − kHz
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
0.1
0.2
0.3
0.4
0.5
0 2 4 6 8 10 12 14 16 18 20 22
Error − dB
G010
All specifications at TA= 25 ° C, V
Digital Filter (De-Emphasis Curves)
DE-EMPHASIS (fS= 32 kHz) DE-EMPHASIS ERROR (fS= 32 kHz)
TYPICAL PERFORMANCE CURVES (continued)
CC
= 5 V, V
= 3.3 V, fS= 44.1 kHz, system clock = 384 fS, and 24-bit input data, unless
DD
otherwise noted
PCM1609A
SLES145 – AUGUST 2005
Figure 5. Figure 6.
DE-EMPHASIS (fS= 44.1 kHz) DE-EMPHASIS ERROR (fS= 44.1 kHz)
Figure 7. Figure 8.
DE-EMPHASIS (fS= 48 kHz) DE-EMPHASIS ERROR (fS= 48 kHz)
Figure 9. Figure 10.
9
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VCC − Supply Voltage − V
96
98
100
102
104
106
108
110
4.0 4.5 5.0 5.5 6.0
Dynamic Range − dB
G012
44.1kHz, 384f
S
96kHz, 384f
S
192kHz, 128f
S
VCC − Supply Voltage − V
4.0 4.5 5.0 5.5 6.0
THD+N − Total Harmonic Distortion + Noise − %
10
0.01
0.001
0.0001
G011
0.1
1
−60dB/44.1kHz, 384f
S
0dB/44.1kHz, 384f
S
−60dB/192kHz, 128f
S
0dB/192kHz, 128f
S
0dB/96kHz, 384f
S
−60dB/96kHz, 384f
S
VCC − Supply Voltage − V
96
98
100
102
104
106
108
110
4.0 4.5 5.0 5.5 6.0
SNR − Signal-to-Noise Ratio − dB
G013
192kHz, 128f
S
96kHz, 384f
S
44.1kHz, 384f
S
VCC − Supply Voltage − V
96
98
100
102
104
106
108
110
4.0 4.5 5.0 5.5 6.0
Channel Separation − dB
G014
192kHz, 128f
S
96kHz, 384f
S
44.1kHz, 384f
S
PCM1609A
SLES145 – AUGUST 2005
TYPICAL PERFORMANCE CURVES (continued)
ANALOG DYNAMIC PERFORMANCE
All specifications at TA= 25 ° C, V
operation are system clock = 128 fS, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 fS(set by OVER
bit in register 12).
Supply-Voltage Characteristics
CC
= 5 V, V
= 3.3 V, and 24-bit input data, unless otherwise noted. Conditions in 192-kHz
DD
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE
vs vs
V
(V
= 3.3 V) V
CC
DD
Figure 11. Figure 12.
SIGNAL-TO-NOISE RATIO CHANNEL SEPARATION
vs vs
V
(V
= 3.3 V) V
CC
DD
(V
CC
CC
= 3.3 V)
DD
(V
= 3.3 V)
DD
10
Figure 13. Figure 14.
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TA − Free-Air Temperature − °C
96
98
100
102
104
106
108
110
−50 −25 0 25 50 75 100
Dynamic Range − dB
G016
192kHz, 128f
S
96kHz, 384f
S
44.1kHz, 384f
S
TA − Free-Air Temperature − °C
−50 −25 0 25 50 75 100
THD+N − Total Harmonic Distortion + Noise − %
10
0.01
0.001
0.0001
G015
0.1
1
0dB/192kHz, 128f
S
−60dB/192kHz, 128f
S
0dB/96kHz, 384f
S
−60dB/96kHz, 384f
S
−60dB/44.1kHz, 384f
S
0dB/44.1kHz, 384f
S
TA − Free-Air Temperature − °C
96
98
100
102
104
106
108
110
−50 −25 0 25 50 75 100
SNR − Signal-to-Noise Ratio − dB
G017
192kHz, 128f
S
96kHz, 384f
S
44.1kHz, 384f
S
TA − Free-Air Temperature − °C
96
98
100
102
104
106
108
110
−50 −25 0 25 50 75 100
Channel Separation − dB
G018
192kHz, 128f
S
96kHz, 384f
S
44.1kHz, 384f
S
SLES145 – AUGUST 2005
TYPICAL PERFORMANCE CURVES (continued)
ANALOG DYNAMIC PERFORMANCE (continued)
All specifications at TA= 25 ° C, V
operation are system clock = 128 fS, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 fS(set by OVER
bit in register 12).
CC
= 5 V, V
= 3.3 V, and 24-bit input data, unless otherwise noted. Conditions in 192-kHz
DD
Temperature Characteristics
PCM1609A
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE
vs vs
TEMPERATURE (TA) TEMPERATURE (TA)
Figure 15. Figure 16.
SIGNAL-TO-NOISE RATIO CHANNEL SEPARATION
vs vs
TEMPERATURE (TA) TEMPERATURE (TA)
Figure 17. Figure 18.
11
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t
w(SCKH)
System Clock
t
w(SCKL)
2 V
0.8 V
H
L
System Clock
Pulse Cycle
Time
(1)
T0005A08
PCM1609A
SLES145 – AUGUST 2005
SYSTEM CLOCK AND RESET FUNCTIONS
SYSTEM CLOCK INPUT
The PCM1609A requires a system clock for operating the digital interpolation filters and multilevel delta-sigma
modulators. The system clock is applied at the SCKI input (pin 38). Table 1 shows examples of system clock
frequencies for common audio sampling rates.
Figure 19 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. The PLL170x multiclock generator from Texas Instruments is
an excellent choice for providing the PCM1609A system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY SYSTEM CLOCK FREQUENCY (f
(kHz)
8
16
32
44.1
48
96
192 24.576 36.864
128 f
S
(1) (1)
(1) (1)
(1) (1)
(1) (1)
(1) (1)
(1) (1)
192 f
S
256 f
S
2.048 3.072 4.096 6.144
4.096 6.144 8.192 12.288
8.192 12.288 16.384 24.576
11.2896 16.9344 22.5792 33.8688
12.288 18.432 24.576 36.864
24.576 36.864 49.152
(1) (1) (1) (1)
(1) This system clock is not supported for the given sampling frequency.
384 f
) (MHz)
SCLK
S
512 f
S
768 f
S
(1)
SYMBOL PARAMETER MIN MAX UNIT
t
w(SCKH)
t
w(SCKL)
System clock pulse duration, HIGH 7 ns
System clock pulse duration, LOW 7 ns
(1) 1/128 fS, 1/256 fS, 1/384 fS, 1/512 fS, and 1/768 fS.
Figure 19. System Clock Timing
SYSTEM CLOCK OUTPUT
A buffered version of the system clock input is available at the SCKO output (pin 39). SCKO can operate at
either full (f
register 9. The SCKO output pin can also be enabled or disabled using the CLKE bit of register 9. If the SCKO
output is not required, it is recommended to disable it using the CLKE bit. The default is SCKO enabled.
12
SCKI
) or half (f
/2) rate. The SCKO output frequency can be programmed using the CLKD bit of
SCKI
www.ti.com
Reset Reset Removal
V
DD
2.4 V
2 V
1.6 V
Internal Reset
System Clock
T0014-08
0 V
Don’t Care 1024 System Clocks
Reset Removal
1024 System Clocks
RST
Internal Reset
System Clock
Reset
T0015-06
PCM1609A
SLES145 – AUGUST 2005
POWER-ON AND EXTERNAL RESET FUNCTIONS
The PCM1609A includes a power-on-reset function, as shown in Figure 20 . With the system clock active, and
V
> 2 V (typical, 1.6 V to 2.4 V), the power-on-reset function is enabled. The initialization sequence requires
DD
1024 system clocks from the time V
default state, as described in the Mode Control Registers section of this data sheet.
The PCM1609A also includes an external reset capability using the RST input (pin 37). This allows an external
controller or master reset circuit to force the PCM1609A to initialize to its reset default state. For normal
operation, RST should be set to a logic-1.
The external reset operation and timing is shown in Figure 21 . The RST pin is set to logic-0 for a minimum of
20 ns. After the initialization sequence is completed, the PCM1609A is set to its reset default state, as described
in the Mode Control Registers section of this data sheet.
During the reset period (1024 system clocks), the analog outputs are forced to the bipolar zero level (or V
After the reset period, the internal registers are initialized in the next 1/f
are provided continuously, the PCM1609A provides proper analog output with the group delay time given in the
Electrical Characteristics section of this data sheet.
The external reset is especially useful in applications where there is a delay between PCM1609A power-up and
system-clock activation. In this case, the RST pin should be held at a logic-0 level until the system clock has
been activated.
> 2 V. After the initialization period, the PCM1609A is set to its reset
DD
period and, if SCKI, BCK, and LRCK
S
/2).
CC
Figure 20. Power-On-Reset Timing
Figure 21. External Reset Timing
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