BURR-BROWN PCM1609A User Manual

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24-Bit, 192-kHz Sampling, 8-Channel, Enhanced Multilevel,

PCM1609A

SLES145 – AUGUST 2005

Delta-Sigma Digital-to-Analog Converter

FEATURES

• 5-V Tolerant Digital Logic Inputs

• 24-Bit Resolution • Package: LQFP-48

• Analog Performance:

– Dynamic Range: 105 dB, Typical – SNR: 105 dB, Typical – THD+N: 0.002%, Typical – Full-Scale Output: 3.1 Vp-p, Typical

• 4 × /8 × Oversampling Interpolation Filter:

– Stop-Band Attenuation: –55 dB – Pass-Band Ripple: ± 0.03 dB

APPLICATIONS

• Integrated A/V Receivers

• DVD Movie and Audio Players

• HDTV Receivers

• Car Audio Systems

• DVD Add-On Cards for High-End PCs

• Digital Audio Workstations

• Other Multichannel Audio Systems

• Sampling Frequency: 5 kHz to 100 kHz

• Accepts 16-, 18-, 20-, and 24-Bit Audio Data

• Data Formats: Standard, I2S, and

Left-Justified

• System Clock: 128 fS, 192 fS, 256 fS, 384 fS,

512 fS, or 768 f

• User-Programmable Functions:

– Digital Attenuation: 0 dB to –63 dB,

0.5 dB/Step – Soft Mute – Zero Flags Can Be Used As General-

Purpose Logic Output – Digital De-Emphasis – Digital Filter Rolloff: Sharp or Slow

DESCRIPTION

The PCM1609A is a CMOS, monolithic integrated circuit that features eight 24-bit audio digital-to-analog converters (DACs) and support circuitry in a small LQFP-48 package. The DACs use Texas Instruments' enhanced multilevel, delta-sigma architecture that employs fourth-order noise shaping and 8-level amplitude quantization to achieve excellent signal-to-noise performance and a high tolerance to clock jitter.

The PCM1609A accepts industry-standard audio data formats with 16- to 24-bit audio data. Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through a 4-wire serial control port that supports register write and read functions.

• Dual-Supply Operation:

– 5-V Analog – 3.3-V Digital

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FilterPro is a trademark of Texas Instruments. System Two, Audio Precision are trademarks of Audio Precision, Inc. All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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PCM1609A

SLES145 – AUGUST 2005

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

VCC, V

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Power supply voltage

Supply voltage difference V Ground voltage differences ± 0.1 V Digital input voltage –0.3 V to 6.5 V Input current (except power supply pins) ± 10 mA Operating temperature under bias –40 ° C to 125 ° C Storage temperature –55 ° C to 150 ° C Junction temperature 150 ° C Lead temperature (soldering) 260 ° C, 5 s Package temperature (reflow, peak) 260 ° C

–0.3 V to 4 V

–0.3 V to 6.5 V

– V

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range

MIN NOM MAX UNIT

Digital supply voltage, V Analog supply voltage, V Digital input logic family TTL

Digital input clock frequency

Analog output load resistance 5 k Ω Analog output load capacitance 50 pF Digital output load capacitance 20 pF Operating free-air temperature, T

System clock 8.192 36.864 MHz Sampling clock 32 192 kHz

3 3.3 3.6 V

4.5 5 5.5 V

–25 85 ° C

< 3 V

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PCM1609A

SLES145 – AUGUST 2005

ELECTRICAL CHARACTERISTICS

All specifications at TA= 25 ° C, V otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RESOLUTION 24 Bits DATA FORMAT

Audio data interface formats Standard, I2S, left-justified Audio data bit length 16-, 18-, 20-, 24-bit, selectable Audio data format MSB-first, binary 2s complement

DIGITAL INPUT/OUTPUT

(1)

(2)

DYNAMIC PERFORMANCE

THD+N Total harmonic distortion + noise

SNR Signal-to-noise ratio A-weighted, fS= 96 kHz 103 dB

DC ACCURACY

(1) Pins 31, 38, 40, 41, 45–47 (DATA4, SCKI, BCK, LRCK, DATA1, DATA2, DATA3) (2) Pins 34–37 (MDI, MC, ML, RST) (3) Analog performance specifications are tested using a System Two™ Cascade audio measurement system by Audio Precision™ with

(4) Conditions in 192-kHz operation are: system clock = 128 fSand oversampling rate = 64 fSin register 12.

Sampling frequency 5 200 kHz System clock frequency

Logic family TTL-compatible

Input logic level Vdc

Input logic current µ A

Output logic level Vdc

(3) (4)

Dynamic range A-weighted, fS= 96 kHz 103 dB

Channel separation fS= 96 kHz 101 dB

Level linearity error V

Gain error ± 1 ± 6 % of FSR Gain mismatch, channel-to-channel ± 1 ± 3 % of FSR Bipolar zero error V

400-Hz HPF on, 30-kHz LPF on, average mode with 20-kHz bandwidth limiting. The load connected to the analog output is 5 k Ω or larger, via capacitive loading.

= 5 V, V

= 3.3 V, system clock = 384 fS(fS= 44.1 kHz), and 24-bit data, unless

128 fS, 192 fS, 256 fS,

384 fS, 512 fS, 768 f

VIN= V

VIN= 0 V –10 VIN= V

65 100 VIN= 0 V –10 IOH= –4 mA 2.4 IOL= 4 mA 1

= 0 dB, fS= 44.1 kHz 0.002% 0.008%

OUT

= 0 dB, fS= 96 kHz 0.004%

OUT

= 0 dB, fS= 192 kHz 0.005%

OUT

= –60 dB, fS= 44.1 kHz 0.7%

OUT

= –60 dB, fS= 96 kHz 0.9%

OUT

= –60 dB, fS= 192 kHz 1%

OUT

EIAJ, A-weighted, fS= 44.1 kHz 98 105

A-weighted, fS= 192 kHz 102 EIAJ, A-weighted, fS= 44.1 kHz 98 105

A-weighted, fS= 192 kHz 102 fS= 44.1 kHz 94 103

fS= 192 kHz 100

= –90 dB ± 0.5 dB

OUT

= 0.5 V

OUT

at bipolar zero ± 30 ± 60 mV

0.8 10

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PCM1609A

SLES145 – AUGUST 2005

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= 25 ° C, V otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG OUTPUT

Output voltage Full scale (–0 dB) 0.62 V Center voltage 0.5 V Load impedance AC load 5 k Ω

DIGITAL FILTER PERFORMANCE

Group delay time 20/f De-emphasis error ± 0.1 dB

Filter Characteristics 1, Sharp Rolloff

Pass band ± 0.03 dB 0.454 f Pass band –3 dB 0.487 f Stop band 0.546 f Pass-band ripple ± 0.03 dB Stop-band attenuation Stop band = 0.546 f Stop-band attenuation Stop band = 0.567 f

Filter Characteristics 2, Slow Rolloff

Pass band ± 0.5 dB 0.198 f Pass band –3 dB 0.39 f Stop band 0.884 f Pass-band ripple ± 0.5 dB Stop-band attenuation Stop band = 0.884 f

ANALOG FILTER PERFORMANCE

Frequency response dB

POWER-SUPPLY REQUIREMENTS

(6)

TEMPERATURE RANGE

Voltage range Vdc

Supply current mA

Power dissipation fS= 96 kHz 312 mW

Operation temperature –25 85 ° C Thermal resistance 100 ° C/W

= 5 V, V

(5)

= 3.3 V, system clock = 384 fS(fS= 44.1 kHz), and 24-bit data, unless

CC CC

S S

–50 dB –55 dB

–40 dB

f = 20 kHz –0.03 f = 44 kHz –0.2

3 3.3 3.6

4.5 5 5.5 fS= 44.1 kHz 18 25 fS= 96 kHz 40 fS= 192 kHz 40 fS= 44.1 kHz 33 46 fS= 96 kHz 36 fS= 192 kHz 36 fS= 44.1 kHz 224 313

fS= 192 kHz 312

Vp-p

Vdc

S S

(5) Conditions in 192-kHz operation are: system clock = 128 fSand oversampling rate = 64 fSin register 12. (6) SCKO is disabled.

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Output Amp and

Low-Pass Filter

System Clock

Manager

Enhanced

Multilevel

Delta-Sigma

Modulator

DAC

Serial

Input

I/F

Function

Control

I/F

System Clock

DAC

Output Amp and

DAC

Output Amp and

DAC

Output Amp and

DAC

Output Amp and

OUT

COM

OUT

Low-Pass Filter

Output Amp and

BCK

LRCK

DATA1 (1, 2) DATA2 (3, 4) DATA3 (5, 6) DATA4 (7, 8)

SCKI

4× / 8×

Oversampling

Digital Filter

with

Function

Controller

DAC

Output Amp and

DAC

Output Amp and

OUT

Low-Pass Filter

Zero Detect Power Supply

B0033-03

ZERO1/GPO1

AGND1−6

1−5

DGND

SCKO

ZERO2/GPO2

ZERO3/GPO3

ZERO4/GPO4

ZERO5/GPO5

ZERO6/GPO6

ZERO7

ZERO8

TEST

RST

MDI

MDO

FUNCTIONAL BLOCK DIAGRAM

PCM1609A

SLES145 – AUGUST 2005

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VCC3 AGND3 VCC4 AGND4 V

OUT

8 AGND6 VCC5 AGND5 V

OUT

7 V

COM

OUT

1 V

OUT

RST

SCKI

SCKO

BCK

LRCK

TEST

DGND DATA1 DATA2 DATA3

ZEROA

38 23 39 22 40 21 41 20 42 19 43 18 44 17 45 16 46 15 47 14 48 13

9298307316325

4343352361

PT PACKAGE

(TOP VIEW)

ZERO1/GPO1

ZERO2/GPO2

ZERO3/GPO3

ZERO4/GPO4

ZERO5/GPO5

ZERO6/GPO6

OUT

MDI

MDO

ZERO8

DATA4

ZERO7NCV

AGND1

AGND2

P0028-03

PCM1609A

SLES145 – AUGUST 2005

TERMINAL FUNCTIONS

TERMINAL

NAME NO.

AGND1 27 – Analog ground AGND2 25 – Analog ground AGND3 23 – Analog ground AGND4 21 – Analog ground AGND5 17 – Analog ground AGND6 19 – Analog ground BCK 40 I Shift clock input for serial audio data. Clock must be one of 32 fS, 48 fS, or 64 fS. DATA1 45 I Serial audio data input for V DATA2 46 I Serial audio data input for V DATA3 47 I Serial audio data input for V DATA4 31 I Serial audio data input for V DGND 44 – Digital ground LRCK 41 I Left and right clock input. This clock is equal to the sampling rate, fS. MC 35 I Shift clock for serial control port MDI 34 I Serial data input for serial control port MDO 33 O Serial data output for serial control port

(1) Schmitt-trigger input, 5-V tolerant (2) Schmitt-trigger input with internal pulldown, 5-V tolerant (3) 3-state output

I/O DESCRIPTION

1 and V

OUT

3 and V

OUT

5 and V

OUT

7 and V

OUT

(1)

OUT

(1)

OUT

(1)

OUT

(1)

OUT

(2)

(3)

(1)

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PCM1609A

SLES145 – AUGUST 2005

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME NO.

ML 36 I Latch enable for serial control port NC 7, 8, 29 – No connection RST 37 I System reset, active-low SCKI 38 I System clock input. Input frequency is one of 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, or 768 fS.

SCKO 39 O TEST 42 – Test pin. This pin should be connected to DGND.

VCC1 28 – Analog power supply, 5-V VCC2 26 – Analog power supply, 5-V VCC3 24 – Analog power supply, 5-V VCC4 22 – Analog power supply, 5-V VCC5 18 – Analog power supply, 5-V V

COM

1 14 O Voltage output of audio signal corresponding to Lch on DATA1

OUT

2 13 O Voltage output of audio signal corresponding to Rch on DATA1

OUT

3 12 O Voltage output of audio signal corresponding to Lch on DATA2

OUT

4 11 O Voltage output of audio signal corresponding to Rch on DATA2

OUT

5 10 O Voltage output of audio signal corresponding to Lch on DATA3

OUT

6 9 O Voltage output of audio signal corresponding to Rch on DATA3

OUT

7 16 O Voltage output of audio signal corresponding to Lch on DATA4

OUT

8 20 O Voltage output of audio signal corresponding to Rch on DATA4

OUT

15 O Common voltage output. This pin should be bypassed with a 10- µ F capacitor to AGND. 43 – Digital power supply, 3.3-V

ZERO1/GPO1 1 O Zero-data flag for V ZERO2/GPO2 2 O Zero-data flag for V ZERO3/GPO3 3 O Zero-data flag for V ZERO4/GPO4 4 O Zero-data flag for V ZERO5/GPO5 5 O Zero-data flag for V ZERO6/GPO6 6 O Zero-data flag for V ZERO7 30 O Zero-data flag for V ZERO8 32 O Zero-data flag for V ZEROA 48 O Zero-data flag. Logical AND of ZERO1 through ZERO6

I/O DESCRIPTION

(2)

Buffered clock output. Output frequency is one of 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, or 768 fS, or one-half of 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, or 768 fS.

(2)

1. Can also be used as GPO pin.

OUT

2. Can also be used as GPO pin.

OUT

3. Can also be used as GPO pin.

OUT

4. Can also be used as GPO pin.

OUT

5. Can also be used as GPO pin.

OUT

6. Can also be used as GPO pin.

OUT

(1)

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Frequency [× fS]

−140

−120

−100

−80

−60

−40

−20

0 1 2 3 4

Amplitude − dB

G001

Frequency [× fS]

−0.05

−0.04

−0.03

−0.02

−0.01

0.00

0.01

0.02

0.03

0.04

0.05

0.0 0.1 0.2 0.3 0.4 0.5

Amplitude − dB

G002

Frequency [× fS]

−140

−120

−100

−80

−60

−40

−20

0 1 2 3 4

Amplitude − dB

G003

Frequency [× fS]

−5

−4

−3

−2

−1

0.0 0.1 0.2 0.3 0.4 0.5

Amplitude − dB

G004

PCM1609A

SLES145 – AUGUST 2005

All specifications at TA= 25 ° C, V

Digital Filter (De-Emphasis Off)

FREQUENCY RESPONSE (SHARP ROLLOFF) PASS-BAND FREQUENCY RESPONSE (SHARP ROLLOFF)

TYPICAL PERFORMANCE CURVES

= 5 V, V

= 3.3 V, fS= 44.1 kHz, system clock = 384 fS, and 24-bit input data, unless

otherwise noted

Figure 1. Figure 2.

FREQUENCY RESPONSE (SLOW ROLLOFF) TRANSITION CHARACTERISTICS (SLOW ROLLOFF)

Figure 3. Figure 4.

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f − Frequency − kHz

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

0 2 4 6 8 10 12 14

Level − dB

G005

f − Frequency − kHz

−0.5

−0.4

−0.3

−0.2

−0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 2 4 6 8 10 12 14

Error − dB

G006

f − Frequency − kHz

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

0 2 4 6 8 10 12 14 16 18 20

Level − dB

G007

f − Frequency − kHz

−0.5

−0.4

−0.3

−0.2

−0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 2 4 6 8 10 12 14 16 18 20

Error − dB

G008

f − Frequency − kHz

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

0 2 4 6 8 10 12 14 16 18 20 22

Level − dB

G009

f − Frequency − kHz

−0.5

−0.4

−0.3

−0.2

−0.1

0.0

0.1

0.2

0.3

0.4

0.5

0 2 4 6 8 10 12 14 16 18 20 22

Error − dB

G010

All specifications at TA= 25 ° C, V

Digital Filter (De-Emphasis Curves)

DE-EMPHASIS (fS= 32 kHz) DE-EMPHASIS ERROR (fS= 32 kHz)

TYPICAL PERFORMANCE CURVES (continued)

= 5 V, V

= 3.3 V, fS= 44.1 kHz, system clock = 384 fS, and 24-bit input data, unless

otherwise noted

PCM1609A

SLES145 – AUGUST 2005

Figure 5. Figure 6.

DE-EMPHASIS (fS= 44.1 kHz) DE-EMPHASIS ERROR (fS= 44.1 kHz)

Figure 7. Figure 8.

DE-EMPHASIS (fS= 48 kHz) DE-EMPHASIS ERROR (fS= 48 kHz)

Figure 9. Figure 10.

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VCC − Supply Voltage − V

100

102

104

106

108

110

4.0 4.5 5.0 5.5 6.0

Dynamic Range − dB

G012

44.1kHz, 384f

96kHz, 384f

192kHz, 128f

VCC − Supply Voltage − V

4.0 4.5 5.0 5.5 6.0

THD+N − Total Harmonic Distortion + Noise − %

0.01

0.001

0.0001

G011

0.1

−60dB/44.1kHz, 384f

0dB/44.1kHz, 384f

−60dB/192kHz, 128f

0dB/192kHz, 128f

0dB/96kHz, 384f

−60dB/96kHz, 384f

VCC − Supply Voltage − V

100

102

104

106

108

110

4.0 4.5 5.0 5.5 6.0

SNR − Signal-to-Noise Ratio − dB

G013

192kHz, 128f

96kHz, 384f

44.1kHz, 384f

VCC − Supply Voltage − V

100

102

104

106

108

110

4.0 4.5 5.0 5.5 6.0

Channel Separation − dB

G014

192kHz, 128f

96kHz, 384f

44.1kHz, 384f

PCM1609A

SLES145 – AUGUST 2005

TYPICAL PERFORMANCE CURVES (continued)

ANALOG DYNAMIC PERFORMANCE

All specifications at TA= 25 ° C, V operation are system clock = 128 fS, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 fS(set by OVER bit in register 12).

Supply-Voltage Characteristics

= 5 V, V

= 3.3 V, and 24-bit input data, unless otherwise noted. Conditions in 192-kHz

TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE

vs vs

= 3.3 V) V

Figure 11. Figure 12.

SIGNAL-TO-NOISE RATIO CHANNEL SEPARATION

vs vs

= 3.3 V) V

= 3.3 V)

Figure 13. Figure 14.

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TA − Free-Air Temperature − °C

100

102

104

106

108

110

−50 −25 0 25 50 75 100

Dynamic Range − dB

G016

192kHz, 128f

96kHz, 384f

44.1kHz, 384f

TA − Free-Air Temperature − °C

−50 −25 0 25 50 75 100

THD+N − Total Harmonic Distortion + Noise − %

0.01

0.001

0.0001

G015

0.1

0dB/192kHz, 128f

−60dB/192kHz, 128f

0dB/96kHz, 384f

−60dB/96kHz, 384f

−60dB/44.1kHz, 384f

0dB/44.1kHz, 384f

TA − Free-Air Temperature − °C

100

102

104

106

108

110

−50 −25 0 25 50 75 100

SNR − Signal-to-Noise Ratio − dB

G017

192kHz, 128f

96kHz, 384f

44.1kHz, 384f

TA − Free-Air Temperature − °C

100

102

104

106

108

110

−50 −25 0 25 50 75 100

Channel Separation − dB

G018

192kHz, 128f

96kHz, 384f

44.1kHz, 384f

SLES145 – AUGUST 2005

TYPICAL PERFORMANCE CURVES (continued)

ANALOG DYNAMIC PERFORMANCE (continued)

All specifications at TA= 25 ° C, V operation are system clock = 128 fS, DAC3 through DAC6 disabled in register 8, and oversampling rate = 64 fS(set by OVER bit in register 12).

= 5 V, V

= 3.3 V, and 24-bit input data, unless otherwise noted. Conditions in 192-kHz

Temperature Characteristics

PCM1609A

TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE

vs vs

TEMPERATURE (TA) TEMPERATURE (TA)

Figure 15. Figure 16.

SIGNAL-TO-NOISE RATIO CHANNEL SEPARATION

vs vs

TEMPERATURE (TA) TEMPERATURE (TA)

Figure 17. Figure 18.

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w(SCKH)

System Clock

w(SCKL)

2 V

0.8 V

System Clock

Pulse Cycle

Time

(1)

T0005A08

PCM1609A

SLES145 – AUGUST 2005

SYSTEM CLOCK AND RESET FUNCTIONS

SYSTEM CLOCK INPUT

The PCM1609A requires a system clock for operating the digital interpolation filters and multilevel delta-sigma modulators. The system clock is applied at the SCKI input (pin 38). Table 1 shows examples of system clock frequencies for common audio sampling rates.

Figure 19 shows the timing requirements for the system clock input. For optimal performance, it is important to

use a clock source with low phase jitter and noise. The PLL170x multiclock generator from Texas Instruments is an excellent choice for providing the PCM1609A system clock.

Table 1. System Clock Rates for Common Audio Sampling Frequencies

SAMPLING FREQUENCY SYSTEM CLOCK FREQUENCY (f

(kHz)

8 16 32

44.1 48 96

192 24.576 36.864

128 f

(1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)

192 f

256 f

2.048 3.072 4.096 6.144

4.096 6.144 8.192 12.288

8.192 12.288 16.384 24.576

11.2896 16.9344 22.5792 33.8688

12.288 18.432 24.576 36.864

24.576 36.864 49.152

(1) (1) (1) (1)

(1) This system clock is not supported for the given sampling frequency.

384 f

) (MHz)

SCLK S

512 f

768 f

(1)

SYMBOL PARAMETER MIN MAX UNIT

w(SCKH)

w(SCKL)

System clock pulse duration, HIGH 7 ns System clock pulse duration, LOW 7 ns

(1) 1/128 fS, 1/256 fS, 1/384 fS, 1/512 fS, and 1/768 fS.

Figure 19. System Clock Timing

SYSTEM CLOCK OUTPUT

A buffered version of the system clock input is available at the SCKO output (pin 39). SCKO can operate at either full (f register 9. The SCKO output pin can also be enabled or disabled using the CLKE bit of register 9. If the SCKO output is not required, it is recommended to disable it using the CLKE bit. The default is SCKO enabled.

SCKI

) or half (f

/2) rate. The SCKO output frequency can be programmed using the CLKD bit of

SCKI

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Reset Reset Removal

2.4 V 2 V

1.6 V

Internal Reset

System Clock

T0014-08

0 V

Don’t Care 1024 System Clocks

Reset Removal

1024 System Clocks

RST

Internal Reset

System Clock

Reset

T0015-06

PCM1609A

SLES145 – AUGUST 2005

POWER-ON AND EXTERNAL RESET FUNCTIONS

The PCM1609A includes a power-on-reset function, as shown in Figure 20 . With the system clock active, and V

> 2 V (typical, 1.6 V to 2.4 V), the power-on-reset function is enabled. The initialization sequence requires

1024 system clocks from the time V default state, as described in the Mode Control Registers section of this data sheet.

The PCM1609A also includes an external reset capability using the RST input (pin 37). This allows an external controller or master reset circuit to force the PCM1609A to initialize to its reset default state. For normal operation, RST should be set to a logic-1.

The external reset operation and timing is shown in Figure 21 . The RST pin is set to logic-0 for a minimum of 20 ns. After the initialization sequence is completed, the PCM1609A is set to its reset default state, as described in the Mode Control Registers section of this data sheet.

During the reset period (1024 system clocks), the analog outputs are forced to the bipolar zero level (or V After the reset period, the internal registers are initialized in the next 1/f are provided continuously, the PCM1609A provides proper analog output with the group delay time given in the Electrical Characteristics section of this data sheet.

The external reset is especially useful in applications where there is a delay between PCM1609A power-up and system-clock activation. In this case, the RST pin should be held at a logic-0 level until the system clock has been activated.

> 2 V. After the initialization period, the PCM1609A is set to its reset

period and, if SCKI, BCK, and LRCK

/2).

Figure 20. Power-On-Reset Timing

Figure 21. External Reset Timing

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PCM1609A

SLES145 – AUGUST 2005

AUDIO SERIAL INTERFACE

The audio serial interface for the PCM1609A consists of a 5-wire synchronous serial port. It includes LRCK (pin 41), BCK (pin 40), DATA1 (pin 45), DATA2 (pin 46), DATA3 (pin 47), and DATA4 (pin 31). BCK is the serial audio bit clock, and is used to clock the serial data present on DATA1, DATA2, DATA3, and DATA4 into the audio interface serial shift register. Serial data is clocked into the PCM1609A on the rising edge of BCK. LRCK is the serial audio left/right word clock. It is used to latch serial data into the serial audio interface internal registers.

Both LRCK and BCK must be synchronous to the system clock. Ideally, it is recommended that LRCK and BCK be derived from the system clock input, SCKI. LRCK is operated at the sampling frequency (fS). BCK can be operated at 32, 48, or 64 times the sampling frequency (I2S format does not support BCK = 32 fS).

Internal operation of the PCM1609A is synchronized with LRCK. Accordingly, internal operation of the device is suspended when the sampling rate clock (LRCK) is changed, or when SCKI and/or BCK is interrupted at least for a 3-bit clock cycle. If SCKI, BCK, and LRCK are provided continuously after this suspended state, the internal operation is resynchronized automatically within a period of less than 3/f and for a 3/f

time thereafter, the analog outputs are forced to the bipolar zero level, V

not required.

AUDIO DATA FORMATS AND TIMING

The PCM1609A supports industry-standard audio data formats, including standard, I2S, and left-justified (see

Figure 22 ). Data formats are selected using the format bits, FMT[2:0], in register 9. The default data format is

24-bit standard. All formats require binary 2s complement, MSB-first audio data. See Figure 23 for a detailed timing diagram of the serial audio interface.

DATA1, DATA2, DATA3, and DATA4 each carry two audio channels, designated as the left and right channels. The left-channel data always precedes the right-channel data in the serial data stream for all data formats.

Table 2 shows the mapping of the digital input data to the analog output pins.

. During this resynchronization period

/2. External resetting is

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LRCK

(2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH

MSB LSB

1/f

(= 32 fS, 48 fS, or 64 fS)

18-Bit Right-Justified

1/f

(1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW

(3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW

MSB LSB

20-Bit Right-Justified

MSB LSB

24-Bit Right-Justified

1/f

(= 48 fS, or 64 fS)

LSB

16-Bit Right-Justified, BCK = 48 fS or 64 f

16-Bit Right-Justified, BCK = 32 f

LSB

L-Channel R-Channel

BCK

DATA 14 15 16 14 15 16

14 15 16 14 15 16

16 17 18

DATA

1 2 3 16 17 18

18 19 20 1 2 3 18 19 20

22 23 24 1 2 3

MSB LSB

LSB

MSB LSB

1 2 3 14 15 16

14 15 16

1 2 3 16 17 18

1 2 3 18 19 20

22 23 24

MSB LSB

1 2 3 22 23 24

L-Channel R-ChannelLRCK

BCK

DATA

1 2 3 1 2

MSB

N–2NN–1

LSB

L-Channel R-Channel

LRCK

BCK

DATA

T0009-05

MSB

1 2 3

MSB

1 2 3

MSB

1 2 3

MSB

N–2NN–1

LSB

1 2 3

MSB

N–2NN–1

LSB

1 2 3

MSB

N–2NN–1

LSB

(= 48 fS, or 64 fS)

1 2

PCM1609A

SLES145 – AUGUST 2005

Figure 22. Audio Data Input Formats

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DATA1, DATA2,

DATA3, DATA4

(BCH)

1.4 V

BCK

LRCK

(BCL)

(LB)

(BCY)

(BL)

(DS)

(DH)

T0010-07

1.4 V

PCM1609A

SLES145 – AUGUST 2005

SYMBOL PARAMETER MIN MAX UNITS

(BCY)

(BCH)

(BCL)

(BL)

(LB)

(DS)

(DH)

BCK pulse cycle time 1/(64 fS) BCK high-level time 35 ns BCK low-level time 35 ns BCK rising edge to LRCK edge 10 ns LRCK falling edge to BCK rising edge 10 ns DATA setup time 10 ns DATA hold time 10 ns

(1)

(1) fSis the sampling frequency (e.g., 44.1 kHz, 48 kHz, 96 kHz, etc.)

Figure 23. Audio Interface Timing

Table 2. Audio Input Data to Analog Output Mapping

DATA INPUT CHANNEL ANALOG OUTPUT

DATA1 Left V DATA1 Right V DATA2 Left V DATA2 Right V DATA3 Left V DATA3 Right V DATA4 Left V DATA4 Right V

OUT

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R0001-02

IDX6

MSB LSB

IDX5

IDX4R/W IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0

Read/Write Operation 0 = Write Operation 1 = Read Operation (Register Index is Ignored)

IDX0

D7 D6 D4D5 D3 D2 D1 D0R/W

MDI X R/W

IDX6

IDX1IDX2IDX3IDX4IDX5IDX6

T0048-02

PCM1609A

SLES145 – AUGUST 2005

SERIAL CONTROL INTERFACE

The serial control interface is a 4-wire synchronous serial port that operates asynchronously to the serial audio interface. The serial control interface is used to program and read the on-chip mode registers. The control interface includes MDO (pin 33), MDI (pin 34), MC (pin 35), and ML (pin 36). MDO is the serial data output, used to read back the values of the mode registers; MDI is the serial data input, used to program the mode registers; MC is the serial bit clock, used to shift data in and out of the control port; and ML is the control port latch clock.

All write operations for the serial control port use 16-bit data words. Figure 24 shows the control data word format. The most significant bit is the read/write (R/ W) bit. When set to 0, this bit indicates a write operation. Seven bits, labeled IDX[6:0], set the register index (or address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0].

Figure 25 shows the functional timing diagram for writing to the serial control port. ML is held at a logic-1 state

until a register is to be written. To start the register write cycle, ML is set to logic-0. Sixteen clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI. After the sixteenth clock cycle has completed, ML is set to logic-1 to latch the data into the indexed mode control register.

Figure 24. Control Data Word Format for MDI

Figure 25. Write Operation Timing

SINGLE REGISTER READ OPERATION

Read operations use the 16-bit control word format shown in Figure 24 . For read operations, the R/ W bit is set to 1. Read operations ignore the index bits, IDX[6:0], of the control data word. Instead, the REG[6:0] bits in control register 11 are used to set the index of the register that is to be read during the read operation. Bits IDX[6:0] should be set to 00h for read operations.

The details of the read operation are shown in Figure 26 . First, control register 11 must be written with the index of the register to be read back. Additionally, the INC bit must be set to logic-0 in order to disable the auto-increment read function. The read cycle is then initiated by setting ML to logic-0 and setting the R/ W bit of the control data word to logic-1, indicating a read operation. MDO remains in a high-impedance state until the last eight bits of the 16-bit read cycle, which correspond to the eight data bits of the register indexed by the REG[6:0] bits of control register 11. The read cycle is completed when ML is set to 1, immediately after the MC clock cycle for the least-significant bit of the indexed control register has completed.

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INC = 1 (Auto-Increment Read)

INDEX “N”

1 0 0 0 0 0 0 0 X X X X X X X X

D0D1D2D3D4D5D6D7High Impedance

MDI

MDO

INDEX “Y”

X X X X X X X X X X X X X X X X

D0D1D2D3D4D5D6D7 High Impedance

MDI

MDO

INDEX “N + 1”

D0D1D2D3D4D5D6D7

INC = 0 (Single-Register Read)

INDEX “N”

1 0 0 0 0 0 0 0 X X X X X X X X

D0D1D2D3D4D5D6D7High Impedance

MDI

MDO

T0075-01

PCM1609A

SLES145 – AUGUST 2005

NOTES: X = Don’t care

Y = Last register to be read

In single-register read (INC = 0), the index which indicates the resister to be read in read operation can be set by REG[6:0] in register 11. For example, setting REG[6:0] = 000 1001b means reading from register 9. In auto-increment read (INC = 1), the index REG[6:0] indicates the first register to be read. For example, setting REG[6:0] = 000 1001b means reading registers from 9 to Y. Y is determined by the low-to-high transition of ML in serial mode control.

AUTO-INCREMENT READ OPERATION

The auto-increment read function allows for multiple registers to be read sequentially. The auto-increment read function is enabled by setting the INC bit of control register 11 to 1. The sequence always starts with the register indexed by the REG[6:0] bits in control register 11, and ends by the ML setting to 1 after MC clock cycle for the least-significant bit of last register.

Figure 26. Read Operation Timing

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(MCH)

1.4 V

(MLS)

LSB

1.4 V

(MCL)

(MHH)

(MLH)

(MCY)

(MDH)

(MDS)

MDI

LSB

MDI

T0013-05

LSB

50% of V

MDO

(MOS)

1.4 V

PCM1609A

SLES145 – AUGUST 2005

Figure 26 shows the timing of the auto-increment read operation. The operation begins by writing control register

11, setting INC to 1, and setting REG[6:0] to the first register to be read in the sequence. The actual read operation starts on the next HIGH-to-LOW transition of the ML pin.

The read cycle starts by setting the R/ W bit of the control word to 1, and setting all of the IDX[6:0] bits to 0. All subsequent bits input on MDI are ignored while ML is set to 0. For the first eight clocks of the read cycle, MDO is set to the high-impedance state. This is followed by a sequence of 8-bit words, each corresponding to the data contained in control registers N through Y, where N is defined by the REG[6:0] bits in control register 11, and where Y is the last register to be read. The read cycle is completed when ML is set to 1, immediately after the MC clock cycle for the least-significant bit of the last register has completed. If ML is held low and the MC clock continues beyond the last physical register (register 19), the read operation returns to control register 1 and subsequent control registers, continuing until ML is set to 1.

CONTROL INTERFACE TIMING REQUIREMENTS

Figure 27 shows a detailed timing diagram for the serial control interface. Pay special attention to the setup and

hold times, as well as t clocks. These timing parameters are critical for proper control-port operation.

and t

(MLS)

, which define minimum delays between the edges of the ML and MC

(MLH)

SYMBOL PARAMETER MIN MAX UNITS

(MCY)

(MCL)

(MCH)

(MHH)

(MLS)

(MLH)

(MDH)

(MDS)

(MOS)

MC pulse cycle time 100 ns MC low-level time 50 ns MC high-level time 50 ns ML high-level time 300 ns ML falling edge to MC rising edge 20 ns ML hold time MDI hold time 15 ns MDL setup time 20 ns MC falling edge to MDO stable 30 ns

(1)

(1) MC rising edge for LSB to ML rising edge.

20 ns

Figure 27. Control Interface Timing

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PCM1609A

SLES145 – AUGUST 2005

MODE CONTROL REGISTERS

User-Programmable Mode Controls

The PCM1609A includes a number of user-programmable functions that are accessed via control registers. The registers are programmed using the serial control interface that is previously discussed in this data sheet.

Table 3 lists the available mode control functions, along with their reset default conditions and associated register

index.

Table 3. User-Programmable Mode Controls

FUNCTION RESET DEFAULT BIT(S) LABEL

Digital attenuation control, 0 dB to –63 dB in 0.5-dB steps 0 dB, no attenuation

Soft mute control Mute disabled 7, 18 MUT[8:1] DAC1–DAC8 operation control DAC1–DAC8 enabled 8, 19 DAC[8:1] Audio data format control 24-bit standard format 9 FMT[2:0] Digital filter rolloff control Sharp rolloff 9 FLT SCKO frequency selection Full rate (= f SCKO output enable SCKO enabled 9 CLKE

De-emphasis all-channel function control 10 DMC De-emphasis all-channel sample rate selection 44.1 kHz 10 DMF[1:0]

Output phase select Normal phase 10 DREV Zero-flag polarity select High 10 ZREV Read-register index control REG[6:0] = 01h 11 REG[6:0] Read auto-increment control Auto-increment disabled 11 INC General-purpose output enable Zero-flag enabled 12 GPOE General-purpose output bits (GPO1–GPO6) Disabled 12 GPO[6:1] Oversampling rate control 64 × 12 OVER

De-emphasis, all channels disabled

) 9 CLKD

SCKI

CONTROL

AT1[7:0], AT2[7:0],

1 through 6, 16, AT3[7:0], AT4[7:0],

17 AT5[7:0], AT6[7:0],

AT7[7:0], AT8[7:0]

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PCM1609A

SLES145 – AUGUST 2005

Reserved Registers

Registers 00h and 0Dh through 0Fh are reserved for factory use. To ensure proper operation, the user should not write to or read from these registers.

The mode control register map is shown in Table 4 . Each register includes an R/ W bit that determines whether a register read (R/ W = 1) or write (R/ W = 0) operation is performed. Each register also includes an index (or address) indicated by the IDX[6:0] bits.

Table 4. Mode Control Register Map

IDX REGIS- B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

(B14–B8) TER

01h 1 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 02h 2 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 03h 3 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30 04h 4 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40 05h 5 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT57 AT56 AT55 AT54 AT53 AT52 AT51 AT50 06h 6 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT67 AT66 AT65 AT64 AT63 AT62 AT61 AT60

(1)

07h 7 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV 08h 8 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV 09h 9 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV 0Ah 10 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV 0Bh 11 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 INC REG6 REG5 REG4 REG3 REG2 REG1 REG0 0Ch 12 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER GPOE GPO6 GPO5 GPO4 GPO3 GPO2 GPO1 10h 16 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT77 AT76 AT75 AT74 AT73 AT72 AT71 AT70 11h 17 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT87 AT86 AT85 AT84 AT83 AT82 AT81 AT80 12h 18 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV 13h 19 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV

(1) Reserved for test operation. It should be set to 0 during normal operation.

(1)

RSV

(1)

RSV

(1)

RSV

(1)

ZREV DREV DMF1 DMF0 DMC DMC DMC

(1)

RSV

(1)

RSV

MUT6 MUT5 MUT4 MUT3 MUT2 MUT1

(1)

DAC6 DAC5 DAC4 DAC3 DAC2 DAC1

(1)

FLT CLKD CLKE FMT2 FMT1 FMT0

(1)

RSV

(1)

RSV

(1)

RSV

(1)

RSV

(1)

MUT8 MUT7

(1)

DAC8 DAC7

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PCM1609A

SLES145 – AUGUST 2005

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

REGISTER 1 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 REGISTER 2 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 REGISTER 3 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30 REGISTER 4 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40 REGISTER 5 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT57 AT56 AT55 AT54 AT53 AT52 AT51 AT50 REGISTER 6 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT67 AT66 AT65 AT64 AT63 AT62 AT61 AT60 REGISTER 16 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT77 AT76 AT75 AT74 AT73 AT72 AT71 AT70 REGISTER 17 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT87 AT86 AT85 AT84 AT83 AT82 AT81 AT80

R/ W – Read/Write Mode Select

When R/ W = 0, a write operation is performed. When R/ W = 1, a read operation is performed. Default value: 0

ATx[7:0] – Digital Attenuation Level Setting

where x = 1 through 8, corresponding to the DAC output V

OUT

These bits are read/write. Default value: 1111 1111b Each DAC output, V

1 through V

OUT

8, includes a digital attenuator function. The attenuation level can be set

OUT

from 0 dB to –63 dB in 0.5-dB steps. Changes in attenuation levels are made by incrementing or decrementing by one step (0.5 dB) for every 8/f

time interval until the programmed attenuator setting is reached. Alternatively,

the attenuation level can be set to infinite attenuation, or mute. The attenuation level is calculated using the following formula:

Attenuation level (dB) = 0.5 (ATx[7:0] where ATx[7:0] For ATx[7:0]

= 0 through 255.

DEC

= 0 through 128, the attenuator is set to infinite attenuation.

DEC

– 255)

DEC

The following table shows attenuation levels for various settings.

ATx[7:0] DECIMAL VALUE ATTENUATOR LEVEL SETTING

1111 1111b 255 0 dB, no attenuation (default) 1111 1110b 254 –0.5 dB 1111 1101b 253 –1 dB

: : : 1000 0011b 131 –62 dB 1000 0010b 130 –62.5 dB 1000 0001b 129 –63 dB 1000 0000b 128 Mute

: : : 0000 0000b 0 Mute

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PCM1609A

SLES145 – AUGUST 2005

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

REGISTER 7 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 REGISTER 18 R/ W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV RSV MUT8 MUT7

R/ W – Read/Write Mode Select

When R/ W = 0, a write operation is performed. When R/ W = 1, a read operation is performed. Default value: 0

MUTx – Soft Mute Control

Where x = 1 through 8, corresponding to the DAC output V These bits are read/write. Default value: 0

MUTx = 0 Mute disabled (default) MUTx = 1 Mute enabled

The mute bits, MUT1 through MUT8, are used to enable or disable the soft mute function for the corresponding DAC outputs, V

1 through V

OUT

8. The soft mute function is incorporated into the digital attenuators. When

OUT

mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to the infinite attenuation setting, one attenuator step (0.5 dB) at a time. This provides a quiet, pop-free muting of the DAC output. On returning from soft mute, by setting MUTx = 0, the attenuator is increased one step at a time to the previously programmed attenuation level.

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

OUT

R/ W – Read/Write Mode Select

When R/ W = 0, a write operation is performed. When R/ W = 1, a read operation is performed. Default value: 0

DACx – DAC Operation Control

Where x = 1 through 8, corresponding to the DAC output V

OUT

These bits are read/write. Default value: 0

DACx = 0 DAC operation enabled (default) DACx = 1 DAC operation disabled

The DAC operation controls are used to enable and disable the DAC outputs, V

1 through V

OUT

DACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier input is switched to the dc common-mode voltage (V

), equal to V

COM

/2.

8. When

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PCM1609A

SLES145 – AUGUST 2005

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

R/ W – Read/Write Mode Select

When R/ W = 0, a write operation is performed. When R/ W = 1, a read operation is performed. Default value: 0

FLT – Digital Filter Rolloff Control

This bit is read/write. Default value: 0

FLT = 0 Sharp rolloff (default) FLT = 1 Slow rolloff

The FLT bit allows users to select the digital filter rolloff that is best suited to their application. Two filter rolloff selections are available: sharp or slow. The filter responses for these selections are shown in the Typical Performance Curves section of this data sheet.

CLKD – SCKO Frequency Selection

This bit is read/write. Default value: 0

CLKD = 0 Full-rate, f CLKD = 1 Half-rate, f

= f

SCKO

(default)

SCKI

= f

SCKI

The CLKD bit is used to determine the clock frequency at the system clock output pin, SCKO.

CLKE – SCKO Output Enable

This bit is read/write. Default value: 0

CLKE = 0 SCKO enabled (default) CLKE = 1 SCKO disabled

The CLKE bit is used to enable or disable the system clock output pin, SCKO. When SCKO is enabled, it outputs either a full- or half-rate clock, based on the setting of the CLKD bit. When SCKO is disabled, it is set to a LOW level.

FMT[2:0] – Audio Interface Data Format

These bits are read/write. Default value: 000b

FMT[2:0] Audio Data Format Selection

000 24-bit standard format, right-justified data (default) 001 20-bit standard format, right-justified data 010 18-bit standard format, right-justified data 011 16-bit standard format, right-justified data 100 I2S format, 16- to 24-bit 101 Left-justified format, 16- to 24-bit 110 Reserved 111 Reserved

The FMT[2:0] bits are used to select the data format for the serial audio interface.

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SLES145 – AUGUST 2005

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

R/ W – Read/Write Mode Select

When R/ W = 0, a write operation is performed. When R/ W = 1, a read operation is performed. Default value: 0

ZREV – Zero-Flag Polarity Select

Default value: 0

ZREV = 0 Zero-flag pins HIGH at a zero detect (default) ZREV = 1 Zero-flag pins LOW at a zero detect

The ZREV bit allows the user to select the polarity of zero-flag pins.

DREV – Output Phase Select

Default value: 0

DREV = 0 Normal output (default) DREV = 1 Inverted output

PCM1609A

The DREV bit allows the user to select the phase of analog output signal.

DMF[1:0] – Sampling Frequency Selection for the De-Emphasis Function

These bits are read/write. Default value: 00b

DMF[1:0] De-Emphasis Sample Rate Selection

00 44.1 kHz (default) 01 48 kHz 10 32 kHz 11 Reserved

The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it is enabled. The de-emphasis curves are shown in the Typical Performance Curves section of this data sheet. The preceding table shows the available sampling frequencies.

DMC – Digital De-Emphasis, All-Channel Function Control

This bit is read/write. Default value: 0

DMC = 0 De-emphasis disabled for all channels (default) DMC = 1 De-emphasis enabled for all channels

The DMC bits are used to enable or disable the de-emphasis function for all channels. The three DMC bits are ORed together. Setting any one DMC bit, any combination of two DMC bits, or all three DMC bits to 1 enables digital de-emphasis for all channels. Setting all three DMC bits to 0 disables digital de-emphasis for all channels.

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PCM1609A

SLES145 – AUGUST 2005

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

R/ W – Read/Write Mode Select

When R/ W = 0, a write operation is performed. When R/ W = 1, a read operation is performed. Default value: 0

INC – Auto-Increment Read Control

This bit is read/write. Default value: 0

INC = 0 Auto-increment read disabled (default) INC = 1 Auto-increment read enabled

The INC bit is used to enable or disable the auto-increment read feature of the serial control interface. See the Serial Control Interface section of this data sheet for details regarding auto-increment read operation.

REG[6:0] – Read Register Index

These bits are read/write. Default value: 01h The REG[6:0] bits are used to set the index of the register to be read when performing the single-register read

operation. In the case of an auto-increment read operation, the REG[6:0] bits indicate the index of the last register to be read in the auto-increment read sequence. For example, if registers 1 through 6 are to be read during an auto-increment read operation, the REG[6:0] bits would be set to 06h. See the Serial Control Interface section of this data sheet for details regarding the single-register and auto-increment read operations.

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SLES145 – AUGUST 2005

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

R/ W – Read/Write Mode Select

When R/ W = 0, a write operation is performed. When R/ W = 1, a read operation is performed. Default value: 0

OVER – Oversampling Rate Control

This bit is read/write. Default value: 0

System clock rate = 256 fS, 384 fS, 512 fS, or 768 fS:

OVER = 0 64 × oversampling (default) OVER = 1 128 × oversampling

System clock rate = 128 fSor 192 fS:

OVER = 0 32 × oversampling (default) OVER = 1 64 × oversampling

PCM1609A

The OVER bit is used to control the oversampling rate of the delta-sigma DACs. The OVER = 1 setting is recommended when the oversampling rate is 192 kHz (system clock rate is 128 fSor 192 fS).

GPOE – General-Purpose Output Enable

This bit is read/write. Default value: 0

GPOE = 0 General-purpose outputs disabled (default)

GPOE = 1 General-purpose outputs enabled

Pins default to zero-flag function (ZERO1 through ZERO6).

Data written to GPO1 through GPO6 appears at the corresponding pins.

GPOx – General-Purpose Logic Output

Where: x = 1 through 6, corresponding pins GPO1 through GPO6. These bits are read/write. Default value: 0

GPOx = 0 Set GPOx to 0 (default) GPOx = 1 Set GPOx to 1

The general-purpose output pins, GPO1 through GPO6, are enabled by setting GPOE = 1. These pins are used as general-purpose outputs for controlling user-defined logic functions. When general-purpose outputs are disabled (GPOE = 0), they default to the zero-flag function, ZERO1 through ZERO6.

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f − Frequency − Hz

−100

−80

−60

−40

−20

Level − dB

1 100 1k 10M

G019

10 10k 100k 1M

–

COM

OPA337

10 µF

PCM1609A

S0054-04

BIAS



PCM1609A

SLES145 – AUGUST 2005

ANALOG OUTPUTS

The PCM1609A includes eight independent output channels, V outputs, each capable of driving 3.1 Vp-p typical into a 5-k Ω ac load with V amplifiers for V

OUT

1 through V

8 are dc-biased to the common-mode (or bipolar zero) voltage, equal to V

OUT

1 through V

OUT

8. These are unbalanced

OUT

= 5 V. The internal output

The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy present at the DAC outputs due to the noise-shaping characteristics of the PCM1609A delta-sigma DACs. The frequency response of this filter is shown in Figure 28 . By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for most applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Application Information section of this data sheet.

Figure 28. Output-Filter Frequency Response

/2.

OUTPUT

COM

One unbuffered, common-mode voltage output pin, V pin is nominally biased to a dc voltage level equal to V voltage follower is required for buffering purposes. Figure 29 shows an example of using the V external biasing applications.

(pin 15), is brought out for decoupling purposes. This

COM

/2. If this pin is to be used to bias external circuitry, a

Figure 29. Biasing External Circuits Using the V

pin for

COM

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PCM1609A

SLES145 – AUGUST 2005

ZERO FLAG

Zero-Detect Condition

Zero detection for each output channel is independent from the others. If the data for a given channel remains at a 0 level for 1024 sample periods (or LRCK clock periods), a zero-detect condition exists for that channel.

Zero Output Flags

Given that a zero-detect condition exists for one or more channels, the zero-flag pins for those channels are set to a logic-1 state. Each channel, ZERO1 through ZERO6 (pins 1 through 6), ZERO7 (pin 30), and ZERO8 (pin

32), has zero-flag pins. In addition, all eight zero flags are logically ANDed together, and the result is provided at the ZEROA pin (pin 48), which is set to a logic-1 state when all channels indicate a zero-detect condition. The zero-flag pins can be used to operate external mute circuits. ZERO1 through ZERO6 can be used as status indicators for a microcontroller, audio signal processor, or other digitally controlled function.

The active polarity of the zero-flag output can be inverted by setting to 1 the ZREV bit of control register 10. The reset default is active-high output, or ZREV = 0.

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10 µF

ZERO1−6

+5V Power Supply

S0090-03

PLL170x

SCKO3

MC MD

Regulator

Microcontroller

LPF

LPF LPF LPF LPF

OUT

LRCK

RST

BCK

DATA1 DATA2 DATA3

ZEROA

3536 25262728293031323334

VCC3

AGND3

VCC4

AGND4

OUT

AGND6

VCC5

AGND5

OUT

COM

OUT

24 23 22 21 20 19 18 17 16 15 14 13

PCM1609A

37 38 39 40 41 42 43 44 45 46 47 48

RST SCKI SCKO BCK LRCK TEST V

DGND DATA1 DATA2 DATA3

ZEROA

21 1211109876543

MDI

MDO

ZERO8

DATA4

ZERO7

AGND1

AGND2

ZERO1/GPO1

ZERO2/GPO2

ZERO3/GPO3

ZERO4/GPO4

ZERO5/GPO5

ZERO6/GPO6NCNC

OUT

ZERO7, 8

DATA4

LPF

OUT

LPF

OUT

PCM1609A

SLES145 – AUGUST 2005

APPLICATION INFORMATION

CONNECTION DIAGRAMS

A basic connection diagram with the necessary power-supply bypassing and decoupling components is shown in

Figure 30 . Texas Instruments recommends using the component values shown in Figure 30 for all designs.

Figure 30. Basic Connection Diagram

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0.1 µF

+5V Analog

S0091-03

µC/µP

(1)

3536 25262728293031323334

AGND3

AGND4

OUT

AGND6

AGND5

OUT

COM

OUT

PCM1609A

RST

SCKI

SCKO

BCK

LRCK

TEST

VDDDGND

DATA1

DATA2

DATA3

ZEROA

21 1211109876543

Zero Flag or

General−Purpose

Outputs

for Mute Circuits,

Microcontroller, or

DSP/Decoder

10 µF

REG1117

+3.3V

+3.3V for V

10 µF

Output

Low-Pass

Filters

(4)

10 µF+10 µF

10 µF

CTR

10 µF

SUB

DIGITAL SECTION ANALOG SECTION

10 µF

+3.3V

for V

0.1 µF

(3)

PLL170x

Buffer

SCKO3

(2)

XT1

27MHz

Master Clock

RSR

Audio DSP

Decoder

RSR

10 µF

10 µF+10 µF

10 µF

Down Mix

Zero-Flag

AGND2 VCC2 AGND1 VCC1 NC ZERO7 DATA4 ZERO8 MDO MDI MC ML

OUT

6 NC NC

ZERO6/GPO6 ZERO5/GPO5 ZERO4/GPO4 ZERO3/GPO3 ZERO2/GPO2 ZERO1/GPO1

PCM1609A

SLES145 – AUGUST 2005

APPLICATION INFORMATION (continued)

(1) Serial control and reset functions can be provided by DSP/decoder GPIO pins. (2) Actual clock output used is determined by the application. (3) RS= 22 Ω to 100 Ω . (4) See the Application Information section of this data sheet for more information.

Figure 31. Typical Application Diagram

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–

OPA2134

OUT

 

S0053-02

PCM1609A

SLES145 – AUGUST 2005

APPLICATION INFORMATION (continued)

A typical application diagram is shown in Figure 31 . The REG1117-3.3 from Texas Instruments is used to generate 3.3 V for V generate the system clock input at SCKI, as well as generating the clock for the audio signal processor.

Series resistors (22- Ω to 100- Ω ) are recommended for SCKI, LRCK, BCK, DATA1, DATA2, DATA3, and DATA4. The series resistor combines with the stray PCB and device input capacitance to form a low-pass filter which removes high-frequency noise from the digital signal, thus reducing high-frequency emission.

POWER SUPPLIES AND GROUNDING

The PCM1609A requires a 5-V analog supply and a 3.3-V digital supply. The 5-V supply is used to power the DAC analog and output filter circuitry, whereas the 3.3-V supply is used to power the digital filter and serial interface circuitry. For best performance, the 3.3-V supply should be derived from the 5-V supply using a linear regulator (see Figure 31 ).

Two capacitors are required for supply bypassing (see Figure 30 ). These capacitors should be located as close as possible to the PCM1609A package. The 10- µ F capacitors should be tantalum or aluminum electrolytic, whereas the 0.1- µ F capacitors are ceramic (X7R type is recommended for surface-mount applications).

DAC OUTPUT FILTER CIRCUITS

Delta-sigma DACs use noise-shaping techniques to improve in-band signal-to-noise ratio (SNR) performance at the expense of generating increased out-of-band noise above the Nyquist frequency, or fS/2. The out-of-band noise must be low-pass filtered in order to provide optimal converter performance. This is accomplished by a combination of on-chip and external low-pass filtering.

Figure 32 and Figure 33 show the recommended external low-pass active filter circuits for dual- and

single-supply applications. These circuits are second-order Butterworth filters using the multiple feedback (MFB) circuit arrangement, which reduces sensitivity to passive component variations over frequency and temperature. For more information regarding MFB active filter design, see the FilterPro™ MFB and Sallen-Key Low-Pass Filter Design Program application report (SBFA001 ), available from the TI Web site (www.ti.com).

Because the overall system performance is defined by the quality of the DACs and their associated analog output circuitry, high-quality audio operational amplifiers are recommended for the active filters. The OPA2134 and OPA2353 dual operational amplifiers from Texas Instruments are shown in Figure 32 and Figure 33 , and are recommended for use with the PCM1609A.

from the 5-V analog power supply. The PLL170x from Texas Instruments is used to

Figure 32. Dual-Supply Filter Circuit

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–

PCM1609A

 

COM

OPA2134

10 µF

S0056-04

OPA337

−

To Additional Low-Pass Filter Circuits

OUT

Digital Logic

and

Audio

Processor

Digital Power +V

DGND

Digital Section Analog Section

Return Path for Digital Signals

Analog Power

AGND −V

+5V

Digital

Ground

Analog

Ground

Output

Circuits

PCM1609A

AGND

DGND

REG

B0031-05

APPLICATION INFORMATION (continued)

PCM1609A

SLES145 – AUGUST 2005

Figure 33. Single-Supply Filter Circuit

PCB LAYOUT GUIDELINES

A typical PCB floor plan for the PCM1609A is shown in Figure 34 . A ground plane is recommended, with the analog and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1609A should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections to the digital audio interface and control signals originating from the digital section of the board.

Figure 34. Recommended PCB Layout

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Digital Section Analog Section

RF Choke or Ferrite Bead

Power Supplies

Common

Ground

Output

Circuits

AGND

+5V −V

AGND

DGND

REG

PCM1609A

B0032-05

Digital Logic

and

Audio

Processor

PCM1609A

SLES145 – AUGUST 2005

PCB LAYOUT GUIDELINES (continued)

Separate power supplies are recommended for the digital and analog sections of the board. This prevents the switching noise present on the digital supply from contaminating the analog power supply and degrading the dynamic performance of the DACs. In cases where a common 5-V supply must be used for the analog and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital 5-V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 35 shows the recommended approach for single-supply applications.

Figure 35. Single-Supply PCB Layout

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B0008-03

−

–1

+ +

8-Level Quantizer

−

–1

8 f

OUT

64 f

–1

PCM1609A

SLES145 – AUGUST 2005

THEORY OF OPERATION

The DAC section of the PCM1609A is based on a multi-bit delta-sigma architecture. This architecture uses a fourth-order noise shaper and an 8-level amplitude quantizer, followed by an analog low-pass filter. A block diagram of the delta-sigma modulator is shown in Figure 36 . This architecture has the advantage of stability and improved jitter tolerance, when compared to traditional 1-bit (2-level) delta-sigma designs.

Figure 36. Eight-Level Delta-Sigma Modulator

The combined oversampling rate of the digital interpolation filter and the delta-sigma modulator is 32 fS, 64 fS, or 128 fS. The total oversampling rate is determined by the desired sampling frequency. If fS≤ 96 kHz, then the OVER bit in register 12 can be set to an oversampling rate of 64 fSor 128 fS. If fS> 96 kHz, then the OVER bit can be used to set the oversampling rate to 32 fSor 64 fS. Figure 37 shows the out-of-band quantization-noise plots for both the 64 × and 128 × oversampling scenarios. Notice that the 128 × oversampling plot shows significantly improved out-of-band noise performance, allowing for a simplified low-pass filter to be used at the output of the DAC.

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Frequency [fS]

−180

−160

−140

−120

−100

−80

−60

−40

−20

0 1 2 3 4 5 6 7 8

Amplitude − dB

G021

Frequency [fS]

−180

−160

−140

−120

−100

−80

−60

−40

−20

0 1 2 3 4 5 6 7 8

Amplitude − dB

G022

Jitter − ps

100

105

110

115

120

125

0 100 200 300 400 500 600

Dynamic Range − dB

G020

PCM1609A

SLES145 – AUGUST 2005

THEORY OF OPERATION (continued)

QUANTIZATION NOISE SPECTRUM QUANTIZATION NOISE SPECTRUM

(64 × OVERSAMPLING) vs

(128 × OVERSAMPLING)

Figure 37. Quantization-Noise Spectrum

Figure 38 illustrates the simulated jitter sensitivity of the PCM1609A. To achieve best performance, the system

clock jitter should be less than 300 picoseconds. This is easily achieved using a quality clock generation IC, like the PLL170x from Texas Instruments.

JITTER DEPENDENCE (64 × OVERSAMPLING)

Figure 38. Jitter Sensitivity

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S/PDIF

Receiver

Evaluation Board

DEM-DAI1609A

PCM1609A

2nd-Order

Low-Pass

Filter

Notch FilterBand Limit

Analyzer

and

Display

Digital

Generator S/PDIF Output

100% Full-Scale

24-Bit, 1-kHz

Sine Wave

rms Mode HPF = 22 Hz

(1)

LPF = 30 kHz

(1)

Option = 20-kHz Apogee Filter

(2)

= 1 kHz

–3 dB

= 54 kHz

B0062-03

PCM1609A

SLES145 – AUGUST 2005

KEY PERFORMANCE PARAMETERS AND MEASUREMENT

This section provides information on how to measure key dynamic performance parameters for the PCM1609A. In all cases, a System Two Cascade audio measurement system by Audio Precision or equivalent is used to perform the testing.

TOTAL HARMONIC DISTORTION + NOISE

Total harmonic distortion + noise (THD+N) is a significant figure of merit for audio DACs, because it takes into account both harmonic distortion and all noise sources within a specified measurement bandwidth. The true rms value of the distortion and noise is referred to as THD+N. The test setup for THD+N measurements is shown in

Figure 39 .

(1) There is little difference in measured THD+N when using the various settings for these filters. (2) Required for THD+N test

Figure 39. Test Setup for THD+N Measurements

For the PCM1609A DACs, THD+N is measured with a full-scale, 1-kHz digital sine wave as the test stimulus at the input of the DAC. The digital generator is set to a 24-bit audio word length and a sampling frequency of 44.1 kHz or 96 kHz. The digital generator output is taken from the unbalanced S/PDIF connector of the measurement system. The S/PDIF data is transmitted via coaxial cable to the digital audio receiver on the DEM-DAI1602 demonstration board. The receiver is then configured to output 24-bit data in either I2S or left-justified data format. The DAC audio interface format is programmed to match the receiver output format. The analog output is then taken from the DAC post filter and connected to the analog analyzer input of the measurement system. The analog input is band-limited, using filters resident in the analyzer. The resulting THD+N is measured by the analyzer and displayed by the measurement system.

DYNAMIC RANGE

Dynamic range is specified as A-weighted THD+N measured with a –60-dBFS, 1-kHz digital sine wave stimulus at the input of the DAC. This measurement is designed to give a good indication of how the DAC performs, given a low-level input signal.

The measurement setup for the dynamic range measurement is shown in Figure 40 , and is similar to the THD+N test setup discussed previously. The differences include the band-limit filter selection, the additional A-weighting filter, and the –60-dBFS input level.

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S/PDIF

Receiver

Evaluation Board

DEM-DAI1609A

PCM1609A

(1)

2nd-Order

Low-Pass

Filter

Band Limit

A-Weight

Filter

(1)

Analyzer

and

Display

Digital

Generator

S/PDIF

Output

0% Full-Scale,

Dither Off (SNR)

–60 dB FS,

1-kHz Sine Wave

(Dynamic Range)

rms Mode HPF = 22 Hz

LPF = 22 kHz Option = A-Weighting

(2)

B0063-03

–3 dB

= 54 kHz

= 1 kHz

Notch Filter

PCM1609A

SLES145 – AUGUST 2005

KEY PERFORMANCE PARAMETERS AND MEASUREMENT (continued)

(1) Infinite-zero-detect mute disabled (2) Results without A-weighting are approximately 3 dB worse.

Figure 40. Test Setup for Dynamic Range and SNR Measurements

IDLE-CHANNEL SIGNAL-TO-NOISE RATIO

The SNR test provides a measure of the noise of the DAC. The input to the DAC is in all-0s data, and the DAC infinite-zero-detect mute function must be disabled (default condition at power up for the PCM1609A). This ensures that the delta-sigma modulator output is connected to the output amplifier circuit so that idle tones (if present) can be observed at the output. The dither function of the digital signal generator must also be disabled to ensure an all-0s data stream at the input of the DAC.

The measurement setup for SNR is identical to that used for dynamic range, with the exception of the input signal level (see the notes provided in Figure 40 ).

PACKAGE OPTION ADDENDUM

www.ti.com

27-Sep-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

PCM1609APT PREVIEW LQFP PT 48 TBD Call TI Call TI

PCM1609APTR PREVIEW LQFP PT 48 TBD Call TI CallTI

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

17-Nov-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

PCM1609APT ACTIVE LQFP PT 48 250 Green (RoHS &

no Sb/Br)

PCM1609APTG4 ACTIVE LQFP PT 48 250 Green (RoHS &

no Sb/Br)

PCM1609APTR ACTIVE LQFP PT 48 1000 Green (RoHS &

no Sb/Br)

PCM1609APTRG4 ACTIVE LQFP PT 48 1000 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996

PT (S-PQFP-G48) PLASTIC QUAD FLATPACK

0,50

1,45 1,35

0,27

0,17

5,50 TYP

7,20

6,80 9,20

8,80

0,08

0,05 MIN

0,13 NOM

Gage Plane

0,25

0°–7°

1,60 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. This may also be a thermally enhanced plastic package with leads conected to the die pads.

Seating Plane

0,10

0,75 0,45

4040052/C 11/96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty . Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

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BURR-BROWN PCM1609A User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual