Burr-Brown MPC508A, MPC509A User Manual

Level

Shift

1kΩ

1kΩ

1kΩ

Overvoltage

Clamp and

Signal

Isolation

5V

Ref

Decoder/

Driver

NOTE: (1) Digital
Input Protection.

In 1

In 2

In 8

MPC508A

A

0

A

1

A

2

EN

(1)

Out

(1)

(1)

(1)

查询MPC509AU/1K供应商

Single-Ended 8-Channel/Differential 4-Channel

CMOS ANALOG MULTIPLEXERS

M

P

C508

MPC508A
MPC509A

M

PC509

SBFS019A – JANUARY 1988 — REVISED OCTOBER 2003

FEATURES

● ANALOG OVERVOLTAGE PROTECTION: 70V

● NO CHANNEL INTERACTION DURING

OVERVOLTAGE

● BREAK-BEFORE-MAKE SWITCHING

● ANALOG SIGNAL RANGE:

±15V

● STANDBY POWER: 7.5mW typ

● TRUE SECOND SOURCE

DESCRIPTION

The MPC508A is an 8-channel single-ended analog
multiplexer and the MPC509A is a 4-channel differential
multiplexer.

The MPC508A and MPC509A multiplexers have input
overvoltage protection. Analog input voltages may exceed
either power supply voltage without damaging the device or
disturbing the signal path of other channels. The protection
circuitry assures that signal fidelity is maintained even under
fault conditions that would destroy other multiplexers. Analog
inputs can withstand 70V
tests. Signal sources are protected from short circuits should
multiplexer power loss occur; each input presents a 1kΩ
resistance under this condition. Digital inputs can also sustain
continuous faults up to 4V greater than either supply voltage.

These features make the MPC508A and MPC509A ideal for
use in systems where the analog signals originate from
external equipment or separately powered sources.

The MPC508A and MPC509A are fabricated with Burr­Brown’s dielectrically isolated CMOS technology. The
multiplexers are available in plastic DIP and plastic SOIC
packages. Temperature range is –40°C to +85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

signal levels and standard ESD

PP

PP

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In 1A

In 4A

In 1B

In 4B

FUNCTIONAL DIAGRAMS

1kΩ

1kΩ

1kΩ

1kΩ

Overvoltage

Clamp and

Signal

Isolation

NOTE: (1) Digital
Input Protection.

MPC509A

Copyright © 1998-2003, Texas Instruments Incorporated

5V

Ref

Decoder/

Driver

Level

Shift

(1) (1) (1)

A

A

1

0

Out A

Out B

EN

ELECTRICAL CHARACTERISTICS

Supplies = +15V, –15V; VAH (Logic Level High) = +4.0V, VAL (Logic Level Low) = +0.8V, unless otherwise specified.

MPC508A/509A

PARAMETER TEMP MIN TYP MAX UNITS
ANALOG CHANNEL CHARACTERISTICS

, Analog Signal Range Full –15 +15 V

V

S

RON, On Resistance

(OFF), Off Input Leakage Current +25°C 0.5 nA

I

S

(OFF), Off Output Leakage Current +25°C 0.2 nA

I

D

MPC508A Full 5 nA
MPC509A Full 5 nA

(OFF) with Input Overvoltage Applied

I

D

(ON), On Channel Leakage Current +25°C2nA

I

D

MPC508A Full 10 nA
MPC509A Full 10 nA

I

Differential Off Output Leakage Current

DIFF

(MPC509A Only) Full 10 nA

DIGITAL INPUT CHARACTERISTICS

, Input Low Threshold Drive Full 0.8 V

V

AL

, Input High Threshold

V

AH

IA, Input Leakage Current (High or Low)

SWITCHING CHARACTERISTICS

, Access Time +25°C 0.5 µs

t

A

, Break-Before-Make Delay +25°C2580 ns

t

OPEN

(EN), Enable Delay (ON) +25°C 200 ns

t

ON

(EN), Enable Delay (OFF) +25°C 250 ns

t

OFF

Settling Time (0.1%) +25°C 1.2 µs

"OFF Isolation"
CS (OFF), Channel Input Capacitance +25°C5pF

(OFF), Channel Output Capacitance: MPC508A +25°C25pF

C

D

MPC509A +25°C12pF

, Digital Input Capacitance 25°C5pF

C

A

CDS (OFF), Input to Output Capacitance +25°C 0.1 pF

POWER REQUIREMENTS

, Power Dissipation Full 7.5 mW

P

D

I+, Current Pin 1
I–, Current Pin 27

NOTES: (1) V
(4) Digital input leakage is primarily due to the clamp diodes. Typical leakage is less than 1nA at 25°C. (5) V
Worst-case isolation occurs on channel 4 due to proximity of the output pins. (6) V

(1)

+25°C 1.3 1.5 kΩ

Full 1.5 1.8 kΩ

Full 10 nA

(2)

(3)

(4)

+25°C 2.0 µA

Full 4.0 V
Full 1.0 µA

Full 0.6 µs

Full 500 ns

Full 500 ns

(0.01%) +25°C 3.5 µs

(5)

= ±10V, I

OUT

(6)

(6)

= –100µA. (2) Analog overvoltage = ±33V. (3) To drive from DTL/TTL circuits. 1kΩ pull-up resistors to +5.0V supply are recommended.

OUT

+25°C5068 dB

Full 0.7 1.5 mA
Full 5 20 µA

= 0.8V, RL = 1kΩ, CL = 15pF, VS = 7Vrms, f = 100kHz.

, VA = 0V or 4.0V.

EN

EN

2

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MPC508A, MPC509A

SBFS019A

PIN CONFIGURATIONS

Top View

A

16

15

14

13

12

11

10

9

1

A

2

Ground

+V

SUPPLY

In 5

In 6

In 7

In 8

–V

En

SUPPLY

In 1

In 2

In 3

In 4

Out

1

A

0

2

3

4

5

6

7

8

MPC508A (Plastic)

TRUTH TABLES

MPC508A

A

2

A

1

A

0

EN CHANNEL

X X X L None
LLLH1
LLHH2
LHLH3
LHHH4
HLLH5
HLHH6
HHLH7
HHHH8

"ON"

Top View

A

16

15

14

13

12

11

10

9

1

Ground

+V

SUPPLY

In 1B

In 2B

In 3B

In 4B

Out B

–V

SUPPLY

In 1A

In 2A

In 3A

In 4A

Out A

A

En

1

0

2

3

4

5

6

7

8

MPC509 A (Plastic)

MPC509A

"ON"

CHANNEL

A

1

X X L None
LLH 1
LHH 2
HLH 3
HHH 4

A

0

EN PAIR

ABSOLUTE MAXIMUM RATINGS

(1)

Voltage between supply pins ............................................................... 44V

V+ to ground ........................................................................................ 22V

V– to ground ........................................................................................ 25V

Digital input overvoltage V

Analog input overvoltage V

Continuous current, S or D ............................................................... 20mA

, VA:

EN

V

(+) ................................................... +4V

SUPPLY

V

(–) ................................................... –4V

SUPPLY

or 20mA, whichever occurs first.

:

S

V

(+) ................................................ +20V

SUPPLY

V

(–) ................................................ –20V

SUPPLY

Peak current, S or D

(pulsed at 1ms, 10% duty cycle max) ............................................ 40mA

Power dissipation

(2)

.......................................................................... 1.28W

Operating temperature range ........................................... –40°C to +85°C

Storage temperature range............................................. –65°C to +150°C

NOTE: (1) Absolute maximum ratings are limiting values, applied individu­ally, beyond which the serviceability of the circuit may be impaired. Func­tional operation under any of these conditions is not necessarily implied.
(2) Derate 1.28mW/°C above T

= +70°C.

A

MPC508A, MPC509A

SBFS019A

PACKAGE/ORDERING INFORMATION

For the most current package and ordering information, see
the Package Option Addendum located at the end of this
data sheet.

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3

q

)

g

TYPICAL PERFORMANCE CURVES

Typical at +25°C unless otherwise noted.

SOURCE RESISTANCE FOR 20V STEP CHANGE

1k

100

10

Settling Time (µs)

1

0.1

0.01 0.1

SETTLING TIME vs

To ±0.01%

To ±0.1%

1

Source Resistance (kΩ)

120

100

80

60

10 100

COMBINED CMR vs

FREQUENCY MPC509A AND INA110

1

0.1

0.01

0.001

Crosstalk (% of Off Channel Signal)

0.0001
110

G = 100

G = 10

CROSSTALK vs SIGNAL FREQUENCY

Rs = 100kΩ

nal Frequency (Hz)

Si

G = 500

Rs = 10kΩ

R

100

= 1kΩ

s

= 100Ω

R

s

1k 10k

40

20

Common-Mode Rejection (dB)

0

1 10 100 1k 10k

uency (Hz

Fre

4

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MPC508A, MPC509A

SBFS019A

DISCUSSION OF
PERFORMANCE

DC CHARACTERISTICS

The static or dc transfer accuracy of transmitting the multi­plexer input voltage to the output depends on the channel ON
resistance (RON), the load impedance, the source impedance,
the load bias current and the multiplexer leakage current.

Single-Ended Multiplexer Static Accuracy

The major contributors to static transfer accuracy for single­ended multiplexers are:

Source resistance loading error;
Multiplexer ON resistance error;
and, dc offset error caused by both load bias current and
multiplexer leakage current.

Resistive Loading Errors

The source and load impedances will determine the input
resistive loading errors. To minimize these errors:

• Keep loading impedance as high as possible. This mini­mizes the resistive loading effects of the source resis­tance and multiplexer ON resistance. As a guideline, load
impedances of 10
ing errors to 0.002% or less for 1000Ω source imped­ances. A 106Ω load impedance will increase source
loading error to 0.2% or more.

• Use sources with impedances as low as possible. 1000Ω
source resistance will present less than 0.001% loading
error and 10kΩ source resistance will increase source
loading error to 0.01% with a 108 load impedance.

Input resistive loading errors are determined by the follow­ing relationship (see Figure 1).

Source and Multiplexer Resistive Loading Error

∈+ =

where RS = source resistance

RL = load resistance
R

= multiplexer ON resistance

ON

8

Ω, or greater, will keep resistive load-

+

RR

SON

SON

++

RR R

SON

100

×() %RR

L

Differential Multiplexer Static Accuracy

Static accuracy errors in a differential multiplexer are diffi­cult to control, especially when it is used for multiplexing
low-level signals with full-scale ranges of 10mV to 100mV.

The matching properties of the multiplexer, source and
output load play a very important part in determining the
transfer accuracy of the multiplexer. The source impedance
unbalance, common-mode impedance, load bias current mis­match, load differential impedance mismatch, and common­mode impedance of the load all contribute errors to the
multiplexer. The multiplexer ON resistance mismatch, leak­age current mismatch and ON resistance also contribute to
differential errors.

The effects of these errors can be minimized by following the
general guidelines described in this section, especially for
low-level multiplexing applications. Refer to Figure 2.

Load (Output Device) Characteristics

• Use devices with very low bias current. Generally, FET
input amplifiers should be used for low-level signals less
than 50mV FSR. Low bias current bipolar input amplifi­ers are acceptable for signal ranges higher than 50mV
FSR. Bias current matching will determine the input
offset.

• The system dc common-mode rejection (CMR) can never
be better than the combined CMR of the multiplexer and
driven load. System CMR will be less than the device
which has the lower CMR figure.

• Load impedances, differential and common-mode, should

10

be 10

Ω or higher.

I

R

S1

V

S1

R

S8

V

S8

R

ON

R

OFF

BIAS

V

M

I

L

Z

L

Measured

Voltage

FIGURE 1. MPC508A DC Accuracy Equivalent Circuit.

Input Offset Voltage

Bias current generates an input OFFSET voltage as a result
of the IR drop across the multiplexer ON resistance and
source resistance. A load bias current of 10nA will generate
an offset voltage of 20µV if a 1kΩ source is used. In general,
for the MPC508A, the OFFSET voltage at the output is
determined by:

V

= (IB + IL) (RON + RS)

OFFSET

where IB = Bias current of device multiplexer is driving

IL = Multiplexer leakage current
RON = Multiplexer ON resistance
RS = source resistance

MPC508A, MPC509A

SBFS019A

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R

S1

V

S1

S1B

S4A

S48

R

R

R

R

R

CM1

R

V

S8

R

R

CM4

ON1A

ON1B

OFF4A

OFF4B

BIAS A

Cd/2

I

L

I

BIAS B

Cd/2

I

LB

Rd/2

Rd/2

Z

L

R

CM

C

CM

I

R

FIGURE 2. MPC509A DC Accuracy Equivalent Circuit.

5