Burr-Brown DAC7731 User Manual

DAC7731

SBAS249 – DECEMBER 2001

16-Bit, Voltage Output, Serial Input

DIGITAL-TO-ANALOG CONVERTER

DAC7731

FEATURES

● LOW POWER: 150mW MAXIMUM

● +10V INTERNAL REFERENCE

● UNIPOLAR OR BIPOLAR OPERATION

● SETTLING TIME: 5µs to ±0.003% FSR

● 16-BIT MONOTINICITY, –40°C TO +85°C

● ±10V, ±5V, OR +10V CONFIGURABLE VOLTAGE

OUTPUT

● RESET TO ZERO OR MID-SCALE

● DOUBLE-BUFFERED DATA INPUT

● DAISY-CHAIN FEATURE FOR MULTIPLE

DAC7731s ON A SINGLE BUS

● SMALL SSOP-24 PACKAGE

APPLICATIONS

● PROCESS CONTROL

● ATE PIN ELECTRONICS

● CLOSED-LOOP SERVO CONTROL

● MOTOR CONTROL

● DATA ACQUISITION SYSTEMS

DESCRIPTION

The DAC7731 is a 16-bit Digital-to-Analog Converter (DAC)
which provides 16 bits of monotonic performance over the
specified operating temperature range and offers a +10V
internal reference. Designed for automatic test equipment
and industrial process control applications, the DAC7731’s
output swing can be configured in a ±10V, ±5V, or +10V
range. The flexibility of the output configuration allows the
DAC7731 to provide both unipolar and bipolar operation by
pin strapping. The DAC7731 includes a high-speed output
amplifier with a maximum settling time of 5µs to ±0.003%
FSR for a 20V full-scale change and only consumes 100mW
(typical) of power.

The DAC7731 features a standard 3-wire, SPI-compatible
serial interface with double buffering to allow asynchronous
updates of the analog output as well as a serial data output
line for daisy-chaining multiple DAC7731’s. A user program­mable reset control forces the DAC output to either min-scale
(0000

) or mid-scale (8000H), overriding both the input and

H

DAC register values. The DAC7731 is available in a
SSOP-24 package and three performance grades specified
to operate from –40°C to +85°C.

V

DDVSSVCC

REFEN

RSTSEL

RST

LDAC

SCLK

CS

SDO

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Enable

SDI

AGND DGND

REFADJ

Control

Logic

Input

Register

REF

+10V

Reference

Register

REF

OUT

DAC

www.ti.com

IN

Buffer

V

DAC

REF

R

OFFSET

RFB2

RFB1

SJ

V

OUT

Copyright © 2001, Texas Instruments Incorporated

ABSOLUTE MAXIMUM RATINGS

V

to VSS...........................................................................–0.3V to +32V

CC

V

to AGND ...................................................................... –0.3V to +16V

CC

V

to AGND ...................................................................... –16V to +0.3V

SS

AGND

to DGND................................................................... –0.3V to 0.3V

REF

to AGND .............................................................. 0V to VCC – 1.4V

IN

V

to DGND ........................................................................ –0.3V to +6V

DD

Digital Input Voltage to DGND ................................. –0.3V to V

Digital Output Voltage to DGND .............................. –0.3V to V

Operating Temperature Range ........................................ –40°C to +85°C

Storage Temperature Range ......................................... –65°C to +150°C

Junction Temperature (TJ Max) .................................................... +150°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

(1)

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru­ments recommends that all integrated circuits be handled with

+ 0.3V

DD

+ 0.3V

DD

appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

PACKAGE/ORDERING INFORMATION

PRODUCT PACKAGE-LEAD DESIGNATOR

PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

DAC7731E SSOP-24 DB –40°C to +85°C DAC7731E DAC7731E Rails, 60

(1)

"" " " "DAC7731E/1K Tape and Reel,1000

DAC7731EB SSOP-24 DB –40°C to +85°C DAC7731EB DAC7731EB Rails, 60

"" " " "DAC7731EB/1K Tape and Reel, 1000

DAC7731EC SSOP-24 DB –40°C to +85°C DAC7731EC DAC7731EC Rails, 60

"" " " "DAC7731EC/1K Tape and Reel, 1000

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. (2) Models with a slash (/) are available only in Tape and
Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7731EC/1K” will get a single 1000-piece Tape and Reel.

SPECIFIED

RANGE MARKING NUMBER

(2)

MEDIA, QUANTITY

ELECTRICAL CHARACTERISTICS

All specifications at TA = T

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
ACCURACY

Linearity Error (INL) ±6 ±4 ±3LSB

Differential Linearity Error
Monotonicity 14 15 16 Bits
Offset Error
Offset Error Drift
Gain Error With Internal REF ±0.4 ±0.25 ±0.15 % of FSR

Gain Error Drift With Internal REF ±15 ±10 ±7 ppm/°C
PSRR (V

ANALOG OUTPUT

Voltage Output

Output Current ±5 ✻✻ mA
Output Impeadance 0.1 ✻✻Ω
Maximum Load Capacitance 200 ✻✻pF
Short-Circuit Current ±15 ✻✻mA
Short-Circuit Duration AGND Indefinite ✻✻

REFERENCE

Reference Output 9.96 10 10.04 9.975 ✻ 10.025 ✻✻✻ V
REF
REF
REF
REF
REF
REFADJ Input Range

REFADJ Input Impedance 50
V

REF

V

REF

or VSS) At Full-Scale 50 200 ✻✻ ✻✻ppm/V

CC

(2)

Impedance 400 ✻✻Ω

OUT

Voltage Drift ±15 ±10 ±7 ppm/°C

OUT

Voltage Adjustment

OUT

Input Range

IN

Input Current 10 ✻✻nA

IN

Output Current –2+2✻✻✻ ✻mA
Impedance 1 ✻✻Ω

to T

MIN

(DNL)

(1)

(4)

, VCC = +15V, VSS = –15V, VDD = +5V, Internal refi⁄ence enabled, unless otherwise noted.

MAX

DAC7731E DAC7731EB DAC7731EC

TA = 25°C ±5 ±3 ±2LSB

±2 ✻✻ppm/°C

With External REF ±0.25 ±0.1 ✻ % of FSR

+11.4/–4.75 0 to 10 ✻✻V
+11.4/–11.4 ±10 ✻✻V

+11.4/–6.4 ±5 ✻✻V

(3)

Absolute Max Value that

can be applied is V

±25 ✻✻ mV

4.75 V

010✻✻✻✻V

CC

±4 ±2 ±1LSB

±0.1 ✻✻% of FSR

– 1.4 ✻✻✻✻V

CC

✻✻kΩ

2

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DAC7731

SBAS249

ELECTRICAL CHARACTERISTICS (Cont.)

All specifications at TA = T

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DYNAMIC PERFORMANCE

Settling Time to ±0.003% 20V Output Step 3 5 ✻✻ ✻✻ µs

Digital Feedthrough 2 ✻✻nV-s
Output Noise Voltage at 10kHz 100 ✻✻nV/√Hz

DIGITAL INPUT

V

IH

V

IL

DIGITAL OUTPUT

V

OH

V

OL

POWER SUPPLY

V

DD

V

CC

V

SS

I

DD

I

CC

I

SS

Power

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻✻ ✻°C

✻ Specifications same as grade to the left.

NOTES: (1)

With minimum VCC/VSS requirements, internal reference enabled. (2) Please refer to the "Theory of Operation" section for more information with respect to output voltage
configurations. (3) See Figure 11 for gain and offset adjustment connection diagrams when using the internal reference. (4) The minimum value for REF
of V

+14V and +4.75V, where +4.75V is the minimum voltage allowed. (5) Reference low-pass filter values: 100kΩ, 1.0µF (see Figure 14).

SS

to T

MIN

, VCC = +15V, VSS = –15V, VDD = +5V, Internal reference enabled, unless otherwise noted.

MAX

R

= 5kΩ, CL = 200pF,

L

with external REF

to REF

|IH| < 10µA0.7 • V
|IL| < 10µA0.3 • V

OUT

(5)

filter

IN

DD

IOH = –0.8mA 3.6 ✻✻ V

IOL = 1.6mA 0.4 ✻✻V

+4.75 +5.0 +5.25 ✻✻✻✻✻✻ V
+11.4 +15.75 ✻✻✻✻V

Bipolar Operation –15.75 –11.4 ✻✻✻✻V

Unipolar Opeation –15.75 –4.75 ✻✻✻✻V

Unloaded 4 6 ✻✻ ✻✻ mA

Unloaded –4 –2.5 ✻✻ ✻✻ mA
No Load, Ext. Reference
No Load, Int. Reference 100 150

DAC7731E DAC7731EB DAC7731EC

✻✻ V

DD

✻✻V

100 ✻✻µA

85 ✻✻mW

✻✻ ✻✻mW

must be equal to the greater

IN

PIN CONFIGURATION

Top View SSOP

V

1

CC

REF

REFADJ

R

OFFSET

AGND

OUT

REF

V

REF

RFB2
RFB1

V

OUT

V

SJ

2
3

IN

4
5
6

DAC7731

7
8
9

10

11

12

DD

NOTE: (1) RST, LDAC, SDI, CS and SCK are Schmitt-triggered inputs.

24
23
22
21
20
19
18
17
16
15
14
13

V

SS

REFEN
RSTSEL
SCLK
CS
SDO
SDI
LDAC
RST
NC
TEST
DGND

PIN DESCRIPTIONS

PIN NAME DESCRIPTION

1V
2REF
3 REF
4 REFADJ Internal Reference Trim. (Acts as a gain adjustment

5V

6R

OFFSET

7 AGND Analog ground
8 RFB2 Feedback Resistor 2, used to configure DAC output

9 RFB1 Feedback Resistor 1, used to configure DAC output

10 SJ Summing Junction of the Output Amplifier
11 V
12 V
13 DGND Digital Ground
14 TEST Reserved, Connect to DGND
15 NC No Connection
16 RST V

17 LDAC DAC register load control, rising dege triggered. Data

18 SDI Serial Data Input. Data is latched into the input

19 SDO Serial Data Output, delayed 16 SCLK clock cycles.
20 CS Chip Select, Active LOW
21 SCLK Serial Clock Input
22 RSTSEL Reset Select; determines the action of RST. If HIGH,

23 REFEN Enables internal +10V reference (REF

24 V

Positive Analog Power Supply

CC

Internal Reference Output

OUT

Reference Input

IN

input when the internal reference is used.)
Buffered Output from REFIN, can be used to drive

REF

external devices. Internally, this pin directly drives the
DAC's circuitry.
Offsetting Resistor

range.

range.

DAC Voltage Output

OUT

Digital Power Supply

DD

reset; active LOW, depending on the state of

OUT

RSTSEL, the DAC register is either reset to mid­scale or min-scale.

is loaded from the input register to the DAC register.

register on the rising edge of SCLK.

RST will reset the DAC register to mid-scale. If LOW,
RST will reset the DAC register to min-scale.

LOW.
Negative Analog Power Supply

SS

OUT

), active

DAC7731

SBAS249

www.ti.com

3

TIMING CHARACTERISTICS

VCC = +15V, V

PARAMETER DESCRIPTION MIN TYP MAX UNITS

t

WH

t

WL

t

SDI

t

HDI

t

SCS

t

HSC

t

DDO

t

HDO

t

DDOZ

t

WCSH

t

WLDL

t

WLDH

t

SLD

t

DLD

t

SCLK

t

SRS

t

HRS

t

WRL

t

INTERFACE TIMING

= –15V, VDD = 5V; RL = 2kΩ to AGND; CL = 200pF to AGND; all specifications –40°C to +85°C, unless otherwise noted.

SS

DAC7731

SCLK HIGH Time 25 ns
SCLK LOW Time 25 ns
Setup Time: Data in valid before rising SCLK 5 ns
Hold Time: Data in valid after rising SCLK 20 ns
Setup Time: CS falling edge before first rising SCLK 15 ns
Hold Time: CS rising edge after 16th rising SCLK 0 ns
Delay Time: CS Falling Edge to Data Out valid, CL = 20pF on SDO 50 ns
Hold Time: Data Out valid after SCLK rising edge, CL 20pF on SDO 50 ns
Delay Time: CS rising edge to SDO = High Impedance 70 ns
CS HIGH Time 50 ns
LDAC LOW Time 20 ns
LDAC HIGH Time 20 ns
Setup Time: 16th Rising SCLK Before LDAC Rising Edge 15 ns
Delay Time: LDAC rising edge to first SCLK rising edge of next 15 ns
transfer cycle.
Setup Time: CS High before falling SCLK edge following 16th 5 ns
rising SCLK edge
Setup Time: RSTSEL Valid Before RST LOW 0 ns
Hold Time: RSTSEL valid after RST HIGH 20 ns
RST LOW Time 30 ns

S

DAC V

Settling Time 5 µs

OUT

SCLK

SDO

LDAC

V

RESET TIMING

SDI

OUT

CS

t

SCS

t

WH

12 16

t

Word B

Word A

t

SRS

WL

t

t

HDI

HDO

t

SDI

B15 B14 B13 B0

t

DDO

A15 A14 A13 A0

RSTSEL

RST

+FS

(RSTSEL = LOW)

V

OUT

–FS
+FS

(RSTSEL = HIGH)

V

OUT

–FS

t

HCS

t

t

HRS

WRL

t

DDOZ

t

WCSH

t

SCLK

C15 C14 C13 C12

Word C

B15 B14 B13 B12

t

t

WLDL

t

SLD

DLD

t

WLDH

±0.003% of FSR

Error Bands

t

S

t

S

Word B

Min-Scale

Mid-Scale

4

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DAC7731

SBAS249

TYPICAL CHARACTERISTICS

TA = +25°C (unless otherwise noted).

6
4
2
0

–2

INL (LSB)

Bipolar Configuration: V

–4

T

= 85°C, Internal Reference Enabled

A

–6

2.0

1.5

1.0

0.5

0.0

–0.5

DNL (LSB)

–1.0
–1.5
–2.0

0000

H

6
4
2
0

–2

INL (LSB)

Bipolar Configuration: V

–4

T

= –40°C, Internal Reference Enabled

A

–6

2.0

1.5

1.0

0.5

0.0

–0.5

DNL (LSB)

–1.0
–1.5
–2.0

0000

H

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

= –10V to +10V

OUT

2000H4000H6000H8000

A000

H

C000HE000HFFFF

H

Digital Input Code

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

= –10V to +10V

OUT

2000H4000H6000H8000

H

A000

C000HE000HFFFF

H

Digital Input Code

LINEARITY ERROR AND DIFFERENTIAL

6

LINEARITY ERROR vs DIGITAL INPUT CODE

4
2
0

–2

INL (LSB)

Bipolar Configuration: V

–4

T

= 25°C, Internal Reference

A

–6

2.0

1.5

1.0

0.5

0.0

–0.5

DNL (LSB)

–1.0
–1.5
–2.0

H

2000H4000H6000H8000

0000

H

= –10V to +10V

OUT

Enabled

A000

H

C000HE000HFFFF

H

H

Digital Input Code

1.00

OFFSET ERROR vs TEMPERATURE

0.75
V

= –10 to +10V

0.50

0.25

V

OUT

= 0 to +10V

OUT

0.00

–0.25

Error (mV)

–0.50
–0.75
–1.00

H

–40 –15 10 35 60 85

Temperature (°C)

0.000

–0.010
–0.020
–0.030
–0.040
–0.050

Error (%)

–0.060

Ext. Ref, Unipolar Mode: V

Int. Ref, Unipolar Mode: V

GAIN ERROR vs TEMPERATURE

= 0 to +10V

OUT

Ext. Ref, Bipolar Mode: V

= 0 to +10V

OUT

–0.070
–0.080
–0.090
–0.100

Load = 200pF, 2kΩ

Int. Ref, Bipolar Mode: V

–40 –15 10 35 60 85

Temperature (°C)

DAC7731

SBAS249

= –10 to +10V

OUT

= –10 to +10V

OUT

www.ti.com

VCC SUPPLY CURRENT vs DIGITAL INPUT CODE

4.4

4.3

Bipolar Configuration: V
Internal Reference Enabled, T

4.2

4.1

(mA)

4.0

CC

I

3.9

3.8

3.7

0000H2000H4000H6000H8000

A000

H

Digital Input Code

= –10V to +10V

OUT

= 25°C

A

C000HE000HFFFF

H

H

5

TYPICAL CHARACTERISTICS (Cont.)

TA = +25°C (unless otherwise noted).

VCC SUPPLY CURRENT vs DIGITAL INPUT CODE

3.4

3.3

Bipolar Configuration: V
External Reference, REFEN = 5V, T

= –10V to +10V

OUT

3.2

3.1

(mA)

3.0

CC

I

2.9

2.8

2.7

0000H2000H4000H6000H8000

A000

H

C000HE000HFFFF

H

Digital Input Code

7
6
5

SUPPLY CURRENT vs TEMPERATURE

Load Current Excluded
V

= +15V, VSS = –15V

CC

Bipolar V

Configuration: –10V to +10V

OUT

4
3

I

(mA)

SS

, I

CC

I

–1
–2

CC

2
1
0

I

SS

–3

–40 –15 10 35 60 85

Temperature (°C)

= 25°C

A

–1.50

VSS SUPPLY CURRENT vs DIGITAL INPUT CODE

–1.75

–2.00

(mA)

SS

I

–2.25

–2.50

Bipolar Configuration: V
T

= 25°C

–2.75

H

A

0000H2000H4000H6000H8000

= –10V to +10V

OUT

A000

H

C000HE000HFFFF

H

H

Digital Input Code

1800
1600
1400
1200

SUPPLY CURRENT vs LOGIC INPUT VOLTAGE

TA = 25°C, Transition
Shown for a Single
Input (Applies to CS,
SCLK,D
inputs)

and LDAC

IN

1000

(µA)

800

DD

I

600
400
200

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V

(V)

LOGIC

HISTOGRAM OF VCC CURRENT CONSUMPTION

100

Bipolar Output Configuration

90

Internal Reference Enabled
Code = 5555

80

H

70
60
50
40

Frequency

30
20
10

0

3.000 3.500 4.000 4.500 5.000
(mA)

I

CC

6

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100

HISTOGRAM OF VSS CURRENT CONSUMPTION

Bipolar Output Configuration

90

Internal Reference Enabled
Code = 5555

80

H

70
60
50
40

Frequency

30
20
10

0

–3.50 –3.00 –2.50 –2.00 –1.50

I

(mA)

SS

DAC7731

SBAS249

TYPICAL CHARACTERISTICS (Cont.)

10.015

10.010

10.005

10.000

9.995

9.990

9.985

REF

OUT

(V)

–40 –15 10 35 60 85

Temperature (°C)

INTERNAL REFERENCE OUTPUT vs TEMPERATURE

Source

Sink

OUTPUT VOLTAGE vs R

LOAD

12

8

4

0

–4

–8

–12

V

OUT

(V)

0.0 0.1 1.0 10.0 100.0
R

LOAD

(kΩ)

TA = +25°C (unless otherwise noted).

POWER-SUPPY REJECTION RATIO vs FREQUENCY

10

Bipolar Configuration: ±10V V

0

Code 8000

–VSS, VCC = 15V + 1Vp-p

–10

V

–20

H

= 5V + 0.5Vp-p

DD

(Measured at V

OUT

OUT

)

–30
–40

PSRR (dB)

–50
–60

V

SS

V

CC

–70

V

–80

DD

0.1K 1K 10K 100K 1M 10M
Frequency (Hz)

INTERNAL REFERENCE START-UP

15V

(5V/div)

0V

CC

V

POWER-SUPPY REJECTION RATIO vs FREQUENCY

10

Bipolar Configuration: ±10V V

0

–VSS, VCC = 15V + 1Vp-p, VDD = 5V + 0.5Vp-p

(Measured at V

OUT

, Code FFFF

OUT

)

H

–10
–20
–30
–40

PSRR (dB)

–50
–60

V

SS

V

CC

V

DD

–70
–80

0.01K 0.1K 1K 10K 100K 1M 10M
Frequency (Hz)

10V

(2V/div)

OUT

0V

REF

VOLTAGE vs LOAD

REF

11.0

OUT

Loaded to V

10.5

10.0

(V)

OUT

9.5

REF

9.0

8.5
1 10 100 1K

Loaded to AGND

REF

DAC7731

SBAS249

Time (2ms/div)

CC

LOAD(kΩ)

OUT

V

CC

= +15V

www.ti.com

7

TYPICAL CHARACTERISTICS (Cont.)

TA = +25°C (unless otherwise noted).

POWER-SUPPY REJECTION RATIO vs FREQUENCY

10

Internal Reference Enabled

0

–V

, VCC = 15V + 1Vp-p,

SS

V

= 5V + 0.5Vp-p

DD

–10
–20
–30
–40

PSRR (dB)

–50

(Measured at REF

V

SS

)

OUT

V

CC

V

DD

–60
–70
–80

1 10 100 1K 10K 100K 1M 10M

Frequency (Hz)

800

Bipolar Configuration: ±10V, Internal Reference Enabled

OUTPUT NOISE vs FREQUENCY

700
600
500
400
300
200

Output Noise (nV/rtHz)

100

Code 0000

Code 8000

H

H

Code FFFF

H

0

0.01K 0.1K 1K 10K 100K 1M 10M
Frequency (Hz)

900

Unipolar Configuration, Internal Reference Enabled

800

OUTPUT NOISE vs FREQUENCY

700
600
500

Code FFFF

H

400
300

Output Noise (nV/Hz)

200

Code 0000

100

H

0

0.01K 0.1K 1K 10K 100K 1M 10M
Frequency (Hz)

BROADBAND NOISE

(V, 50µV/div)

OUT

V

Internal Reference Enabled
Filtered with 1.6Hz Low-Pass
Code FFFF
10kHz Measurement BW

, Bipolar ±10V Configuration

H

Time (100µs/div)

UNIPOLAR FULL-SCALE SETTLING TIME

Large-Signal Output (5V/div)

Small-Signal Error (150µV/div)

Unipolar Configuration: V

Zero-Scale to +Full-Scale Change

= 0 to +10V

OUT

5kΩ, 200pF Load

Time (2µs/div)

8

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BIPOLAR FULL-SCALE SETTLING TIME

Large-Signal Output (5V/div)

Small-Signal Error (300µV/div)

Bipolar Configuration: V

–Full-Scale to +Full-Scale

= –10 to +10V

OUT

5kΩ, 200pF Load

Time (2µs/div)

DAC7731

SBAS249

TYPICAL CHARACTERISTICS (Cont.)

TA = +25°C (unless otherwise noted).

UNIPOLAR FULL-SCALE SETTLING TIME

Small-Signal Error (150µV/div)

Large-Signal Output (5V/div)

Unipolar Configuration: V

+Full-Scale to Zero-Scale Change

Time (2µs/div)

MID-SCALE GLITCH

Code 8000H to 7FFF
Bipolar Configuration: ±10V V

H

OUT

= 0V to +10V

OUT

5kΩ, 200pF Load

BIPOLAR FULL-SCALE SETTLING TIME

Small-Signal Error (300µV/div)

Large-Signal Output (5V/div)

Bipolar Configuration: V

+Full-Scale to –Full-Scale

Time (2µs/div)

MID-SCALE GLITCH

Code 7FFFH to 8000

Bipolar Configuration: ±10V V

= –10 to +10V

OUT

5kΩ, 200pF Load

H

OUT

(V, 100mV/div)

OUT

V

Time (1µs/div)

(V, 100mV/div)

OUT

V

Time (1µs/div)

DAC7731

SBAS249

www.ti.com

9

THEORY OF OPERATION

The DAC7731 is a voltage output, 16-bit DAC with a +10V
built-in internal reference. The architecture is an R-2R ladder
configuration with the three MSB’s segmented, followed by
an operational amplifier that serves as a buffer, as shown in
Figure 1. The output buffer is designed to allow user­configurable output adjustments giving the DAC7731 output
voltage ranges of 0V to +10V, –5V to +5V, or –10V to +10V.
Please refer to Figures 2, 3, and 4 for pin configuration
information.

The digital input is a serial word made up of the DAC code
(MSB first) and is loaded into the DAC register using the
LDAC input pin. The converter can be powered from ±12V
to ±15V dual analog supplies and a +5V logic supply. The
device offers a reset function, which immediately sets the
DAC output voltage and DAC register to min-scale (code
0000

) or mid-scale (code 8000H). The data I/O and reset

H

functions are discussed in more detail in the following sec­tions.

R

2R2R 2R 2R 2R 2R 2R 2R 2R

FIGURE 1. DAC7731 Architecture.

V

CC

(0V to +10V)

V

DD

1µF0.1µF

1
2
3
4
5
6
7
8

9
10
11
12

DAC7731

V

CC

REF

OUT

REF

IN

REFADJ
V

REF

R

OFFSET

AGND
RFB2
RFB1
SJ
V

OUT

V

DD

REFEN

RSTSEL

SCLK

SDO

LDAC

TEST

DGND

V

CS

SDI

RST

NC

REF

ADJ

REF

OUT

REF

IN

V

REF

R

OFFSET

RFB2

Buffer

R/4

RFB1

+10V Internal

Reference

R/2R/2 R/4

SJ

V

OUT

R/4

V

REF

AGND

V

CC

1
2
3
4
5
6
7
8

9
10
11
12

V

CC

REF

OUT

REF

IN

REFADJ
V

REF

R

OFFSET

AGND
RFB2
RFB1
SJ
V

OUT

V

DD

DAC7731

V

REFEN

RSTSEL

SCLK

CS

SDO

SDI

LDAC

RST

NC

TEST

DGND

24

SS

23
22
21
20

Control/Data

19

Bus

18
17
16
15
14
13

V

24

SS

23
22
21
20

Control/Data

19

Bus

18
17
16
15
14
13

SS

1µF0.1µF

(–5V to +5V)

V

DD

1µF0.1µF

V

SS

1µF0.1µF

1µF0.1µF

FIGURE 2. Basic Operation: V

10

= 0V to +10V.

OUT

FIGURE 3. Basic Operation: V

www.ti.com

1µF0.1µF

= –5V to +5V.

OUT

DAC7731

SBAS249

V

CC

1µF0.1µF

(–10V to +10V)

V

DD

REFSEL ACTION

DAC7731

V

1

CC

REF

2

OUT

REF

3

IN

REFADJ

4

V

5

REF

R

6

OFFSET

AGND

7

RFB2

8

RFB1

9

SJ

10

V

11

OUT

V

12

DD

1µF0.1µF

V

REFEN

RSTSEL

SCLK

CS

SDO

SDI

LDAC

RST

NC

TEST

DGND

24

SS

23
22
21
20

Control/Data

19

Bus

18
17
16
15
14
13

V

SS

1µF0.1µF

1 Internal Reference disabled;

0 Internal Reference enabled;

REF

= High Impedance

OUT

REF

OUT

= +10V

TABLE I. REFEN Action.

DIGITAL INTERFACE

Table II shows the input data format for the DAC7731 and
Table III illustrates the basic control logic of the device. The
serial interface consists of a chip select input (CS), serial data
clock input (SCLK), serial data input (SDI), serial data output
(SDO), and load control input (LDAC). An asynchronous reset
input (RST), which is active LOW, is provided to simplify start­up conditions, periodic resets, or emergency resets to a known
state, depending on the status of the reset select (RSTSEL)
signal. Please refer to the "DAC Reset" section for additional
information regarding the reset operation.

FIGURE 4. Basic Operation: V

= –10V to +10V.

OUT

ANALOG OUTPUTS

The output amplifier can swing to within 1.4V of the supply
rails, specified over the –40°C to +85°C temperature range.
This allows for a ±10V DAC voltage output operation from
±12V supplies with a typical 5% tolerance.

When the DAC7731 is configured for a unipolar, 0V to 10V
output, a negative voltage supply is required. This is due to
internal biasing of the output stage. Please refer to the
“Electrical Characteristics” table for more information.

The minimum and maximum voltage output values are de­pendent upon the output configuration implemented and
reference voltage applied to the DAC7731. Please note that
V

(the negative power supply) must be in the range of

SS

–4.75V to –15.75V for unipolar operation. The voltage on V
sets several bias points within the converter and is required
in all modes of operation. If V

is not in one of these two

SS

configurations, the bias values may be in error and proper
operation of the device is not ensured.

REFERENCE INPUTS

The DAC7731 provides a built-in +10V voltage reference and
on-chip buffer to allow external component reference drive. To
use the internal reference, REFEN must be LOW, enabling the
reference circuitry of the DAC7731 (as shown in Table I) and
the REF
to the on-chip reference buffer. The buffer’s output is provided
at the V
DAC7731 output amplifier into one of three voltage output
modes as discussed earlier. V
other system components requiring an external reference.

The internal reference of the DAC7731 can be disabled when
use of an external reference is desired. When using an
external reference, the reference input, REF
voltage between 4.75V (or V
and V

pin must be connected to REFIN. This is the input

OUT

pin. In this configuration, V

REF

– 1.4V.

CC

REF

+ 14V, whichever is greater)

SS

is used to setup the

REF

can also be used to drive

, can be any

IN

SS

ANALOG OUTPUT

DIGITAL INPUT Unipolar Configuration Bipolar Configuration

Unipolar Straight Binary Bipolar Offset Binary
0x0000 Zero (0V)
0x0001 Zero + 1LSB –Full-Scale + 1LSB

:: :
0x8000 1/2 Full-Scale Bipolar Zero
0x8001 1/2 Full-Scale + 1LSB Bipolar Zero + 1LSB

:: :

0xFFFF Full-Scale (V

– 1LSB) +Full-Scale (+V

REF

–Full-Scale (–V

or +V

REF

or –V

REF

– 1LSB

REF

/2 – 1LSB)

REF

/2)

TABLE II. DAC7731 Data Format.

CONTROL STATUS COMMAND

CS RST RSTSEL LDAC SCLK ACTION

H H X X X Shift Register is disabled on the serial bus.

L H X X X enables shift operation and I/O bus

LH X X ↑ Serial Data Shifted into Input Register
↑ H X X L Serial Data Shifted into Input Register
XH X ↑ X
X L H X X Resets Input and DAC Registers to mid-scale.
X L L X X Resets Input and DAC Registers to min-scale.

NOTE: (1) In order to avoid unwanted shifting of the input register by an
additional bit, care must be taken that a rising edge on CS only occurs
when SCLK is HIGH.

Enable SDO pin from High Impedance;

(SCLK, SDI, SDO).

(1)

Data in Input Register is Loaded into DAC Register.

TABLE III. DAC7731 Logic Truth Table.

The DAC code is provided via a 16-bit serial interface, as shown
in Table II. The digital input word makes up the digital code to
be loaded into the data input register of the device. A typical
data transfer and DAC output update takes place as follows:
Once CS is active (LOW), the DAC7731 is enabled on the serial
bus and the 16-bit serial data transfer can begin. The serial data
is shifted into the device on each rising SCLK edge until all 16
bits are transferred (1 bit per 1 rising SCLK edge). Once
received, the data in the input register is loaded into the DAC
register upon reception of a rising edge on the LDAC input (load
command). This action updates the analog output, V

OUT

, to the

desired voltage specified by the digital input word. A rising edge

DAC7731

SBAS249

www.ti.com

11

on LDAC is completely asynchronous to the serial interface of
the device and can occur at any time. Care must be taken to
ensure that the entire 16 bits of data are loaded into the input
register before issuing a LDAC active edge. Additional load
commands will have no effect on the DAC output if the data in
the input register is unchanged between rising LDAC edges.
When CS is returned HIGH, the rising edge on CS must
occur when SCLK is HIGH. Application of a rising CS edge
when SCLK is LOW will cause one additional shift in the
serial input shift register, corrupting the desired input data.

TIMING CONSIDERATIONS

The flexible interface of the DAC7731 can operate under a
number of different scenarios as is required by a host
controller. Critical timing for a 16-bit data transfer cycle is
shown in the Interface Timing section of the Timing Charac­teristics. While this is the most common method of writing to
the DAC7731, the device accepts two additional modes of
data transfer from the host. These are byte transfer mode
and continuous transfer mode.

CS

Most Significant Byte Least Significant Byte

Byte transfer mode is especially useful when an 8-bit host is
communicating with the DAC. Data transfer can occur with­out requiring an additional general purpose I/O pin to control
the CS input of the DAC in cycles of 16 clocks. A HIGH state
on CS stops data from coming into and out of the internal
shift register. This provides byte-wide support for 8-bit host
processors. Figure 5 is an example of the timing cycle of
such a data transfer.

The remaining data transfer mode accepted by the DAC7731
is continuous transfer. The CS of the DAC7731 can be tied
LOW or held LOW by the controller for an indefinite number of
serial clock cycles. Each clock cycle will transfer data into the
DAC via SDI and out of the DAC on SDO. Care must be taken
that the LDAC signal to the DAC(s) is timed correctly so that
valid data is transferred into the DAC register on each rising
LDAC edge. ("Valid data" refers to the serial data latched on
each of the 16 rising SCLK edges prior to the occurrence of a
rising LDAC signal.) The rising edge of LDAC must occur
before the first rising SCLK edge of the following 16-bit

transfer. Figure 6 shows continuous transfer timing.

16-Bit Data Word

SCLK

SDI

SDO

LDAC

12 8 910

B15

B14 B13 B8 B7 B6 B0

Byte 1, Word N

A15 A14 A13 A8

Byte 1, Word N – 1

FIGURE 5. Byte-Wide Data Write Cycle.

CS

SCLK

SDI

1 2 16 1 2 16 1 2

B15 B14 B1 B0 C15 C14 C1 C0 D15 D14

16

Byte 2, Word N

A7

A6

Byte 2, Word N – 1

Word N Word N + 1 Word N + 2

A0

SDO

Word N – 1 Word N Word N + 1

LDAC

FIGURE 6. Continuous Transfer Control.

12

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C14C15B0B1B14B15A0A1A14A15

DAC7731

SBAS249

DAISY-CHAINING USING SDO

Multiple DAC7731’s can be connected to a single serial port
by attaching each of their control inputs in parallel and daisy­chaining the SDO and SDI I/O's of each device. The SDO
output of the DAC7731 is active when CS is LOW and can
be left unconnected when not required for use in a daisy­chain configuration.

Once a data transfer cycle begins, new data is shifted into SDI
and data currently residing in the shift register (from previous
cycle, power-up, or reset command) is presented on SDO, MSB
first. One data transfer cycle for each DAC7731 is required to
update all devices in the chain. The first data cycle written into
the chain will arrive at the last DAC7731 on the final cycle of the
data transfer. Upon completion of the required number of data
transfer cycles (one cycle per device), each DAC voltage output
is updated with a rising edge on the LDAC inputs.
Figure 8 shows the required timing to properly update two

From Host

Controller

DAC7731’s in a daisy-chained configuration, as shown in
Figure 7.

DAC RESET

The RST and RSTSEL inputs control the reset of the analog
output. The reset command is level triggered by a low signal on
RST. Once RST is LOW, the DAC output will begin settling to
the mid-scale or min-scale code depending on the state of the
RSTSEL input. A HIGH value on RSTSEL will cause V
reset to the mid-scale code (8000
V

to min-scale (8000H). A change in the state of the RSTSEL

OUT

) and a LOW value will reset

H

input while RST is LOW will cause a corresponding change in
the reset command selected internally and consequently change
the output value of V

of the DAC. Note that a valid reset

OUT

signal also resets the input register of the DAC to the value
specified by the state of RSTSEL.

OUT

To next
DAC7731

to

DAC7731

V

1

CC

REF

2

OUT

REF

3

IN

REFADJ

4

V

5

REF

R

6

OFFSET

AGND

7

RFB2

8

RFB1

9

SJ

10

V

11

OUT

V

12

DD

First Device in Chain Second Device in Chain

V

REFEN

RSTSEL

SCLK

CS

SDO

SDI

LDAC

RST

NC

TEST

DGND

24

SS

23
22
21
20
19
18
17
16
15
14
13

FIGURE 7. DAC7731 Daisy-Chain Schematic.

SCLK

12 1216 16

DAC7731

V

1

CC

REF

2

OUT

REF

3

IN

REFADJ

4

V

5

REF

R

6

OFFSET

AGND

7

RFB2

8

RFB1

9

SJ

10

V

11

OUT

V

12

DD

LSBs latched LSBs latched

V

REFEN

RSTSEL

SCLK

CS

SDO

SDI

LDAC

RST

NC

TEST

DGND

24

SS

23
22
21
20
19
18
17
16
15
14
13

Both DAC V

are updated

OUT

's

CS

LDAC

First Data Transfer Cycle

SDI A15 A14 A0

Previous cycle word from host

(to DAC7731 B SDI)

SDO

XX X

FIGURE 8. DAC7731 Daisy-Chain Timing for Figure 7.

DAC7731

SBAS249

www.ti.com

B15 B14 B1 B0

A15 A14 A1 A0

13

APPLICATIONS

REFADJ

V

REF

R

OFFSET

AGND

RFB2

RFB1

SJ

4

5

6

7

8

9

10

DAC7731

Optional Gain

Adjust

Optional Offset

Adjust

R

1

R

POT2

R

POT1

R

S

V

OADJ

(Other Connections Omitted

for Clarity)

+

–

I

SJ

GAIN AND OFFSET CALIBRATION

The architecture of the DAC7731 is designed in such a way
as to allow for easily configurable offset and gain calibration
using a minimum of external components. The DAC7731
has built-in feedback resistors and output amplifier summing
points brought out of the package in order to make the
absolute calibration possible. Figures 9 and 10 illustrate the
relationship of offset and gain adjustments for the DAC7731
in a unipolar configuration and in a bipolar configuration,

respectively.

(+V

)

REF

+ Full Scale

1LSB

Gain Adjust

Rotates
the Line

should be at +10V – 1LSB for the 0V to +10V or ±10V output
range and +5V – 1LSB for the ±5V output range. Figure 11
shows the generalized external offset and gain adjustment
circuitry using potentiometers.

Analog Output

Zero Scale

(AGND)

Offset Adjust Translates the Line

FIGURE 9. Relationship of Offset and Gain Adjustments for

+ Full
Scale

Input =

0000

H

Analog Output

FIGURE 10. Relationship of Offset and Gain Adjustments for

When calibrating the DAC’s output, offset should be adjusted
first to avoid first order interaction of adjustments. In unipolar
mode, the DAC7731’s offset is adjusted from code 0000
and for either bipolar mode, offset adjustments are made at
code 8000
FFFF

H

for each configuration, where the output of the DAC

H

14

Input =

Full Scale Range

0000

H

Digital Input

V

= 0V to +10V Output Configuration.

OUT

(+V

or +V

REF

Input = 8000

– Full-Scale
(–V

REF

OUT

/2)

Gain

Adjust

Rotates

the Line

Input =

FFFF

H

OR –V

REF

= –5V to +5V.)

REF

1LSB

Range

Full Scale

Digital Input

V

= –10V to +10V Output Configuration. (Same

OUT

Theory Applies for V

. Gain adjustment can then be made at code

H

/2)

Input =
FFFF

H

Offset
Adjust
Translates
the Line

FIGURE 11. Generalized External Calibration Circuitry for

OFFSET ADJUSTMENT

Offset adjustment is accomplished by introducing a small
current into the summing junction (SJ) of the DAC7731. The
voltage at SJ, or V
tion of the DAC7731. See Table IV for the required pin
strapping for a given configuration and the nominal values of

V

TABLE IV. Nominal VSJ versus V

The current level required to adjust the DAC7731’s offset can
be created by using a potentiometer divider as shown in
Figure 11 Another alternative is to use a unipolar DAC in order
to apply a voltage, V
range applied to SJ will ensure offset adjustment coverage of
the ±0.1% maximum offset specification of the DAC7731.

When in a unipolar configuration (V
resistor, R
a 0V to 10V V
configurations, V

H

(±5V range), and circuit values chosen to match those given
in Table V will provide symmetrical offset adjust. Please refer

to Figure 11 for component configuration.

www.ti.com

Gain and Symmetrical Offset Adjustment.

, is dependent on the output configura-

SJ

for each output range.

SJ

REFERENCE OUTPUT PIN STRAPPING V
CONFIGURATION

Internal 0V to +10V to V
Reference –10V to +10V NC NC to V

External 0V to V
Reference –V

NOTE: (1) Voltage measured at V

CONFIGURATION R

–5V to +5V to AGND to V

REF

to V

REF

–V

/2 to V

REF

OFFSET

to V

REF
REF

NC NC to V

/2 to AGND to V

for a given configuration.

SJ

OUT

RFB1 RFB2

to V

to V

OUT

OUT
OUT

OUT

to V

OUT
OUT

to V

OUT

to V

OUTVREF
OUTVREF

to V

OUTVREF

+3.333V
+1.666V

REF

REF

and Reference Configu-

ration.

, to the resistor RS. A ±2uA current

OADJ

= 5V), only a single

, is needed for symmetrical offset adjustment with

S

range. When in one of the two bipolar

OADJ

is either +3.333V (±10V range) or +1.666V

SJ

SJ

DAC7731

SBAS249

SJ

+5V

(1)

/2
/3
/6

V

CC

REF

OUT

REF

IN

REFADJ
V

REF

R

OFFSET

AGND
RFB2
RFB1
SJ
V

OUT

V

DD

V

SS

REFEN

RSTSEL

SCLK

CS

SDO

SDI

LDAC

RST

NC

TEST

DGND

1
2
3
4
5
6
7
8

9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

DAC7731

100kΩ

1.0µF

(Other connections omitted for clarity.)

Low-Pass Reference Filter

OUTPUT R
CONFIGURATION RANGE OFFSET

0V to +10V 10K 0 2.5M ±2µA ±25mV

–10V to +10V 10K 5K 1.5M ±2.2µA ±55mV
–5V to +5V 10K 20K 1M ±1.7µA ±21mV

POT2R1

R

I

S

SJ

NOMINAL

ADJUSTMENT

TABLE V. Recommended External Component Values for

Symmetrical Offset Adjustment (V

REF

= 10V).

Figure 12 illustrates the typical minimum offset adjustment
ranges provided by forcing a current at SJ for a given output
voltage configuration.

50

(mV)

25

OUT

typ

0

min (75% of typ)
0V to 10V and –5V to +5V

–25

V

OUT

Offset Adjustment at V

Configuration

OFFSET ADJUST RANGE

–10V to +10V V

typ

Configuration

min (75% of typ)

OUT

REF

ADJUST RANGE

40
30
20
10

Minimum REF

0

Adjustment (mV)

OUT

REF

Adjustment Range

–10
–20
–30
–40

0246810

OUT

Typical REF

Adjustment Range

OUT

OUT

REFADJ (V)

FIGURE 13. Internal Reference Adjustment Transfer Charac-

teristic.

VOLTAGE AT REFADJ REF

REFADJ = 0V 10V + 25mV (min)

REFADJ = 5V or NC

REFADJ = 10V 10V – 25mV (max)

NOTE: "NC" is "Not Connected"

(1)

VOLTAGE

OUT

10V

TABLE VI. Minimum Internal Reference Adjustment Range.

FIGURE 12. Offset Adjustment Transfer Characteristic.

GAIN ADJUSTMENT

When using the internal reference of the DAC7731, gain
adjustment is performed by adjusting the device’s internal
reference voltage via the reference adjust pin, REFADJ. The
effect of a reference voltage change on the gain of the DAC
output can be seen in the generic equation (for unipolar
configuration):

Where N is represented in decimal format and ranges from
0 to 65535.

REFADJ can be driven by a low impedance voltage source
such as a unipolar, 0V to +10V DAC or a potentiometer (less
than 100kΩ), see Figure 11. Since the input impedance of
REFADJ is typically 50kΩ, the smaller the resistance of the
potentiometer, the more linear the adjustment will be. A 10kΩ
potentiometer is suggested if linearity of the reference adjust­ment is of concern.

When the DAC7731’s internal reference is not used, gain
adjustments can be made via trimming the external refer­ence applied to the DAC at REF
through using a potentiometer, unipolar DAC, or other means
of precision voltage adjustment to control the voltage pre­sented to the DAC7731 by the external reference. Figure 13
and Table VI summarize the range of adjustment of the
internal reference via REFADJ.

DAC7731

–50

–220–11

ISJ (µA)

V

SBAS249

OUT

= V

REFIN

• (N/65536)

. This can be accomplished

IN

NOISE PERFORMANCE

Increased noise performance of the DAC output can be
achieved by filtering the voltage reference input to the DAC7731.
Figure 14 shows a typical internal reference filter schematic. A
low-pass filter applied between the REF
increase noise immunity at the DAC and output amplifier. The
REF
taken in order to avoid overloading the internal reference output.

FIGURE 14. Filtering the Internal Reference.

www.ti.com

and REFIN pins can

OUT

pin can source a maximum of 50µA so care should be

OUT

15

LAYOUT

A precision analog component requires careful layout, adequate
bypassing, and clean, well-regulated power supplies. The
DAC7731 offers separate digital and analog supplies, as it will
often be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more digital
logic present in the design and the higher the switching speed,
the more important it will become to separate the analog and
digital ground and supply planes at the device.

Since the DAC7731 has both analog and digital ground pins,
return currents can be better controlled and have less effect
on the DAC output error. Ideally, AGND would be connected
directly to an analog ground plane and DGND to the digital
ground plane. The analog ground plane would be separate
from the ground connection for the digital components until
they were connected at the power-entry point of the system.

The voltages applied to V
and low noise. Switching power supplies and DC/DC convert­ers will often have high-frequency glitches or spikes riding on
the output voltage. In addition, digital components can create
similar high-frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
voltage through various paths between the power connec­tions and analog output.

In addition, a 1µF to 10µF bypass capacitor in parallel with a

0.1µF bypass capacitor is strongly recommended for each
supply input. In some situations, additional bypassing may be
required, such as a 100µF electrolytic capacitor or even a "Pi"
filter made up of inductors and capacitors–all designed to
essentially low-pass filter the analog supplies, removing any
high frequency noise components.

and VSS should be well regulated

CC

16

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DAC7731

SBAS249

PACKAGE DRAWING

MSSO002D – JANUARY 1995 – REVISED SEPTEMBER 2000

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65

28

1

2,00 MAX

0,38
0,22

15

14

A

0,05 MIN

0,15

5,60
5,00

M

8,20
7,40

Seating Plane

0,10

0,15 NOM

Gage Plane

0°–8°

0,25

0,95
0,55

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

14

6,50

6,50

5,905,90

2016

7,50

6,90

24

8,50

28

10,50

9,907,90

30

10,50

9,90

38

12,90

12,30

4040065 /D 09/00

DAC7731

SBAS249

www.ti.com

17

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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