®
For most current data sheet and other product
information, visit www.burr-brown.com
12-Bit, Parallel Input
DIGITAL-TO-ANALOG CONVERTER
DAC7621
®
DAC7621
FEATURES
● LOW POWER: 2.5mW
● FAST SETTLING: 7µs to 1 LSB
● 1mV LSB WITH 4.095V FULL-SCALE
RANGE
● COMPLETE WITH REFERENCE
● 12-BIT LINEARITY AND MONOTONICITY
OVER INDUSTRIAL TEMP RANGE
● ASYNCHRONOUS RESET TO 0V
APPLICATIONS
● PROCESS CONTROL
● DATA ACQUISITION SYSTEMS
● CLOSED-LOOP SERVO-CONTROL
● PC PERIPHERALS
● PORTABLE INSTRUMENTATION
DESCRIPTION
The DAC7621 is a 12-bit digital-to-analog converter
(DAC) with guaranteed 12-bit monotonicity performance over the industrial temperature range. It requires a single +5V supply and contains an input
register, latch, 2.435V reference, DAC, and high speed
rail-to-rail output amplifier. For a full-scale step, the
output will settle to 1 LSB within 7µs. The device
consumes 2.5mW (0.5mA at 5V).
The parallel interface is compatible with a wide variety
of microcontrollers. The DAC7621 accepts a 12-bit
parallel word, has a double-buffered input logic structure and provides data readback. In addition, two
control pins provide a chip select (CS) function and
asynchronous clear (CLR) input. The CLR input can
be used to ensure that the DAC7621 output is 0V on
power-up or as required by the application.
The DAC7621 is available in a 20-lead SSOP package
and is fully specified over the industrial temperature
range of –40°C to +85°C.
V
DD
SBAS107
Ref
CLR
LOADDAC
CS
R/W
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1998 Burr-Brown Corporation PDS-1502B Printed in U.S.A. March, 1999
12-Bit DAC
12
DAC Register
12
Input Register
12
I/O Buffer
DGND
DAC7621
V
OUT
SPECIFICATIONS
ELECTRICAL
At TA = –40°C to +85°C, and VDD = +5V, unless otherwise noted.
DAC7621E DAC7621EB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 12 ✻ Bits
ACCURACY
Relative Accuracy
Differential Nonlinearity Guaranteed Monotonic –1 ±1/2 +1 –1 ±1/4 +1 LSB
Zero-Scale Error Code 000
Full Scale Voltage Code FFF
ANALOG OUTPUT
Output Current Code 800
Load Regulation R
Capacitive Load No Oscillation 500 ✻ pF
Short-Circuit Current ±20 ✻ mA
Short-Circuit Duration GND or V
DIGITAL INPUT
Data Format Parallel ✻
Data Coding Straight Binary ✻
Logic Family CMOS ✻
Logic Levels
V
IH
V
IL
I
IH
I
IL
DYNAMIC PERFORMANCE
Settling Time
DAC Glitch 5 ✻ nV-s
Digital Feedthrough 2 ✻ nV-s
POWER SUPPLY
V
DD
I
DD
Power Dissipation V
Power Supply Sensitivity ∆V
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻°C
(1)
H
H
≥ 402Ω, Code 800
LOAD
H
H
DD
–2 ±1/2 +2 –1 ±1/4 +1 LSB
–1 +1 +3 ✻✻✻ LSB
4.079 4.095 4.111 4.087 4.095 4.103 V
±5 ±7 ✻✻ mA
13 ✻✻ LSB
Indefinite ✻
0.7 • V
DD
0.3 • V
±10 ✻ µA
✻ V
DD
✻ V
±10 ✻ µA
(2)
(tS) To ±1 LSB of Final Value 7 ✻ µs
+4.75 +5.0 +5.25 ✻✻✻ V
VIH = 5V, VIL = 0V, No Load, at Code 000
= 5V, VIL = 0V, No Load 2.5 5 ✻✻ mW
IH
= ±5% 0.001 0.004 ✻✻%/%
DD
H
0.5 1 ✻✻ mA
✻ Same specification as for DAC7621E.
NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions where
the final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
DAC7621
2
PIN CONFIGURATION
PIN DESCRIPTIONS
Top View SSOP
CLR
V
V
OUT
AGND
DGND
DB11 (MSB)
DB10
DB9
DB8
DB7
1
2
DD
3
4
5
DAC7621E
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
LOADDAC
CS
R/W
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
PIN LABEL DESCRIPTION
1 CLR Reset. Resets the DAC register to zero. Active
2V
3V
4 AGND Analog Ground
5 DGND Digital Ground
6 DB11 Data Bit 11, MSB
7 DB10 Data Bit 10
8 DB9 Data Bit 9
9 DB8 Data Bit 8
10 DB7 Data Bit 7
11 DB6 Data Bit 6
12 DB5 Data Bit 5
13 DB4 Data Bit 4
14 DB3 Data Bit 3
15 DB2 Data Bit 2
16 DB1 Data Bit 1
17 DB0 Data Bit 0, LSB
18 R/W Read and Write Control
19 CS Chip Select. Active LOW.
20 LOADDAC Loads the internal DAC register. The DAC register
LOW. Asynchronous input.
Postive Power Supply
DD
DAC Output Voltage
OUT
is a transparent latch and is transparent when
LOADDAC is LOW (regardless of the state of CS or
CLK).
ABSOLUTE MAXIMUM RATINGS
VDD to GND .......................................................................... –0.3V to 6V
Digital Inputs to GND .............................................. –0.3V to V
to GND ........................................................... –0.3V to VDD + 0.3V
V
OUT
Power Dissipation ........................................................................ 325mW
Thermal Resistance,
Maximum Junction Temperature.................................................. +150°C
Operating Temperature Range ...................................... –40°C to +85°C
Storage Temperature Range ....................................... –65°C to +150°C
Lead Temperature (soldering, 10s) .............................................. +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
θ
........................................................... 150°C/W
JA
(1)
+ 0.3V
DD
ELECTROSTA TIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
MINIMUM
RELATIVE DIFFERENTIAL SPECIFICATION PACKAGE
PRODUCT (LSB) (LSB) RANGE PACKAGE NUMBER
ACCURACY NONLINEARITY TEMPERATURE DRAWING ORDERING TRANSPORT
DAC7621E ±2 ±1 –40°C to +85°C 20-Lead SSOP 334 DAC7621E Rails
"" " " ""DAC7621E/1K Tape and Reel
DAC7621EB ±1 ±1 –40°C to +85°C 20-Lead SSOP 334 DAC7621EB Rails
"" " " ""DAC7621EB/1K Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7621E/1K” will get a single
1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
(1)
NUMBER
(2)
MEDIA
3 DAC7621
®
TIMING DIAGRAMS
CS
t
RDS
R/W
Data Out
t
RCS
Data Valid
t
CSD
t
t
RDH
DZ
CS
R/W
LOADDAC
Data In
t
WCS
t
WS
t
DS
t
WH
t
LWD
t
DH
Data Output Timing
TIMING SPECIFICATIONS
TA = –40°C to +85°C
SYMBOL
t
RCS
t
RDS
t
RDH
t
DZ
t
CSD
t
WCS
t
WS
t
WH
t
DS
t
DH
t
LWD
DESCRIPTION MIN TYP MAX UNITS
CS LOW for Read 200 ns
R/W HIGH to CS LOW 10 ns
R/W HIGH after CS HIGH 0 ns
CS HIGH to Data Bus 100 ns
in High Impedance
CS LOW to Data Bus Valid 100 160 ns
CS LOW for Write 50
R/W LOW to CS LOW 0 ns
R/W LOW after CS HIGH 5 ns
Data Valid to CS LOW 0 ns
Data Valid after CS HIGH 5 ns
LOADDAC LOW 50 ns
Digital Input Timing
LOGIC TRUTH TABLE
INPUT DAC
R/W CS LOADDAC REGISTER REGISTER MODE
L L L Write Write Write
L L H Write Hold Write Input
H L H Read Hold Read Input
X H L Hold Update Update
X H H Hold Hold Hold
X = Don’t Care.
®
DAC7621
4
TYPICAL PERFORMANCE CURVES
1k
100
10
1
0.1
0.01
PULL-DOWN VOLTAGE vs OUTPUT SINK CURRENT
Delta V
OUT
(mV)
Current (mA)
0.001 0.01 0.1 1 10 100
85°C (mV)
–40°C
Data = 000
H
25°C
5.0
4.8
4.6
4.4
4.2
4.0
MINIMUM SUPPLY VOLTAGE vs LOAD
V
DD
Minimum (V)
Output Load Current (mA)
0.010 0.100 1.000 10.000
∆VFS = 1 LSB
Data = FFF
H
At TA = +25°, and VDD = 5V, unless otherwise specified.
4.5
OUTPUT SWING vs LOAD
4.0
3.5
3.0
2.5
2.0
1.5
Output Voltage (V)
1.0
0.5
0
10 100 1k 10k 100k
Load Resistance (Ω)
BROADBAND NOISE
Noise Voltage (1mV/div)
Code = FFF
BW = 2MHz
H
Time (2µs/div)
4.0
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
3.5
3.0
2.5
2.0
1.5
Supply Current (mA)
1.0
0.5
0
5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
Logic Voltage (V)
70
POWER SUPPLY REJECTION vs FREQUENCY
60
50
40
30
PSR (dB)
20
10
0
10 100 1k 10k 100k 1M
Frequency (Hz)
Data = FFF
VDD = 5V
H
±200mV AC
®
5 DAC7621
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°, and VDD = 5V, unless otherwise specified.
SHORT-CIRCUIT CURRENT vs OUTPUT VOLTAGE
80
60
40
20
Positive
Current
Limit
Data = 800
Output tied to I
0
–20
Output Current (mA)
–40
–60
Negative
Current
Limit
–80
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (V)
MID-SCALE GLITCH PERFORMANCE
LOADDAC
(2mV/div)
OUT
V
SOURCE
V
OUT
4.0
SUPPLY CURRENT vs TEMPERATURE
V
= 3.5V
LOGIC
3.5
Data = FFF
No Load
3.0
H
2.5
H
2.0
1.5
Supply Current (mA)
1.0
0.5
VDD = 5.25V
VDD = 5.0V
VDD = 4.75V
0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)
MID-SCALE GLITCH PERFORMANCE
LOADDAC
V
(2mV/div)
OUT
V
OUT
1V/div
7FFH to 800
Time (500ns/div)
LARGE-SIGNAL SETTLING TIME
CL = 110pF
R
LD
Time (20µs/div)
= No Load
L
V
OUT
800
H
H to
7FFH
Time (500ns/div)
RISE TIME DETAIL
LD
V
OUT
Output Voltage (1mV/div)
Time (10µs/div)
®
DAC7621
6
TYPICAL PERFORMANCE CURVES (CONT)
0
10
20
30
40
50
60
–12
–8 –4 0 4 8 12
T.U.E = ΣINL = ZS + FS
Sample Size = 300 Units
T
A
= +25°C
Number of Units
TOTAL UNADJUSTED ERROR HISTOGRAM
3
2
1
0
–1
ZERO-SCALE VOLTAGE vs TEMPERATURE
Zero-Scale (mV)
Temperature (°C)
–50 0 25–25 50 75 100 125
At TA = +25°, and VDD = 5V, unless otherwise specified.
FALL TIME DETAIL
Output Voltage (1mV/div)
Time (10µs/div)
LONG-TERM DRIFT ACCELERATED BY BURN-IN
8
6
4
2
0
–2
–4
Output Voltage Change (mV)
–6
–8
0 400200 600 800 1000 1200
Hours of Operation at +150°C
144 Units
10.000
1.000
V
OUT
0.100
LD
min
avg
max
Noise (µV/√Hz)
0.010
OUTPUT VOLTAGE NOISE vs FREQUENCY
Data = FFF
10 100 1k 10k 100k
Frequency (Hz)
H
4.115
4.110
4.105
4.100
4.095
4.090
Full-Scale Output (V)
4.085
4.080
4.075
FULL-SCALE VOLTAGE vs TEMPERATURE
Avg + 3σ
Avg
Avg – 3σ
–50 0 25–25 50 75 100 125
Temperature (°C)
No Load
Sample Size = 300
®
7 DAC7621
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°, and VDD = 5V, unless otherwise specified.
LINEARITY ERROR vs DIGITAL CODE
2.0
1.5
1.0
0.5
0
–0.5
Linearity Error (LSBs)
–1.0
–1.5
–2.0
0
512 1024 1536 2048 2560 3072 3584 4096
LINEARITY ERROR vs DIGITAL CODE
1
0.5
(at +25°C)
Code
(at +85°C)
DIFFERENTIAL LINEARITY ERROR vs DIGITAL CODE
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
Differential Linearity Error (LSBs)
–2.0
0
512 1024 1536 2048 2560 3072 3584 4096
DIFFERENTIAL LINEARITY ERROR vs DIGITAL CODE
1
0.5
(at +25°C)
Code
(at +85°C)
0
Linearity Error (LSBs)
–0.5
–1.0
0
512 1024 1536 2048 2560 3072 3584 4096
LINEARITY ERROR vs DIGITAL CODE
1
0.5
0
Linearity Error (LSBs)
–0.5
–1.0
0
512 1024 1536 2048 2560 3072 3584 4096
Code
(at –40°C)
Code
0
–0.5
Differential Linearity Error (LSBs)
–1.0
0
512 1024 1536 2048 2560 3072 3584 4096
DIFFERENTIAL LINEARITY ERROR vs DIGITAL CODE
1
0.5
0
–0.5
Differential Linearity Error (LSBs)
–1.0
0
512 1024 1536 2048 2560 3072 3584 4096
Code
(at –40°C)
Code
®
DAC7621
8
OPERATION
The DAC7621 is a 12-bit digital-to-analog converter (DAC)
complete with an input shift register, DAC register, lasertrimmed 12-bit DAC, on-board reference, and a rail-to-rail
output amplifier. Figure 1 shows the basic operation of the
DAC7621.
INTERFACE
Figure 1 shows the basic connection between a
microcontroller and the DAC7621. The interface consists of
a Read/Write (R/W), data, and a load DAC signal
(LOADDAC). In addition, a chip select (CS) input is available to enable the DAC7621 when there are multiple devices. The data format is Straight Binary. An asynchronous
clear input (CLR) is provided to simplify start-up or periodic
resets. Table I shows the relationship between input code
and output voltage.
DAC7621 Full-Scale Range = 4.095V
Least Significant Bit = 1mV
DIGITAL INPUT CODE ANALOG OUTPUT
STRAIGHT OFFSET BINARY
FFF
H
801
H
800
H
7FF
H
000
H
TABLE I. Digital Input Code and Corresponding Ideal
Analog Output.
(V) DESCRIPTION
+4.095 Full Scale
+2.049 Midscale + 1 LSB
+2.048 Midscale
+2.047 Midscale – 1 LSB
0 Zero Scale
The digital data into the DAC7621 is double-buffered. This
means that new data can be entered into the DAC without
disturbing the old data and the analog output of the converter. At some point after the data has been entered into the
serial shift register, this data can be transferred into the DAC
register. This transfer is accomplished with a HIGH to LOW
transition of the LOADDAC pin. However, the LOADDAC
pin makes the DAC register transparent. If new data becomes available on the bus register while LOADDAC is
LOW, the DAC output voltage will change as the data
changes. To prevent this, CS must be returned HIGH prior
to changing data on the bus.
At any time, the contents of the DAC register can be set to
000H (analog output equals 0V) by taking the CLR input
LOW. The DAC register will remain at this value until CLR
is returned HIGH and LOADDAC is taken LOW to allow
the contents of the input register to be transferred to the
DAC register. If LOADDAC is LOW when CLR is taken
LOW, the DAC register will be set to 000H and the analog
output driven to 0V. When CLR is returned HIGH, the DAC
register and the analog output will respond accordingly.
DIGITAL-TO-ANALOG CONVERTER
The internal DAC section is a 12-bit voltage output
device that swings between ground and the internal reference voltage. The DAC is realized by a laser-trimmed
R-2R ladder network which is switched by N-channel
MOSFETs. The DAC output is internally connected to
the rail-to-rail output operational amplifier.
Clear
+5V
10µF
+
0.1µF
0V to
+4.095V
FIGURE 1. Basic Operation of the DAC7621.
Data Bus
DAC7621E
1
CLR
2
V
3
V
4
AGND
5
DGND
6
DB11
7
DB10
8
DB9
9
DB8
10
DB7
DD
OUT
LOADDAC
CS
R/W
DB0
DB1
DB2
DB3
DB4
DB5
DB6
20
19
18
17
16
15
14
13
12
11
Load DAC
Chip Select
Read/Write
Data Bus
9 DAC7621
®
Buffer
Bandgap
Reference
2.435V
FIGURE 2. Simplified Schematic of Analog Portion.
R-2R DAC
2R
2R
2R
2R
R
R
R
2R
R
1
Output Amplifier
R
2
OUTPUT AMPLIFIER
A precision, low-power amplifier buffers the output of the
DAC section and provides additional gain to achieve a 0V
to 4.095V range. The amplifier has low offset voltage, low
noise, and a set gain of 1.682V/V (4.095/2.435). See Figure
2 for an equivalent circuit schematic of the analog portion
of the DAC7621.
The output amplifier has a 7µs typical settling time to ±1
LSB of the final value. Note that there are differences in the
settling time for negative-going signals versus positivegoing signals.
The rail-to-rail output stage of the amplifier provides the
full-scale range of 0V to 4.095V while operating on a
supply voltage as low as 4.75V. In addition to its ability to
drive resistive loads, the amplifier will remain stable while
driving capacitive loads of up to 500pF. See Figure 3 for an
equivalent circuit schematic of the amplifier’s output driver
and the Typical Performance Curves section for more information regarding settling time, load driving capability, and
output noise.
V
DD
P-Channel
V
OUT
POWER SUPPLY
A BiCMOS process and careful design of the bipolar and
CMOS sections of the DAC7621 result in a very low power
device. Bipolar transistors are used where tight matching
and low noise are needed to achieve analog accuracy, and
CMOS transistors are used for logic, switching functions
and for other low power stages.
If power consumption is critical, it is important to keep the
logic levels on the digital inputs (R/W, CLK, CS, LOADDAC,
CLR) as close as possible to either VDD or ground. This will
keep the CMOS inputs (see “Supply Current vs Logic Input
Voltages” in the Typical Performance Curves) from shunting current between VDD and ground.
The DAC7621 power supply should be bypassed as shown
in Figure 1. The bypass capacitors should be placed as close
to the device as possible, with the 0.1µF capacitor taking
priority in this regard. The “Power Supply Rejection vs
Frequency” graph in the Typical Performance Curves section shows the PSRR performance of the DAC7621. This
should be taken into account when using switching power
supplies or DC/DC converters.
In addition to offering guaranteed performance with VDD in
the 4.75V to 5.25V range, the DAC7621 will operate with
reduced performance down to 4.5V. Operation between
4.5V and 4.75V will result in longer settling time, reduced
performance, and current sourcing capability. Consult the
“VDD vs Load Current” graph in the Typical Performance
Curves section for more information.
N-Channel
AGND
FIGURE 3. Simplified Driver Section of Output Amplifier.
®
DAC7621
10
APPLICATIONS
POWER AND GROUNDING
The DAC7621 can be used in a wide variety of situations—
from low power, battery operated systems to large-scale
industrial process control systems. In addition, some applications require better performance than others, or are particularly sensitive to one or two specific parameters. This
diversity makes it difficult to define definite rules to follow
concerning the power supply, bypassing, and grounding.
The following discussion must be considered in relation to
the desired performance and needs of the particular system.
A precision analog component requires careful layout, adequate bypassing, and a clean, well-regulated power supply.
As the DAC7621 is a single-supply, +5V component, it will
often be used in conjunction with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the
higher the switching speed, the more difficult it will be to
achieve good performance.
The DAC7621 has separate analog ground and digital ground
pins. The current through DGND is mostly switching transients and are up to 4mA peak in amplitude. The current
through AGND is typically 0.5mA.
For best performance, separate analog and digital ground
planes with a single interconnection point to minimize
ground loops. The analog pins are located adjacent to each
other to help isolate analog from digital signals. Analog
signals should be routed as far as possible from digital
signals and should cross them at right angles. A solid analog
ground plane around the D/A package, as well as under it in
the vicinity of the analog and power supply pins, will isolate
the D/A from switching currents. It is recommended that
DGND and AGND be connected directly to the ground
planes under the package.
If several DAC7621s are used, or if sharing supplies with
other components, connecting the AGND and DGND lines
together at the power supplies once, rather than at each chip,
may produce better results.
The power applied to VDD should be well regulated and lownoise. Switching power supplies and DC/DC converters will
often have high-frequency glitches or spikes riding on the
output voltage. In addition, digital components can create
similar high frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
voltage through various paths between VDD and V
OUT
.
As with the GND connection, VDD should be connected to
a +5V power supply plane or trace that is separate from the
connection for digital logic until they are connected at the
power entry point. In addition, the 10µF and 0.1µF capacitors shown in Figure 4 are strongly recommended and
should be installed as close to VDD and ground as possible.
In some situations, additional bypassing may be required
such as a 100µF electrolytic capacitor or even a “Pi” filter
made up of inductors and capacitors—all designed to essentially lowpass filter the +5V supply, removing the high
frequency noise (see Figure 4).
100µF
Digital Circuits
+5V
GND
+
+
10µF
Analog
Components
Other
0.1µF
DAC7621
V
DD
AGND
DGND
+5V
Power
Supply
+5V
GND
Optional
FIGURE 4. Suggested Power and Ground Connections for a DAC7621 Sharing a +5V Supply with a Digital System with a
Single Ground Plane.
11 DAC7621
®
PACKAGE OPTION ADDENDUM
www.ti.com
16-Mar-2007
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
DAC7621E ACTIVE SSOP DB 20 68 Green (RoHS &
no Sb/Br)
DAC7621E/1K ACTIVE SSOP DB 20 1000 Green (RoHS &
no Sb/Br)
DAC7621E/1KG4 ACTIVE SSOP DB 20 1000 Green (RoHS &
no Sb/Br)
DAC7621EB ACTIVE SSOP DB 20 68 Green (RoHS &
no Sb/Br)
DAC7621EB/1K ACTIVE SSOP DB 20 1000 Green (RoHS &
no Sb/Br)
DAC7621EB/1KG4 ACTIVE SSOP DB 20 1000 Green (RoHS &
no Sb/Br)
DAC7621EBG4 ACTIVE SSOP DB 20 68 Green (RoHS &
no Sb/Br)
DAC7621EG4 ACTIVE SSOP DB 20 68 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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