BURR-BROWN ADS8345 User Manual

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Page 1

ADS8345

SBAS177C – FEBRUARY 2001 – REVISED APRIL 2003

16-Bit, 8-Channel Serial Output Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● BIPOLAR INPUT RANGE

● PIN-FOR-PIN COMPATIBLE WITH THE

ADS7844 AND ADS8344

● SINGLE SUPPLY: 2.7V to 5V

● 8-CHANNEL SINGLE-ENDED OR

4-CHANNEL DIFFERENTIAL INPUT

● UP TO 100kHz CONVERSION RATE

● 85dB SINAD

● SERIAL INTERFACE

● QSOP-20 AND SSOP-20 PACKAGES

APPLICATIONS

● DATA ACQUISITION

● TEST AND MEASUREMENT EQUIPMENT

● INDUSTRIAL PROCESS CONTROL

● PERSONAL DIGITAL ASSISTANTS

● BATTERY-POWERED SYSTEMS

DESCRIPTION

The ADS8345 is an 8-channel, 16-bit, sampling Analog-to-Digital (A/D) converter with a synchronous serial interface. Typical power dissipation is 8mW at a 100kHz throughput rate and a +5V supply. The reference voltage (V

) can be varied between 500mV and VCC/2, providing a

REF

corresponding input voltage range of ±V includes a shutdown mode which reduces power dissipation to under 15µW. The ADS8345 is ensured down to 2.7V operation.

Low-power, high-speed, and an onboard multiplexer make the ADS8345 ideal for battery-operated systems such as personal digital assistants, portable multi-channel data loggers, and measurement equipment. The serial interface also provides low-cost isolation for remote data acquisition. The ADS8345 is available in a QSOP-20 or SSOP-20 package and is ensured over the –40°C to +85°C temperature range.

. The device

REF

CH0 CH1 CH2 CH3

CH4 CH5 CH6 CH7

COM

REF

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

8-Channel

Multiplexer

CDAC

SAR

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Comparator

DCLK

Serial

Interface

and

Control

SHDN D

OUT

BUSY

Page 2

ABSOLUTE MAXIMUM RATINGS

to GND ........................................................................ –0.3V to +6V

Analog Inputs to GND .......................................... –0.3V to (+V

Digital Inputs to GND ........................................................... –0.3V to +6V

Power Dissipation .......................................................................... 250mW

Maximum Junction Temperature................................................... +150°C

Operating Temperature Range ........................................ –40°C to +85°C

Storage Temperature Range ......................................... –65°C to +150°C

Lead Temperature (soldering, 10s) ............................................... +300°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.

(1)

) + 0.3V

ELECTROSTATIC DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

MAXIMUM

INTEGRAL MAXIMUM SPECIFIED

PRODUCT ERROR (LSB) ERROR (%) PACKAGE-LEAD DESIGNATOR

LINEARITY GAIN PACKAGE TEMPERATURE ORDERING TRANSPORT

ADS8345E 8 ±0.05 QSOP-20 DBQ –40°C to +85°C ADS8345E Rails, 100

(1)

RANGE NUMBER MEDIA, QUANTITY

"" " " " "ADS8345E/2K5 Tape and Reel, 2500

ADS8345N 8 ±0.05 SSOP-20 DB –40°C to +85°C ADS8345N Rails, 100

"" " " " "ADS8345N/1K Tape and Reel, 1000

ADS8345EB 6 ±0.024 QSOP-20 DBQ –40°C to +85°C ADS8345EB Rails, 100

"" " " " "ADS8345EB/2K5 Tape and Reel, 2500

ADS8345NB 6 ±0.024 SSOP-20 DB –40°C to +85°C ADS8345NB Rails, 100

"" " " " "ADS8345NB/1K Tape and Reel, 1000

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

PIN CONFIGURATION

Top View SSOP

CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

COM

SHDN

1 2 3 4 5 6 7 8 9

ADS8345

DCLK

BUSY

OUT

GND

REF

PIN DESCRIPTIONS

PIN NAME DESCRIPTION

1 CH0 Analog Input Channel 0 2 CH1 Analog Input Channel 1 3 CH2 Analog Input Channel 2 4 CH3 Analog Input Channel 3 5 CH4 Analog Input Channel 4 6 CH5 Analog Input Channel 5 7 CH6 Analog Input Channel 6 8 CH7 Analog Input Channel 7 9 COM

10 SHDN Shutdown. When LOW, the device enters a very

11 V

12 +V 13 GND Ground 14 GND Ground 15 D

16 BUSY Busy Output. Busy goes LOW when the D

17 D

18 CS Chip Select Input; Active LOW. Data will not be clocked

19 DCLK External Clock Input. The clock speed determines the

20 +V

Common reference for analog inputs. This pin is typically connected to V

low-power shutdown mode. Voltage Reference Input. See the Electrical Character-

REF

istics Table for ranges. Power Supply, 2.7V to 5.25V

Serial Data Output. Data is shifted on the falling edge of

OUT

DCLK. This output is high impedance when CS is HIGH.

are being read and also when the device is converting. The Output is high impedance when CS is HIGH. Serial Data Input. If CS is LOW, data is latched on rising

edge of D

into D

unless CS is LOW. When CS is HIGH, D

high impedance.

conversion rate by the equation f Power Supply

CLK

REF

DCLK

= 24 • f

control bits

SAMPLE

OUT

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ADS8345

SBAS177C

Page 3

ELECTRICAL CHARACTERISTICS: +5V

At TA = –40°C to +85°C, +VCC = +5V, V

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 16 ✻ Bits

ANALOG INPUT

Full-Scale Input Span Positive Input-Negative Input –V Absolute Input Range +IN –0.2

Capacitance 25 ✻ pF Leakage Current ±1 ✻ µA

SYSTEM PERFORMANCE

No Missing Codes 14 15 Bits Integral Linearity Error ±8 ±6LSB Bipolar Error ±2 ±1mV Bipolar Error Match 48 ✻✻LSB Gain Error ±0.05 ±0.024 % Gain Error Match 1.0 4 ✻✻ LSB Noise 20 ✻ µVrms Power-Supply Rejection +4.75V < V

SAMPLING DYNAMICS

Conversion Time 16 ✻ CLK Cycles Acquisition Time 4.5 ✻ CLK Cycles Throughput Rate 100 ✻ kHz Multiplexer Settling Time 500 ✻ ns Aperture Delay 30 ✻ ns Aperture Jitter 100 ✻ ps Internal Clock Frequency SHDN = V External Clock Frequency 0.024 2.4 ✻✻MHz

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion

(2)

Signal-to-(Noise + Distortion) V Spurious-Free Dynamic Range V Channel-to-Channel Isolation V

REFERENCE INPUT

Range 0.5 +VCC/2 ✻✻V Resistance DCLK Static 5 ✻ GΩ Input Current 40 100 ✻✻ µA

DIGITAL INPUT/OUTPUT

Logic Family CMOS ✻ Logic Levels

Data Format Binary Two’s Complement ✻

POWER-SUPPLY REQUIREMENTS

Quiescent Current 1.5 2.0 ✻✻ mA

Power Dissipation 7.5 10 ✻✻ mW

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

= +2.5V, f

REF

= 100kHz, and f

SAMPLE

CLK

= 24 • f

= 2.4MHz, unless otherwise noted.

SAMPLE

ADS8345E, N ADS8345EB, NB

REF

–IN –0.2

< 5.25V 3 ✻ LSB

2.4 ✻ MHz

REF

+VCC + 0.2 +VCC + 0.2

✻✻V ✻✻V ✻✻V

Data Transfer Only 0 2.4 ✻✻MHz

VIN = 5Vp-p at 10kHz –96 ✻ dB

= 5Vp-p at 10kHz 85 ✻ dB

= 5Vp-p at 10kHz 98 ✻ dB

= 5Vp-p at 10kHz 105 ✻ dB

DCLK Static 0.001 3 ✻✻ µA

| IIH | ≤ +5µA 3.0 5.5 ✻✻V | IIL | ≤ +5µA –0.3 +0.8 ✻✻V

IOH = –250µA 3.5 ✻ V

IOL = 250µA 0.4 ✻ V

Specified Performance 4.75 5.25 ✻✻V

= 10kHz 1.2 ✻ mA

SAMPLE

Power-Down Mode

(3)

, CS = +V

3 ✻ µA

(1)

✻ Same specifications as ADS8345E, N. NOTES: (1) LSB means Least Significant Bit. With V

(PD1 = PD0 = 0) active or SHDN = GND.

ADS8345

SBAS177C

equal to +2.5V, one LSB is 76µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode

REF

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Page 4

ELECTRICAL CHARACTERISTICS: +2.7V

At TA = –40°C to +85°C, +VCC = +2.7V, V

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 16 ✻ Bits

ANALOG INPUT

Full-Scale Input Span Positive Input-Negative Input –V Absolute Input Range +IN –0.2

Capacitance 25 ✻ pF Leakage Current ±1 ✻ µA

SYSTEM PERFORMANCE

No Missing Codes 14 15 Bits Integral Linearity Error ±8 ±6LSB Bipolar Error ±1.0 ±0.5 mV Bipolar Error Match 24 ✻✻LSB Gain Error ±0.05 ±0.024 % of FSR Gain Error Match 14 ✻✻ LSB Noise 20 ✻ µVrms Power-Supply Rejection +2.7 < V

SAMPLING DYNAMICS

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion

(2)

Signal-to-(Noise + Distortion) V Spurious-Free Dynamic Range V Channel-to-Channel Isolation V

REFERENCE INPUT

Range 0.5 +VCC/2 ✻✻V Resistance DCLK Static 5 ✻ GΩ Input Current 13 40 ✻✻ µA

DIGITAL INPUT/OUTPUT

Logic Family CMOS ✻ Logic Levels

Data Format Binary Two’s Complement ✻

POWER-SUPPLY REQUIREMENTS

Quiescent Current 1.2 1.85 ✻✻ mA

Power Dissipation 3.2 5 ✻✻ mW

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

= +1.25V, f

REF

= 100kHz, and f

SAMPLE

CLK

= 24 • f

= 2.4MHz, unless otherwise noted.

SAMPLE

ADS8345E, N ADS8345EB, NB

REF

–IN –0.2

< +3.3V 3 ✻ LSB

2.4 ✻ MHz

REF

+VCC + 0.2 +VCC + 0.2

✻✻V ✻✻V ✻✻V

When used with Internal Clock 0.024 2.0 ✻✻MHz

Data Transfer Only 0 2.4 ✻✻MHz

VIN = 2.5Vp-p at 1kHz –95 ✻ dB

= 2.5Vp-p at 1kHz 81 ✻ dB

= 2.5Vp-p at 1kHz 95 ✻ dB

= 2.5Vp-p at 10kHz 108 ✻ dB

DCLK Static 0.001 3 ✻✻ µA

| I

| ≤ +5µA+V

| I

| ≤ +5µA –0.3 +0.8 ✻✻V

IOH = –250µA+V

IOL = 250µA 0.4 ✻ V

• 0.7 5.5 ✻✻V

• 0.8 ✻ V

Specified Performance 2.7 3.6 ✻✻V

= 10kHz 950 ✻ µA

SAMPLE

Power-Down Mode

(3)

, CS = +V

3 ✻ µA

(1)

✻ Same specifications as ADS8345E, N. NOTES: (1) LSB means Least Significant Bit. With V

mode (PD1 = PD0 = 0) active or SHDN = GND.

equal to +1.25V, one LSB is 38µV. (2) First nine harmonics of the test frequency. (3) Auto power-down

REF

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ADS8345

SBAS177C

Page 5

TYPICAL CHARACTERISTICS: +5V

CHANGE IN SIGNAL-TO-(NOISE + DISTORTION)

vs TEMPERATURE

–50 –25 0 20 50 75 100

Temperature (°C)

Delta from +25°C (dB)

0.2

0.0

–0.2

–0.4

–0.6

–0.8

0.4 fIN = 4.956kHz, –0.2dB

At TA = +25°C, +VCC = +5V, V

= +2.5V, f

REF

= 100kHz, and f

SAMPLE

DCLK

= 24 • f

SAMPLE

= 2.4MHz, unless otherwise noted.

FREQUENCY SPECTRUM

(4096 Point FFT; f

–20

–40

–60

–80

Amplitude (dB)

–100

–120

–140

0 1020304050

SIGNAL-TO-NOISE RATIO AND

SIGNAL-TO-(NOISE + DISTORTION)

100

vs INPUT FREQUENCY

= 1.001kHz, –0.2dB)

Frequency (kHz)

SNR

SINAD

FREQUENCY SPECTRUM

(4096 Point FFT; f

–20

–40

–60

–80

Amplitude (dB)

–100

–120

–140

0 1020304050

SPURIOUS-FREE DYNAMIC RANGE

AND TOTAL HARMONIC DISTORTION

110

100

SFDR (dB)

vs INPUT FREQUENCY

= 9.985kHz, –0.2dB)

Frequency (kHz)

SFDR

THD

(1)

–110

–100

–90

–80

THD (dB)

SNR and SINAD (dB)

15.0

14.5

14.0

13.5

13.0

12.5

12.0

Effective Number of Bits

11.5

11.0

101 100

Frequency (kHz)

EFFECTIVE NUMBER OF BITS

vs INPUT FREQUENCY

101 100

Frequency (kHz)

NOTE: (1) First Nine Harmonics of the Input Frequency

–70

–60

101 100

Frequency (kHz)

ADS8345

SBAS177C

www.ti.com

Page 6

TYPICAL CHARACTERISTICS: +5V (Cont.)

At TA = +25°C, +VCC = +5V, V

= +2.5V, f

REF

= 100kHz, and f

SAMPLE

DCLK

= 24 • f

= 2.4MHz, unless otherwise noted.

SAMPLE

INTEGRAL LINEARITY ERROR vs CODE

ILE (LSB)

–1

–2

–3

8000

SUPPLY CURRENT vs TEMPERATURE

1.7

1.6

1.5

1.4

Supply Current (mA)

1.3

C000

0000

Output Code

4000

DIFFERENTIAL LINEARITY ERROR vs CODE

DLE (LSB)

–1

–2

–3

7FFF

8000

C000

0000

4000

7FFF

Output Code

CHANGE IN BPZ vs TEMPERATURE

Delta from 25°C (LSBs)

–1

1.2 –50 –25 0 25 50 75 100

Temperature (°C)

CHANGE IN GAIN vs TEMPERATURE

1.0

0.5

Delta from 25°C (LSBs)

–0.5

–50 –25 0 25 50 75 100

Temperature (°C)

–2

–50 –25 0 25 50 75 100

Temperature (°C)

WORST-CASE CHANNEL-TO-CHANNEL

BPZ MATCH vs TEMPERATURE

5.0

4.5

4.0

3.5

3.0

BPZ Match (LSBs)

2.5

2.0 –50 –25 0 25 50 75 100

Temperature (°C)

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ADS8345

SBAS177C

Page 7

TYPICAL CHARACTERISTICS: +5V (Cont.)

COMMON-MODE REJECTION vs FREQUENCY

0.1 1 10 100 Frequency (kHz)

CMRR (dB)

100

VCM = 2Vp-p Sinewave Centered Around V

REF

At TA = +25°C, +VCC = +2.5V, V

WORST-CASE CHANNEL-TO-CHANNEL

0.5

0.4

0.3

Gain Match (LSBs)

0.2

0.1 –50 –25 0 25 50 75 100

GAIN MATCH vs TEMPERATURE

= +2.5V, f

REF

Temperature (°C)

SAMPLE

= 100kHz, and f

DCLK

= 24 • f

= 2.4MHz, unless otherwise noted.

SAMPLE

TYPICAL CHARACTERISTICS: +2.7V

At TA = +25°C, +VCC = +2.7V, V

= +1.25V, f

REF

= 100kHz, and f

SAMPLE

DCLK

= 24 • f

= 2.4MHz, unless otherwise noted.

SAMPLE

FREQUENCY SPECTRUM

(4096 Point FFT; f

–20

–40

–60

–80

Amplitude (dB)

–100

–120

–140

0 1020304050

Frequency (kHz)

SIGNAL-TO-NOISE RATIO AND

SIGNAL-TO-(NOISE + DISTORTION)

SNR and SINAD (dB)

ADS8345

SBAS177C

vs INPUT FREQUENCY

Frequency (kHz)

= 1.001kHz, –0.2dB)

SNR

SINAD

101 100

Amplitude (dB)

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FREQUENCY SPECTRUM

(4096 Point FFT; f

–20

–40

–60

–80

–100

–120

–140

0 1020304050

SPURIOUS-FREE DYNAMIC RANGE

AND TOTAL HARMONIC DISTORTION

100

SFDR (dB)

NOTE: (1) First Nine Harmonics of the Input Frequency

vs INPUT FREQUENCY

= 9.985kHz, –0.2dB)

Frequency (kHz)

SFDR

(1)

THD

101 100

Frequency (kHz)

–100

–90

–80

–70

–60

–50

THD (dB)

Page 8

TYPICAL CHARACTERISTICS: +2.7V (Cont.)

At TA = +25°C, +VCC = +2.7V, V

= +1.25V, f

REF

= 100kHz, and f

SAMPLE

DCLK

= 24 • f

= 2.4MHz, unless otherwise noted.

SAMPLE

14.0

13.5

13.0

12.5

12.0

11.5

11.0

10.5

Effective Number of Bits

10.0

9.5

9.0

INTEGRAL LINEARITY ERROR vs CODE

EFFECTIVE NUMBER OF BITS

vs INPUT FREQUENCY

101 100

Frequency (kHz)

CHANGE IN SIGNAL-TO-(NOISE + DISTORTION)

vs TEMPERATURE

0.4 fIN = 4.956kHz, –0.2dB

0.2

–0.2

–0.4

–0.6

Delta from +25°C (dB)

–0.8

–1.0

–50 –25 0 20 50 75 100

Temperature (°C)

DIFFERENTIAL LINEARITY ERROR vs CODE

ILE (LSB)

–1

–2

–3

8000

C000

0000

4000

Output Code

SUPPLY CURRENT vs TEMPERATURE

1.3

1.2

1.1

1.0

Supply Current (mA)

0.9 –50 –25 0 25 50 75 100

Temperature (°C)

7FFF

DLE (LSB)

–1

–2

–3

8000

C000

0000

4000

7FFF

Output Code

CHANGE IN BPZ vs TEMPERATURE

1.0

0.5

–0.5

Delta from 25°C (LSBs)

–1.0

–50 –25 0 25 50 75 100

Temperature (°C)

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ADS8345

SBAS177C

Page 9

TYPICAL CHARACTERISTICS: +2.7V (Cont.)

WORST-CASE CHANNEL-TO-CHANNEL

BPZ MATCH vs TEMPERATURE

–50 –25 0 25 50 75 100

Temperature (°C)

BPZ Match (LSBs)

1.0

0.9

0.8

0.7

0.6

0.5

COMMON-MODE REJECTION vs FREQUENCY

0.1 1 10 100 Frequency (kHz)

CMRR (dB)

VCM = 1Vp-p Sinewave Centered Around V

REF

SUPPLY CURRENT vs V

2.5 3.0 3.5 4.0 4.5 5.0 +V

(V)

Supply Current (mA)

1.5

1.4

1.3

1.2

1.1

1.0

0.9

SAMPLE

= 100kHz

At TA = +25°C, +VCC = +2.7V, V

= +1.25V, f

REF

= 100kHz, and f

SAMPLE

DCLK

= 24 • f

= 2.4MHz, unless otherwise noted.

SAMPLE

1.0

0.5

Delta from 25°C (LSBs)

–0.5

–50 –25 0 25 50 75 100

0.35

0.30

CHANGE IN GAIN vs TEMPERATURE

Temperature (°C)

WORST-CASE CHANNEL-TO-CHANNEL

GAIN MATCH vs TEMPERATURE

0.25

Gain Match (LSBs)

0.20 –50 –25 0 25 50 75 100

Temperature (°C)

POWER-DOWN SUPPLY CURRENT

140

120

External Clock Disabled

100

Supply Current (nA)

–50 –25 0 25 50 75 100

ADS8345

SBAS177C

vs TEMPERATURE

Temperature (°C)

www.ti.com

Page 10

THEORY OF OPERATION

The ADS8345 is a classic Successive Approximation Register (SAR) A/D converter. The architecture is based on capacitive redistribution which inherently includes a sampleand-hold function. The converter is fabricated on a 0.6µm CMOS process.

The basic operation of the ADS8345 is shown in Figure 1. The device requires an external reference and an external clock. It operates from a single supply of 2.7V to 5.25V. The external reference can be any voltage between 500mV and +V

/2. The value of the reference voltage directly sets the

input range of the converter. The average reference input current depends on the conversion rate of the ADS8345.

The analog input to the converter is differential and is provided via an eight-channel multiplexer. The input can be provided in reference to a voltage on the COM pin (which is generally +V input channels (CH-CH7). The particular configuration is selectable via the digital interface.

ANALOG INPUT

The analog input is bipolar and fully differential. There are two general methods of driving the analog input of the ADS8345: single-ended or differential (see Figure 2). When the input is single-ended, the COM input is held at a fixed voltage. The CHX input swings around the same voltage and the peak-to-peak amplitude is 2 • V

/2) or differentially by using four of the eight

. The value of V

REF

determines the range over which the common voltage may vary (see Figure 3).

When the input is differential, the amplitude of the input is the difference between the CHX and COM input (see Figure 4). A voltage or signal is common to both of these inputs. The peak-to-peak amplitude of each input is V

about this

REF

common voltage. However, since the input are 180°C out-ofphase, the peak-to-peak amplitude of the difference voltage is 2 • V

. The value of V

REF

also determines the range of the

REF

voltage that may be common to both inputs (see Figure 5). In each case, care should be taken to ensure that the output

impedance of the sources driving the CHX and COM inputs are matched. If this is not observed, the two inputs could have different settling times. This may result in offset error, gain error, and linearity error which changes with both temperature and input voltage. If the impedance cannot be matched, the errors can be lessened by giving the ADS8345 additional acquisition time.

The input current on the analog inputs depends on a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8345 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current.

Care must be taken regarding the absolute analog input voltage. Outside of these ranges, the converter’s linearity may not meet specifications. Please refer to the Electrical Characteristics table for min/max ratings.

Single-ended or differential

analog inputs.

REF

FIGURE 1. Basic Operation of the ADS8345.

+2.7V to +5V

ADS8345

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

SHDN

DCLK

CS D

BUSY

OUT

GND GND +V

REF

19 18 17

16 15 14 13 12

0.1µF

Serial/Conversion Clock Chip Select Serial Data In

Serial Data Out

+1.25V to +2.5V

1µF to 10µF

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ADS8345

SBAS177C

Page 11

Converter

+IN

–IN

CH0 CH1 CH2 CH3

A2-A0

(shown 00o

)

(1)

SGL/DIF

(shown HIGH)

CH4 CH5 CH6 CH7

COM NOTE: (1) See Truth T ables, Table I,

and Table II for address coding.

REFERENCE INPUT

The external reference sets the analog input range. The ADS8345 will operate with a reference in the range of 500mV to +V

/2. Keep in mind that the analog input is the differ-

ence between the CHX input and the COM input, as shown in Figure 4. For example, in the single-ended mode, a 1.25V reference with the COM pin at V

/2, the selected input

channel (CH0-CH7) will properly digitize a signal in the range of (V

/2 – 1.25V) to (VCC/2 + 1.25V).

(1)

±V

REF

Common-Mode

Voltage

(typically V

Common-Mode

NOTE: (1) Relative to common-mode voltage.

Voltage

REF

)

Single-Ended Input

(1)

REF

(1)

REF

Differential Input

CHX

ADS8345

COM

CHX+

ADS8345

CHX–

FIGURE 2. Methods of Driving the ADS8345—Single-Ended

or Differential.

4.9

Common Voltage Range (V)

0.1

–1

0.5 1.0 1.5 2.0 2.5

Single-Ended Input

(V)

REF

= 5V

2.8

2.1

FIGURE 4. Simplified Diagram of the Analog Input.

5.2

Common Voltage Range (V)

0.2

0.0 1.0 1.5 2.0 2.5

Differential Input

(V)

REF

= 5V

4.2

0.8

FIGURE 3. Single-Ended Input—Common Voltage Range

ADS8345

SBAS177C

vs V

REF

FIGURE 5. Differential Input—Common Voltage Range vs V

REF

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Page 12

There are several critical items concerning the reference input and its wide-voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced. This is often referred to as the LSB (Least Significant Bit) size and is equal to the reference voltage divided by 65536. Any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference voltage is reduced. For example, if the offset of a given converter is 2LSBs with a 2.5V reference, then it will typically be 10LSBs with a 0.5V reference. In each case, the actual offset of the device is the same, 152.8µV.

The noise or uncertainty of the digitized output will increase with lower LSB size. With a reference voltage of 500mV, the LSB size is 15.3µV. This level is below the internal noise of the device. As a result, the digital output code will not be stable and will vary around a mean value by a number of LSBs. The distribution of output codes will be gaussian and the noise can be reduced by simply averaging consecutive conversion results or applying a digital filter.

With a lower reference voltage, care should be taken to provide a clean layout including adequate bypassing, a clean (low-noise, low-ripple) power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, the converter will also be more sensitive to nearby digital signals and electromagnetic interference.

The voltage into the V

input is not buffered and directly

REF

drives the Capacitor Digital-to-Analog Converter (CDAC) portion of the ADS8345. Typically, the input current is 13µA with a 2.5V reference. This value will vary by microamps depending on the result of the conversion. The reference current diminishes directly with both conversion rate and reference voltage. As the current from the reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will not reduce overall current drain from the reference.

DIGITAL INTERFACE

The ADS8345 has a 4-wire serial interface compatible with several microprocessor families (note that the digital inputs are over-voltage tolerant up to +5.5V, regardless of +V shows the typical operation of the ADS8345 digital interface.

). Figure 6

Most microprocessors communicate using 8-bit transfers; the ADS8345 can complete a conversion with three such transfers, for a total of 24 clock cycles on the DCLK input, provided the timing is as shown in Figure 6.

The first eight clock cycles are used to provide the control byte via the D

pin. When the converter has enough informa-

tion about the following conversion to set the input multiplexer appropriately, it enters the acquisition (sample) mode. After four more clock cycles, the control byte is complete and the converter enters the conversion mode. At this point, the input sample-and-hold goes into the Hold mode. The next sixteen clock cycles accomplish the actual A/D conversion.

Control Byte

Figure 6 shows placement and order of the control bits within the control byte. Tables I and II give detailed information about these bits. The first bit, the “S” bit, must always be HIGH and indicates the start of the control byte. The ADS8345 will ignore inputs on the D detected. The next three bits (A2-A0) select the active input channel or channels of the input multiplexer (see Tables III and IV and Figure 4).

BIT 7 BIT 0

(MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (LSB)

SA2A1A0— SGL/DIF PD1 PD0

TABLE I. Order of the Control Bits in the Control Byte.

BIT NAME DESCRIPTION

7 S Start Bit. Control byte starts with first HIGH bit on

6-4 A2-A0 Channel Select Bits. Along with the SGL/DIF bit,

2 SGL/DIF Single-Ended/Differential Select Bit. Along with bits

1-0 PD1-PD0 Power-Down Mode Select Bits. See Table V for

these bits control the setting of the multiplexer input.

A2-A0, this bit controls the setting of the multiplexer input.

details.

TABLE II. Descriptions of the Control Bits within the Control Byte.

pin until the START bit is

DCLK

BUSY

OUT

A2S

A1 A0

(START)

ACQ

AcquireIdle Conversion

SGL/

PD1 PD0

DIF

14131211109 8 7654321 0 Zero Filled...

(MSB)

81 8

(START)

(LSB)

181

AcquireIdle Conversion

SGL/

A2SA1A0

DIF

PD1 PD0

(MSB)

FIGURE 6. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated

serial port.

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ADS8345

SBAS177C

Page 13

The SGL/DIF-bit controls the multiplexer input mode: either in single-ended mode, where the selected input channel is referenced to the COM pin, or in differential mode, where the two selected inputs provide a differential input. See Tables III and IV and Figure 4 for more information. The last two bits (PD1-PD0) select the Power-Down mode and Clock mode, as shown in Table V. If both PD1 and PD0 are HIGH, the device is always powered up. If both PD1 and PD0 are LOW, the device enters a power-down mode between conversions. When a new conversion is initiated, the device will resume normal operation instantly—no delay is needed to allow the device to power up and the very first conversion will be valid.

A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

000+IN –IN 100 +IN –IN 001 +IN –IN 101 +IN –IN 010 +IN –IN 110 +IN –IN 011 +IN –IN 111 +IN–IN

TABLE III. Single-Ended Channel Selection (SGL/DIF

A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

00 0+IN–IN 00 1 +IN–IN 01 0 +IN–IN 01 1 +IN–IN 10 0–IN +IN 10 1 –IN +IN 11 0 –IN +IN 11 1 –IN +IN

HIGH).

TABLE IV. Differential Channel Control (SGL/DIF LOW).

PD1 PD0 DESCRIPTION

0 0 Power-down between conversions. When each

1 0 Selects internal clock mode. 0 1 Reserved for future use. 1 1 No power-down between conversions, device al-

conversion is finished, the converter enters a low-power mode. At the start of the next conversion, the device instantly powers up to full power. There is no need for additional delays to assure full operation and the very first conversion is valid.

ways powered. Selects external clock mode.

TABLE V. Power-Down Selection.

Clock Modes

The ADS8345 can be used with an external serial clock or an internal clock to perform the successive-approximation conversion. In both clock modes, the external clock shifts data in and out of the device. Internal clock mode is selected when PD1 is HIGH and PD0 is LOW.

If the user decides to switch from one clock mode to the other, an extra conversion cycle will be required before the ADS8345 can switch to the new mode. The extra cycle is required because the PD0 and PD1 control bits need to be written to the ADS8345 prior to the change in clock modes.

When power is first applied to the ADS8345, the user must set the desired clock mode. It can be set by writing PD1 = 1 and PD0 = 0 for internal clock mode or PD1 = 1 and PD0 = 1 for external clock mode. After enabling the required clock mode, only then should the ADS8345 be set to power-down between conversions (i.e., PD1 = PD0 = 0). The ADS8345 maintains the clock mode it was in prior to entering the power-down modes.

External Clock Mode

In external clock mode, the external clock not only shifts data in and out of the ADS8345, it also controls the A/D conversion steps. BUSY will go HIGH for one clock period after the last bit of the control byte is shifted in. Successive-approximation bit decisions are made and appear at D of the next 16 DCLK falling edges (see Figure 6). Figure 7 shows the BUSY timing in external clock mode.

on each

OUT

CSS

DCLK

BDV

BUSY

OUT

FIGURE 7. Detailed Timing Diagram.

ADS8345

SBAS177C

PD0

15D

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CSH

BTR

Page 14

Since one clock cycle of the serial clock is consumed with BUSY going HIGH (while the MSB decision is being made), 16 additional clocks must be given to clock out all 16 bits of data; thus, one conversion takes a minimum of 25 clock cycles to fully read the data. Since most microprocessors communicate in 8-bit transfers, this means that an additional transfer must be made to capture the LSB.

There are two ways of handling this requirement. One is where the beginning of the next control byte appears at the same time the LSB is being clocked out of the ADS8345 (see Figure 6). This method allows for maximum throughput and 24 clock cycles per conversion.

The other method is shown in Figure 8, which uses 32 clock cycles per conversion; the last seven clock cycles simply shift out zeros on the D high-impedance state when CS

falling edge, BUSY will go LOW.

line. BUSY and D

OUT

goes HIGH; after the next

go into a

OUT

Internal Clock Mode

In internal clock mode, the ADS8345 generates its own conversion clock internally. This relieves the microprocessor from having to generate the SAR conversion clock and allows the conversion result to be read back at the processor’s convenience, at any clock rate from 0MHz to 2.0MHz. BUSY goes LOW at the start of a conversion and then returns HIGH when the conversion is complete. During the conversion, BUSY will remain LOW for a maximum of 8µs. Also, during the conversion, DCLK should remain LOW to achieve the best noise performance. The conversion result is stored in an internal register; the data may be clocked out of this register any time after the conversion is complete.

If CS is LOW when BUSY goes LOW following a conversion, the next falling edge of the external serial clock will write out the MSB on the D

line. The remaining bits (D14-D0) will

OUT

be clocked out on each successive clock cycle following the MSB. If

is HIGH when BUSY goes LOW then the D

OUT

line will remain in tri-state until CS goes LOW, as shown in Figure 9. sion has started. Note that BUSY is not tri-stated when

does not need to remain LOW once a conver-

goes HIGH in internal clock mode. Data can be shifted in and out of the ADS8345 at clock rates

exceeding 2.4MHz, provided that the minimum acquisition time t

, is kept above 1.7µs.

ACQ

Digital Timing

Figure 7 and Tables VI and VII provide detailed timing for the digital interface of the ADS8345.

SYMBOL DESCRIPTION MIN TYP MAX UNITS

ACQ

CSS

CSH

BDV

BTR

TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,

Acquisition Time 1.5 µs

DIN Valid Prior to DCLK Rising 100 ns

DIN Hold After DCLK HIGH 10 ns

DCLK Falling to D CS Falling to D CS Rising to D

Valid 200 ns

OUT

Enabled 200 ns

OUT

Disabled 200 ns

OUT

CS Falling to First DCLK Rising 100 ns

CS Rising to DCLK Ignored 0 ns

DCLK HIGH 200 ns

DCLK LOW 200 ns

DCLK Falling to BUSY Rising 200 ns

CS Falling to BUSY Enabled 200 ns CS Rising to BUSY Disabled 200 ns

= –40°C to +85°C, C

LOAD

= 50pF).

CLK

BUSY

OUT

A1 A0

A2S

(START)

ACQ

AcquireIdle Conversion

SGL/

PD1 PD0

DIF

14131211109 8 7654321 0

(MSB)

FIGURE 8. External Clock Mode, 32 Clocks Per Conversion.

CLK

BUSY

OUT

(START)

A1 A0

A2S

ACQ

AcquireIdle Conversion

SGL/

PD1 PD0

DIF

9 1011121314151617181920212223242526272829303132

14131211109 8 7654321 0 Zero Filled...

(MSB)

FIGURE 9. Internal Clock Mode Timing.

81 8

(LSB)

Idle

Zero Filled...

(LSB)

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ADS8345

SBAS177C

Page 15

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t t

ACQ

DS DH DO

TR CSS CSH

BD BDV BTR

Acquisition Time 1.7 µs

DIN Valid Prior to DCLK Rising 50 ns

DIN Hold After DCLK HIGH 10 ns DCLK Falling to D CS Falling to D CS Rising to D

CS Falling to First DCLK Rising 50 ns

CS Rising to DCLK Ignored 0 ns

DCLK HIGH 150 ns DCLK LOW 150 ns

DCLK Falling to BUSY Rising 100 ns

CS Falling to BUSY Enabled 70 ns CS Rising to BUSY Disabled 70 ns

Valid 100 ns

OUT

Enabled 70 ns

OUT

Disabled 70 ns

OUT

TABLE VII. Timing Specifications (+VCC = +4.75V to +5.25V,

= –40°C to +85°C, and C

LOAD

= 50pF).

Data Format

The output data from the ADS8345 is in Binary Two’s Complement format, as shown in Table VIII. This table represents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise.

DESCRIPTION ANALOG VALUE

Full-Scale Range 2 • V Least Significant 2 • V

Bit (LSB) BINARY CODE HEX CODE +Full-Scale +V Midscale 0V 0000 0000 0000 0000 0000 Midscale – 1LSB 0V – 1LSB 1111 1111 1111 1111 FFFF –Full-Scale –V

REF

/65536

REF

– 1LSB 0111 1111 1111 1111 7FFF

REF

TABLE VIII. Ideal Input Voltages and Output Codes.

DIGITAL OUTPUT

BINARY TWO’S COMPLEMENT

1000 0000 0000 0000 8000

If DCLK is active and

is LOW while the ADS8345 is in auto power-down mode, the device will continue to dissipate some power in the digital logic. The power can be reduced to a minimum by keeping

HIGH.

Operating the ADS8345 in auto power-down mode will result in the lowest power dissipation, and there is no conversion time “penalty” on power-up. The very first conversion will be valid.

SHDN

can be used to force an immediate power-down.

NOISE

The noise floor of the ADS8345 itself is rather low (see Figures 10 and 11). The ADS8345 was tested at both 5V and

2.7V, and in both the internal and external clock modes. A low-level DC input was applied to the analog-input pins and the converter was put through 5000 conversions. The digital output of the A/D converter will vary in output code due to the internal noise of the ADS8345. This is true for all 16-bit, SARtype, A/D converters. Using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. The ±1σ, ±2σ, and ±3σ distributions will represent the 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6 and this will yield the ±3σ distribution, or 99.7%, of all codes. Statistically, up to 3 codes could fall outside the distribution when executing 1000 conversions. The ADS8345, with 5 output codes for the ±3σ distribution, will yield a < ±0.83LSB transition noise at 5V operation. Remember, to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference must be < 50µV.

POWER DISSIPATION

There are three power modes for the ADS8345: full-power (PD1-PD0 = 11B), auto power-down (PD1-PD0 = 00B), and shutdown ( depending on how the ADS8345 is being operated. For example, at full conversion rate and 24-clocks per conversion, there is very little difference between full-power mode and auto power-down; a shutdown will not lower power dissipation.

When operating at full-speed and 24-clocks per conversion (see Figure 6), the ADS8345 spends most of its time acquiring or converting. There is little time for auto power-down, assuming that this mode is active. Thus, the difference between full-power mode and auto power-down is negligible. If the conversion rate is decreased by simply slowing the frequency of the DCLK input, the two modes remain approximately equal. However, if the DCLK frequency is kept at the maximum rate during a conversion, but conversions are simply done less often, then the difference between the two modes is dramatic. In the latter case, the converter spends an increasing percentage of its time in power-down mode (assuming the auto power-down mode is active).

SHDN

LOW). The effects of these modes varies

3544

122

FFFE

701

FFFF

0000

Code

568

0001

0002

FIGURE 10. Histogram of 5000 Conversions of a DC Input at

the Code Transition, 5V operation external clock mode. V

REF

= V

COM

= 2.5V.

ADS8345

SBAS177C

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Page 16

2305

780

436

FFFCHFFFDHFFFEHFFFF

938

435

0000H0001H0002H0003H0004

Code

FIGURE 11. Histogram of 5000 Conversions of a DC Input at

the Code Center, 2.7V operation external clock mode. V

REF

= V

= 1.25V.

COM

AVERAGING

The noise of the A/D converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise will be reduced by a factor of 1/

√n

, where n is the number of averages. For example, averaging 4 conversion results will reduce the transition noise by 1/2 to ±0.25LSBs. Averaging should only be used for input signals with frequencies near DC.

For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similar manner to averaging: for every decimation by 2, the signal-to-noise ratio will improve 3dB.

LAYOUT

For optimum performance, care should be taken with the physical layout of the ADS8345 circuitry. This is particularly true if the reference voltage is LOW and/or the conversion rate is HIGH.

The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the

output of the analog comparator. Thus, during any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and highpower devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the DCLK input.

With this in mind, power to the ADS8345 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply.

The reference should be similarly bypassed with a 0.1µF capacitor. Again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, make sure that it can drive the bypass capacitor without oscillation (the series resistor can help in this case). The ADS8345 draws very little current from the reference on average, but it does place larger demands on the reference circuitry over short periods of time (on each rising edge of DCLK during a conversion).

The ADS8345 architecture offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be filtered out as discussed in the previous paragraph, voltage variation due to line frequency (50Hz or 60Hz) can be difficult to remove.

The GND pin should be connected to a clean ground point. In many cases, this will be the “analog” ground. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry.

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Page 17

PACKAGE DRAWINGS

DBQ (R-PDSO-G**) PLASTIC SMALL-OUTLINE

Gage Plane

0.008 (0,20) NOM

0.010 (0,25)

0.016 (0,40)

0.035 (0,89)

2420

Seating Plane

(8,74)

(8,56)

0.3370.337

(8,56)

(8,74)

0.344 0.344

4073301/E 10/00

0.150 (3,81)

0.157 (3,99)

0.012 (0,30)

0.008 (0,20)

24 PINS SHOWN

DIM

PINS **

A MIN

A MAX

0.004 (0,10)

0.010 (0,25)

0.069 (1,75) MAX

0.244 (6,20)

0.228 (5,80)

0.197

(5,00)

(4,78)

0.188

0.004 (0,10)

0.005 (0,13)

0.025 (0,64)

0°–8°

(10,01)

(9,80)

0.386

0.394

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-137

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PACKAGE DRAWINGS (Cont.)

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65

2,00 MAX

0,38 0,22

0,05 MIN

0,15

5,60 5,00

Seating Plane

8,20 7,40

0,10

0,25 0,09

0°–8°

Gage Plane

0,25

0,95 0,55

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

6,50

5,905,90

2016

7,50

6,90

8,50

10,50

9,907,90

10,50

9,90

12,90

12,30

4040065 /E 12/01

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Page 19

PACKAGE OPTION ADDENDUM

www.ti.com

1-Aug-2006

PACKAGING INFORMATION

Orderable Device Status

ADS8345E ACTIVE SSOP/

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

DBQ 20 56 Pb-Free

QSOP

ADS8345E/2K5 ACTIVE SSOP/

DBQ 20 2500 Pb-Free

QSOP

ADS8345E/2K5G4 ACTIVE SSOP/

DBQ 20 2500 Pb-Free

QSOP

ADS8345EB ACTIVE SSOP/

DBQ 20 56 Pb-Free

QSOP

ADS8345EB/2K5 ACTIVE SSOP/

DBQ 20 2500 Pb-Free

QSOP

ADS8345EB/2K5G4 ACTIVE SSOP/

DBQ 20 2500 Pb-Free

QSOP

ADS8345N ACTIVE SSOP DB 20 68 Green (RoHS&

no Sb/Br)

ADS8345N/1K ACTIVE SSOP DB 20 1000 Green (RoHS &

no Sb/Br)

ADS8345N/1KG4 ACTIVE SSOP DB 20 1000 Green (RoHS &

no Sb/Br)

ADS8345NB ACTIVE SSOP DB 20 68 Green (RoHS &

no Sb/Br)

ADS8345NB/1K ACTIVE SSOP DB 20 1000 Green (RoHS&

no Sb/Br)

ADS8345NB/1KG4 ACTIVE SSOP DB 20 1000 Green (RoHS &

no Sb/Br)

ADS8345NBG4 ACTIVE SSOP DB 20 68 Green (RoHS &

no Sb/Br)

(1)

The marketingstatus valuesare defined as follows:

ACTIVE: Productdevice recommendedfor new designs. LIFEBUY: TIhas announcedthat the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a newdesign.

PREVIEW: Devicehas beenannounced but is not in production. Samples may or may not be available. OBSOLETE: TIhas discontinuedthe production of the device.

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent forthe latestavailability information and additional product content details.

TBD: ThePb-Free/Green conversionplan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at hightemperatures, TIPb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) asdefined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Bror Sbdo not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

Addendum-Page 1

Page 20

PACKAGE OPTION ADDENDUM

www.ti.com

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information maynot beavailable for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customeron anannual basis.

1-Aug-2006

Addendum-Page 2

Page 21

Page 22

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65

2,00 MAX

0,38 0,22

0,05 MIN

0,15

5,60 5,00

Seating Plane

8,20 7,40

0,10

0,25 0,09

0°–ā8°

Gage Plane

0,25

0,95 0,55

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

6,50

5,905,90

2016

7,50

6,90

8,50

10,50

9,907,90

10,50

9,90

12,90

12,30

4040065 /E 12/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Page 23

IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty . Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

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BURR-BROWN ADS8345 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

PACKAGE/ORDERING INFORMATION

PIN CONFIGURATION

PIN DESCRIPTIONS

ELECTRICAL CHARACTERISTICS: +5V

ELECTRICAL CHARACTERISTICS: +2.7V

TYPICAL CHARACTERISTICS: +5V

TYPICAL CHARACTERISTICS: +2.7V

THEORY OF OPERATION

ANALOG INPUT

REFERENCE INPUT

DIGITAL INTERFACE

Control Byte

Clock Modes

External Clock Mode

Internal Clock Mode

Digital Timing

Data Format

NOISE

POWER DISSIPATION

AVERAGING

LAYOUT

PACKAGE DRAWINGS

DBQ (R-PDSO-G**) PLASTIC SMALL-OUTLINE

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE