BURR-BROWN ADS8317 User Manual

ADS8317

ADS8317

 
  

SAR

Serial

Interface

Comparator

ADS8317

S/H Amp

DCLOCK

D

OUT

CS/SHDN

+IN

REF

−

IN

CDAC

查询ADS8317供应商

16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling

ANALOG-TO-DIGITAL CONVERTER

1

FEATURES DESCRIPTION

23

• 16 Bits No Missing Codes (Full-Supply Range,

High or Low Grade)

• Very Low Noise: 5LSB

• Excellent Linearity:

± 0.8LSB typ, ± 1.5LSB max INL
+0.7LSB typ, +1.25LSB max DNL
± 1mV max Offset
± 16LSB typ Gain Error

• microPower:

10mW at 5V, 250kHz
4mW at 2.7V, 200kHz
2mW at 2.7V, 100kHz

0.2mW at 2.7V, 10kHz

• MSOP-8 Package

(SON-8 package available Q1, 2008; package
size same as 3x3 QFN)

• Pin-Compatible with the ADS8321

• Serial ( SPI™/SSI) Interface

PP

ADS8317

SBAS356A – JUNE 2007 – REVISED SEPTEMBER 2007

The ADS8317 is a 16-bit, sampling, analog-to-digital
(A/D) converter specified for a supply voltage range
from 2.7V to 5.5V. It requires very little power, even
when operating at the full data rate. At lower data
rates, the high speed of the device enables it to
spend most of its time in the power-down mode. For
example, the average power dissipation is less than

0.2mW at a 10kHz data rate.
The ADS8317 offers excellent linearity and very low

noise and distortion. It also features a synchronous
serial (SPI/SSI-compatible) interface and a differential
input. The reference voltage can be set to any level
within the range of 0.1V to V

Low power and small size make the ADS8317 ideal
for portable and battery-operated systems. It is also
an excellent fit for remote data-acquisition modules,
simultaneous multichannel systems, and isolated
data acquisition. The ADS8317 is available in
MSOP-8 and SON-8 packages. The SON package
size is the same as a 3x3 QFN package.

/2.

DD

APPLICATIONS

• Battery-Operated Systems

• Remote Data Acquisition

• Isolated Data Acquisition

• Simultaneous Sampling, Multichannel

Systems

• Industrial Controls

• Robotics

• Vibration Analysis

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 SPI is a trademark of Motorola, Inc.
3 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2007, Texas Instruments Incorporated

www.ti.com

ADS8317

SBAS356A – JUNE 2007 – REVISED SEPTEMBER 2007

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

MAXIMUM NO
INTEGRAL MISSING
LINEARITY CODES SPECIFIED TRANSPORT

ERROR ERROR PACKAGE- PACKAGE TEMPERATURE PACKAGE ORDERING MEDIA,

PRODUCT (LSB)

ADS8317I ± 2 16 MSOP-8 DGK – 40 ° C to +85 ° C D17

ADS8317IB ± 1.5 16 MSOP-8 DGK – 40 ° C to +85 ° C D17

ADS8317I

ADS8317IB

(3)

(3)

(2)

(LSB) LEAD DESIGNATOR RANGE MARKING NUMBER QUANTITY

± 2 16 SON-8 DRB – 40 ° C to +85 ° C D17

± 1.5 16 SON-8 DRB – 40 ° C to +85 ° C D17

(1)

ADS8317IDGKT Tape and Reel, 250

ADS8317IDGKR Tape and Reel, 2500
ADS8317IBDGKT Tape and Reel, 250
ADS8317IBDGKR Tape and Reel, 2500

ADS8317IDRBT Tape and Reel, 250

ADS8317IDRBR Tape and Reel, 2500
ADS8317IBDRBT Tape and Reel, 250
ADS8317IBDRBR Tape and Reel, 2500

(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see

the TI website at www.ti.com.
(2) Maximum Integral Linearity Error specifies a 5V power supply and 2.5V reference voltage.
(3) DRB (SON-8) package available Q1, 2008.

ABSOLUTE MAXIMUM RATINGS

(1)

Over operating free-air temperature range (unless otherwise noted).

ADS8317 UNIT

Supply voltage, V
Analog input voltage
Reference input voltage
Digital input voltage
Input current to any pin except supply – 20 to +20 mA
Power dissipation See Dissipation Ratings Table
Operating virtual junction temperature range, T
Operating free-air temperature range, T
Storage temperature range, T
Lead Temperature 1.6mm (1/16 inch) from case for 10sec +260 ° C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground terminal.

to GND – 0.3 to +7 V

DD

(2)

(2)

(2)

J

A

STG

– 0.3 to V
– 0.3 to V
– 0.3 to V

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

– 40 to +150 ° C

– 40 to +85 ° C

– 65 to +150 ° C

DISSIPATION RATINGS

DERATING

PACKAGE R

θ JC

R

θ JA

DGK +39.1 ° C/W +206.3 ° C/W 4.847mW/ ° C 606mW 388mW 315mW
DRB +5 ° C/W +45.8 ° C/W 3.7mW/ ° C 370mW 204mW 148mW

2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated

FACTOR ABOVE TA≤ +25 ° C TA= +70 ° C TA= +85 ° C

TA= +25 ° C POWER RATING POWER RATING POWER RATING

Product Folder Link(s): ADS8317

www.ti.com

SBAS356A – JUNE 2007 – REVISED SEPTEMBER 2007

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

Supply voltage, GND to V

DD

Reference input voltage 1 VDD/2 V

Analog input voltage +IN to GND – 0.2 V

Operating junction temperature, T

J

Low-voltage levels 2.7 3.6 V
5V logic levels 4.5 5.0 5.5 V

– IN to GND – 0.2 V

+IN – ( – IN) – V

REF

+ 0.2 V

DD

+ 0.2 V

DD

+V

REF

– 40 +125 ° C

ADS8317

V

ELECTRICAL CHARACTERISTICS: V

At – 40 ° C to +85 ° C, V

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT

ANALOG INPUT

Full-scale range FSR +IN – ( – IN) – V
Absolute input range +IN – 0.1 VDD+ 0.1 – 0.1 VDD+ 0.1 V

Input resistance R

Input capacitance During sampling 24 24 pF
Input leakage current ± 50 ± 50 nA
Differential input capacitance +IN to – IN, during sampling 20 20 pF
Full-power bandwidth FSBW fSsinewave, SINAD = 60dB 500 500 kHz

DC ACCURACY

Resolution 16 16 Bits
No missing codes NMC 16 16 16 16 Bits
Integral linearity error INL – 2 ± 1.5 +2 – 1.5 ± 0.8 +1.5 LSB
Differential linearity error DNL – 1 ± 1 +2 – 1 +0.7, – 0.5 +1.25 LSB
Offset error V
Offset error drift TCV

Gain error G

Gain error drift TCG
Bipolar zero error – 2 ± 0.75 +2 – 1 ± 0.5 +1 mV
Bipolar zero error drift ± 3 ± 3 μ V/ ° C
Noise 50 50 μ VRMS
Power-supply rejection PSRR 4.75V ≤ VDD≤ 5.25V 1 1 LSB

SAMPLING DYNAMICS

Conversion time
(16 DCLOCKs)

Acquisition time
(4.5 DCLOCKs)

Throughput rate
(22 DCLOCKs)

Clock frequency 0.024 6.0 0.024 6.0 MHz

= +2.5V, – IN = +2.5V, f

REF

Hold 5 5 G Ω

ON

Sampling 50 100 50 100 Ω

OS
OS

Positive – 32 ± 16 +32 – 32 ± 16 +32 LSB

ERR

Negative – 32 ± 16 +32 – 32 ± 16 +32 LSB

ERR

t

24kHz ≤ f

CONV

tAQf

CLK

CLK

= 6.0MHz 0.75 0.75 μ s

= +5V

DD

= 250kHz, and f

SAMPLE

REF

– 2 ± 0.75 +2 – 1 ± 0.5 +1 mV

≤ 6.0MHz 2.667 666.7 2.667 666.7 μ s

= 24 × f

CLK

ADS8317I ADS8317IB

± 3 ± 3 μ V/ ° C

± 0.1 ± 0.1 ppm/ ° C

, unless otherwise noted.

SAMPLE

V

REF

250 250 kSPS

– V

REF

V

REF

V

Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Link(s): ADS8317

www.ti.com

ADS8317

SBAS356A – JUNE 2007 – REVISED SEPTEMBER 2007

ELECTRICAL CHARACTERISTICS: V

At – 40 ° C to +85 ° C, V

= +2.5V, – IN = +2.5V, f

REF

= +5V (continued)

DD

SAMPLE

= 250kHz, and f

CLK

= 24 × f

SAMPLE

, unless otherwise noted.

ADS8317I ADS8317IB

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT

AC ACCURACY

5V

sinewave at 2kHz – 102 – 106 dB

Total harmonic distortion THD

Spurious-free dynamic range SFDR

Signal-to-noise ratio SNR

Signal-to-noise + distortion SINAD

Effective number of bits ENOB

PP

5V

sinewave at 10kHz – 100 – 104 dB

PP

5V

sinewave at 2kHz 106 110 dB

PP

5V

sinewave at 10kHz 104 109 dB

PP

5V

sinewave at 2kHz 89.6 90 dB

PP

5V

sinewave at 10kHz 89.6 90 dB

PP

5V

sinewave at 2kHz 89.5 89.9 dB

PP

5V

sinewave at 10kHz 89.4 89.8 dB

PP

5V

sinewave at 2kHz 14.57 14.65 Bits

PP

5V

sinewave at 10kHz 14.56 14.63 Bits

PP

VOLTAGE REFERENCE INPUT

Reference voltage 0.5 VDD/2 0.5 VDD/2 V

Reference input resistance

CS = GND, f
CS = V

DD

= 0Hz 5 5 G Ω

SAMPLE

5 5 G Ω

Reference input capacitance 24 24 pF

fS= 250kHz 35 52 35 52 μ A
fS= 200kHz 25 38 25 38 μ A

Reference input current fS= 100kHz 10 15 10 15 μ A

fS= 10kHz 1 2 1 2 μ A
CS = V

DIGITAL INPUTS

(1)

DD

0.1 0.1 μ A

Logic family CMOS CMOS
High-level input voltage V
Low-level input voltage V

IH

IL

0.7 × V

DD

– 0.3 0.3 × V

VDD+ 0.3 0.7 × V

DD

DD

VDD+ 0.3 V

– 0.3 0.3 × V

DD

Input current IINVI= VDDor GND – 50 +50 – 50 +50 nA
Input capacitance C

DIGITAL OUTPUTS

(1)

I

5 5 pF

Logic family CMOS CMOS
High-level output voltage V
Low-level output voltage V
High-impedance state output

current
Output capacitance C
Load capacitance C

VDD= 4.5V, IOH= – 100A 4.44 4.44 V

OH

VDD= 4.5V, IOL= 100A 0.5 0.5 V

OL

IOZCS = VDD, VI= VDDor GND – 50 +50 – 50 +50 nA

O

L

5 5 pF

30 30 pF

Data format Binary twos complement Binary twos complement

(1) Applies for 5.0V nominal supply: V

(min) = 4.5V and V

DD

(max) = 5.5V.

DD

V

4 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated

Product Folder Link(s): ADS8317

www.ti.com

ADS8317

SBAS356A – JUNE 2007 – REVISED SEPTEMBER 2007

ELECTRICAL CHARACTERISTICS: V

At – 40 ° C to +85 ° C, V

= +1.25V, – IN = 1.25V, f

REF

= +2.7V

DD

SAMPLE

= 200kHz, and f

CLK

= 24 × f

SAMPLE

, unless otherwise noted.

ADS8317I ADS8317IB

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT

ANALOG INPUT

Full-scale range FSR +IN – ( – IN) – V

REF

V

REF

– V

REF

V

REF

Absolute input range +IN – 0.1 VDD+ 0.1 – 0.1 VDD+ 0.1 V

Input resistance R

Hold 5 5 G Ω

ON

Sampling 100 150 100 150 Ω
Input capacitance During sampling 24 24 pF
Input leakage current ± 50 ± 50 nA
Differential input capacitance +IN to – IN, during sampling 20 20 pF
Full-power bandwidth FSBW fSsinewave, SINAD = 60dB 1000 1000 kHz

DC ACCURACY

Resolution 16 16 Bits
No missing codes NMC 16 16 16 16 Bits
Integral linearity error INL – 3 ± 2 +3 – 2 ± 1.5 +2 LSB
Differential linearity error DNL – 1 +1.5, – 1 +2.5 – 1 ± 1 +2 LSB
Offset error V
Offset error drift TCV

Gain error G

Gain error drift TCG

OS
OS

Positive – 32 ± 16 +32 – 32 ± 16 +32 LSB

ERR

Negative – 32 ± 16 +32 – 32 ± 16 +32 LSB

ERR

– 2 ± 1 +2 – 1 ± 0.5 +1 mV

± 0.4 ± 0.4 μ V/ ° C

± 0.15 ± 0.15 ppm/ ° C
Bipolar zero error – 2 ± 0.8 +2 – 1 ± 0.4 +1 mV
Bipolar zero error drift ± 0.2 ± 0.2 μ V/ ° C
Noise 50 50 μ VRMS
Power-supply rejection PSRR 2.7V ≤ VDD≤ 3.6V 1 1 LSB

SAMPLING DYNAMICS

Conversion time (16 DCLOCKs) t
Acquisition time (4.5 DCLOCKs) tAQf

24kHz ≤ f

CONV

CLK

≤ 4.8MHz 3.333 666.7 3.333 666.7 μ s

CLK

= 4.8MHz 0.9375 0.9375 μ s
Throughput rate (22 DCLOCKs) 200 200 kSPS
Clock frequency 0.024 4.8 0.024 4.8 MHz

AC ACCURACY

2.5V

sinewave at 2kHz – 104 – 107 dB

Total harmonic distortion THD

Spurious-free dynamic range SFDR

Signal-to-noise ratio SNR

Signal-to-noise + distortion SINAD

Effective number of bits ENOB

PP

2.5V

sinewave at 10kHz – 101 – 106 dB

PP

2.5V

sinewave at 2kHz 106 108 dB

PP

2.5V

sinewave at 10kHz 104 107 dB

PP

2.5V

sinewave at 2kHz 84.8 85 dB

PP

2.5V

sinewave at 10kHz 84.8 85 dB

PP

2.5V

sinewave at 2kHz 84.7 84.9 dB

PP

2.5V

sinewave at 10kHz 84.7 84.8 dB

PP

2.5V

sinewave at 2kHz 13.77 13.8 Bits

PP

2.5V

sinewave at 10kHz 13.77 13.79 Bits

PP

VOLTAGE REFERENCE INPUT

Reference voltage 1 VDD/2 1 VDD/2 V

Reference input resistance

CS = GND, f
CS = V

DD

= 0Hz 5 5 k Ω

SAMPLE

5 5 G Ω

Reference input capacitance 20 20 pF

fS= 200kHz 9 14 9 14 μ A

Reference input current

fS= 100kHz 3 5 3 5 μ A
fS= 10kHz 0.5 1 0.5 1 μ A
CS = V

DD

0.1 0.1 μ A

V

Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Link(s): ADS8317

www.ti.com

ADS8317

SBAS356A – JUNE 2007 – REVISED SEPTEMBER 2007

ELECTRICAL CHARACTERISTICS: V

At – 40 ° C to +85 ° C, V

= +1.25V, – IN = 1.25V, f

REF

= +2.7V (continued)

DD

SAMPLE

= 200kHz, and f

CLK

= 24 × f

SAMPLE

, unless otherwise noted.

ADS8317I ADS8317IB

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT

DIGITAL INPUTS

(1)

Logic family LVCMOS LVCMOS
High-level input voltage V
Low-level input voltage VILVDD= 2.7V – 0.3 0.8 – 0.3 0.3 × V

VDD= 3.6V 2 VDD+ 0.3 2 VDD+ 0.3 V

IH

DD

Input current IINVI= VDDor GND – 50 +50 – 50 +50 nA
Input capacitance C

DIGITAL OUTPUTS

(1)

I

5 5 pF

Logic family LVCMOS LVCMOS
High-level output voltage V
Low-level output voltage V
High-impedance state output

current
Output capacitance C
Load capacitance C

VDD= 2.7V, IOH= – 100A VDD– 0.2 VDD– 0.2 V

OH

VDD= 2.7V, IOL= 100A 0.2 0.2 V

OL

IOZCS = VDD, VI= VDDor GND – 50 +50 – 50 +50 nA

O

L

5 5 pF

30 30 pF

Data format Binary twos complement Binary twos complement

(1) Applies for 5.0V nominal supply: V

(min) = 2.7V and V

DD

(max) = 3.6V.

DD

ELECTRICAL CHARACTERISTICS: GENERAL

At – 40 ° C to +85 ° C, – IN = GND, and f

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT

ANALOG INPUT

Power supply V

Operating supply current I

Power-down supply current I

Power dissipation 3.8 5.4 3.8 5.4 mW

Power dissipation in power-down

Low-voltage levels 2.7 3.6 2.7 3.6 V

DD

5V logic levels 4.5 5.5 4.5 5.5 V
VDD= 2.7V, fS= 10kHz,

f

DCLOCK

VDD= 2.7V, fS= 100kHz,
f

DCLOCK

VDD= 2.7V, fS= 200kHz,

DD

f

DCLOCK

VDD= 5V, fS= 200kHz,
f

DCLOCK

VDD= 5V, fS= 250kHz,
f

DCLOCK

VDD= 2.7V 0.1 0.1 μ A

DD

VDD= 5V 0.2 0.2 μ A
VDD= 2.7V, fS= 10kHz,

f

DCLOCK

VDD= 2.7V, fS= 100kHz,
f

DCLOCK

VDD= 2.7V, fS= 200kHz,
f

DCLOCK

VDD= 5V, fS= 200kHz,
f

DCLOCK

VDD= 5V, fS= 250kHz,
f

DCLOCK

VDD= 2.7V, CS = V
VDD= 5V, CS = V

= 24 × f

DCLOCK

SAMPLE

, unless otherwise noted.

ADS8317I ADS8317IB

= 4.8MHz

= 4.8MHz

= 4.8MHz

= 6MHz

= 6MHz

= 4.8MHz

= 4.8MHz

0.065 0.085 0.065 0.085 mA

0.7 1.0 0.7 1.0 mA

1.4 2.0 1.4 2.0 mA

1.5 2.5 1.5 2.5 mA

2.0 3.0 2.0 3.0 mA

0.18 0.23 0.18 0.23 mW

1.9 2.7 1.9 2.7 mW

= 4.8MHz

= 6MHz

= 6MHz

DD

DD

7.5 12.5 7.5 12.5 mW

10 15 10 15 mW

0.3 0.3 μ W

0.6 0.6 μ W

V

6 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated

Product Folder Link(s): ADS8317

www.ti.com

1

2

3

4

8

7

6

5

V

DD

DCLOCK

D

OUT

CS/SHDN

REF

+IN

-IN

GND

ADS8317

REF

+IN

-IN

GND

V

DD

DCLOCK

D

OUT

CS/SHDN

1

2

3

4

8

7

6

5

ADS8317

(ThermalPad)

R
50W

ON

C

(SAMPLE)

24pF

V

DD

I/O

GND

V

DD

ANALOGIN

GND

DiodeTurn-OnVoltage:0.35V
EquivalentAnalogInputCircuit

V

DD

REF

GND

EquivalentReferenceInputCircuit

EquivalentDigitalInput/OutputCircuit

24pF

R
50W

ON

ADS8317

SBAS356A – JUNE 2007 – REVISED SEPTEMBER 2007

PIN CONFIGURATION

DGK PACKAGE

MSOP-8

(TOP VIEW)

DRB PACKAGE

(1)(2)

SON-8

(TOP VIEW)

(1) DRB package (SON-8) available Q1, 2008.
(2) The DRB package thermal pad must be soldered to the printed circuit board for proper thermal and mechanical

performance.

TERMINAL FUNCTIONS

TERMINAL

NAME NO. I/O DESCRIPTION

REF 1 Analog input Reference input
+IN 2 Analog input Noninverting analog input
– IN 3 Analog input Inverting analog input
GND 4 Power-supply connection Ground
CS/SHDN 5 Digital input Chip select when low; Shutdown mode when high.
D

OUT

DCLOCK 7 Digital input Data clock synchronizes the serial data transfer and determines conversion speed.
V

DD

6 Digital output Serial output data word

8 Power-supply connection Power supply

Equivalent Input Circuits (V

Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 7

= 5.0V)

DD

Product Folder Link(s): ADS8317

www.ti.com

D

OUT

1.4V

TestPoint

3kW

100pF
C

LOAD

LoadCircuitfort ,t ,andt

dDO r f

VoltageWaveformsforD RiseandFallTimes,t ,t

OUT r f

VoltageWaveformsforD DelayTimes,t

OUT dDO

VoltageWaveformsfort

dis

VoltageWaveformsfort

en

LoadCircuitfort andt

dis en

t

r

D

OUT

90%

10%

t

f

D

OUT

TestPoint

t Waveform2,t

dis en

V

DD

t Waveform1

dis

100pF

C

LOAD

3kW

t

dis

CS/SHDN

D

OUT

Waveform1

(3)

D

OUT

Waveform2

(4)

90%

10%

90%

41

B15

5

t

en

CS/SHDN

DCLOCK

D

OUT

t

dDO

D

OUT

DCLOCK

t

hDO

(3)Waveform1isforanoutputwithinternalconditionssuchthat

theoutputishighunlessdisabledbytheoutputcontrol.

(4)Waveform2isforanoutputwithinternalconditionssuchthat

theoutputislowunlessdisabledbytheoutputcontrol.

CS/SHDN

D

OUT

DCLOCK

t

CYC

PowerDown

ConversionSample

Usepositiveclockedgefordatatransfer

t

SUCS

t

CONV

t

SMPL

NOTE:(1)Aminimumof22clockcyclesarerequiredfor16-bitconversion;24clockcyclesareshown.

If remainslowattheendofconversion,anewdatastreamisshiftedoutwithLSB-firstdatafollowedbyzeroesindefinitely.CS

B15

(MSB)

B14 B13 B12 B11 B10 B9 B8

B0

(1)

(LSB)

B7 B1B6 B2B5 B3B4

Hi-Z

0

Hi-Z

t

CSD

NOTES:

CS/SHDN

D

OUT

DCLOCK

t

CONV

t

SUCS

t

CSD

t

CYC

PowerDown

t

SMPL

NOTE:(2)Aftercompletingthedatatransfer,iffurtherclocksareappliedwith low,theA/Dconverterwilloutputzeroesindefinitely.CS

B15

(MSB)

B14 B13 B12 B11 B6 B5 B4 B4B3 B3B2 B2B1 B1B0

Null

Bit

Hi-Z Hi-Z

B5 B0 B11 B12 B13 B14

B15

(2)

(LSB) (MSB)

ADS8317

SBAS356A – JUNE 2007 – REVISED SEPTEMBER 2007

TIMING INFORMATION

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Figure 1. Timing Diagrams

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SBAS356A – JUNE 2007 – REVISED SEPTEMBER 2007

TIMING INFORMATION (continued)

Timing Characteristics

SYMBOL DESCRIPTION MIN TYP MAX UNIT

t

SMPL

t

CONV

t

CYC

t

CSD

t

SUCS

t

HDO

t

DIS

t

EN

t

F

t

R

Analog input sample time 4.5 5.0 DCLOCKs
Conversion time 16 DCLOCKs
Complete cycle time 22 DCLOCKs
CS falling to DCLOCK low 0 ns
CS falling to DCLOCK rising 20 ns
DCLOCK falling to current D
CS rising to D
DCLOCK falling to D
D

fall time 5 25 ns

OUT

D

rise time 7 25 ns

OUT

3-state 70 100 ns

OUT

OUT

not valid 5 15 ns

OUT

enabled 20 50 ns

ADS8317

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Product Folder Link(s): ADS8317