BURR-BROWN ADS7866, ADS7867, ADS7868 User Manual
_
+
CDAC
SAR
Conversion
and
Control
Logic
Comparator
12/10/8 BIT ADC
VIN
REF/V
DD
CS
SCLK
SDO
GND
S/H
查询ADS7866IDBVR供应商
1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE
ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE
ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
FEATURES
• Single 1.2-V to 3.6-V Supply Operation
• High Throughput
– 200/240/280KSPS for 12/10/8-Bit V
– 100/120/140KSPS for 12/10/8-Bit V
• ± 1.5LSB INL, 12-Bit NMC (ADS7866)
• 71 dB SNR, –83 dB THD at fIN= 30 kHz
(ADS7866)
• Synchronized Conversion with SCLK
• SPI Compatible Serial Interface
• No Pipeline Delays
• Low Power
– 1.39 mW Typ at 200 KSPS, V
– 0.39 mW Typ at 200 KSPS, V
– 0.22 mW Typ at 100 KSPS, V
DD
DD
DD
• Auto Power-Down: 8 nA Typ, 300 nA Max
• 0 V to V
Unipolar Input Range
DD
• 6-Pin SOT-23 Package
APPLICATIONS
• Battery Powered Systems
• Isolated Data Acquisition
• Medical Instruments
• Portable Communication
• Portable Data Acquisition Systems
• Automatic Test Equipment
= 3.6 V
= 1.6 V
= 1.2 V
The sampling, conversion, and activation of digital
output SDO are initiated on the falling edge of CS.
The serial clock SCLK is used for controlling the
conversion rate and shifting data out of the converter.
≥ 1.6 V
DD
≥ 1.2 V
DD
Furthermore, SCLK provides a mechanism to allow
digital host processors to synchronize with the converter. These converters interface with
micro-processors or DSPs through a high-speed SPI
compatible serial interface. There are no pipeline
delays associated with the device.
The minimum conversion time is determined by the
frequency of the serial clock input, SCLK, while the
maximum frequency of SCLK is determined by the
minimum sampling time required to charge the input
capacitance to 12/10/8-bit accuracy for the
ADS7866/67/68, respectively. The maximum
throughput is determined by how often a conversion
is initiated when the minimum sampling time is met
and the maximum SCLK frequency is used. Each
device automatically powers down after each conversion, which allows each device to save power when
the throughput is reduced while using the maximum
SCLK frequency.
The converter reference is taken internally from the
supply. Hence, the analog input range for these
devices is 0 V to V
.
DD
These devices are available in a 6-pin SOT-23
package and are characterized over the industrial
–40 ° C to 85 ° C temperature range.
DESCRIPTION
The ADS7866/67/68 are low power, miniature,
12/10/8-bit A/D converters each with a unipolar,
single-ended input. These devices can operate from a
single 1.6 V to 3.6 V supply with a 200-KSPS
throughput for ADS7866. In addition, these devices
can maintain at least a 100-KSPS throughput with a
supply as low as 1.2 V.
Micro-Power Miniature SAR Converter Family
RESOLUTION/SPEED < 200 KSPS 1 MSPS – 1.25 MSPS
12-Bit ADS7866 (1.2 V
10-Bit ADS7867 (1.2 V
8-Bit ADS7868 (1.2 V
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
to 3.6 VDD) ADS7886 (2.35 V
DD
to 3.6 VDD) ADS7887 (2.35 V
DD
to 3.6 VDD) ADS7888 (2.35 V
DD
to 5.25 VDD)
DD
to 5.25 VDD)
DD
to 5.25 VDD)
DD
Copyright © 2005, Texas Instruments Incorporated
www.ti.com
ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
MAXIMUM MAXIMUM NO MISSING
MODEL MARKING TEMPERATURE MEDIA,
ADS7866I ± 1.5 –1/+1.5 12 SOT23-6 A66Y DBV –40 ° C to 85 ° C ADS7866IDBVT Small tape and reel, 250
ADS7866I ± 1.5 –1/+1.5 12 SOT23-6 A66Y DBV –40 ° C to 85 ° C ADS7866IDBVR Tape and reel, 3000
ADS7867I ± 0.5 ± 0.5 10 SOT23-6 A67Y DBV –40 ° C to 85 ° C ADS7867IDBVT Small tape and reel, 250
ADS7867I ± 0.5 ± 0.5 10 SOT23-6 A67Y DBV –40 ° C to 85 ° C ADS7867IDBVR Tape and reel, 3000
ADS7868I ± 0.5 ± 0.5 8 SOT23-6 A68Y DBV –40 ° C to 85 ° C ADS7868IDBVT Small tape and reel, 250
ADS7868I ± 0.5 ± 0.5 8 SOT23-6 A68Y DBV –40 ° C to 85 ° C ADS7868IDBVR Tape and reel, 3000
INTEGRAL DIFFERENTIAL CODES PACKAGE PACKAGE ORDERING
LINEARITY LINEARITY RESOLULTION TYPE DESIGNATOR NUMBER
(LSB) (LSB) (BIT)
PACKAGE SPECIFIED TRANSPORT
(SYMBOL) RANGE QUANTITY
(1)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
RATING
V
to GND –0.3 V to 4.0 V
DD
Analog input voltage to GND –0.3 V to V
Digital input voltage to GND –0.3 V to 4.0 V
Digital output voltage to GND –0.3 V to V
T
A
T
STORAGE
T
J
Operating free-air temperature range –40 ° C to 85 ° C
Storage temperature range –65 ° C to 150 ° C
Junction temperature 150 ° C
SOT-23 Package
Lead temperature,
soldering
θJAThermal impedance 110.9 ° C/W
θJCThermal impedance 22.31 ° C/W
Vapor phase (10–40 sec) 250 ° C
Infrared (10–30 sec) 260 ° C
ESD 3 kV
+ 0.3 V
DD
+ 0.3 V
DD
2
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ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
SPECIFICATIONS, ADS7866
At –40 ° C to 85 ° C, f
1.2 V ≤ V
SYSTEM PERFORMANCE
SAMPLING DYNAMICS (See Timing Characteristics Section)
t
CONVERT
t
SAMPLE
f
SAMPLE
DYNAMIC CHARACTERISTICS
SINAD dB
SNR Signal-to-noise ratio dB
THD Total harmonic distortion
SFDR dB
ANALOG INPUT
C
S
DIGITAL INPUT
V
IH
< 1.6 V (unless otherwise noted)
DD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 12 Bits
No missing codes 12 Bits
Integral linearity –1.5 1.5 LSB
Differential linearity –1 1.5 LSB
Offset error
Gain error
Total unadjusted error
Conversion time f
Acquisition time f
Throughput rate f
Aperture delay 10 ns
Aperture jitter 40 ps
Signal-to-noise
and distortion
Spurious free dynamic
range
Full-power bandwidth
Full-scale input span
Input capacitance 12 pF
Input leakage current –1 1 µA
Logic family , CMOS
Input logic high level V
(3)
SAMPLE
(2)
(7)
= 200 KSPS and f
1.2 V ≤ VDD< 1.6 V –2 2
1.6 V ≤ VDD≤ 3.6 V –3 3
1.2 V ≤ VDD< 1.6 V –2 2
1.6 V ≤ VDD≤ 3.6 V –2 2
1.2 V ≤ VDD< 1.6 V –2.5 2.5
(4)
1.6 V ≤ VDD≤ 3.6 V –3.5 3.5
= 3.4 MHz, 13 SCLK cycles 3.82 µs
SCLK
= 3.4 MHz, 1.6 V ≤ VDD≤ 3.6 V 0.64 µs
SCLK
= 3.4 MHz, 1.6 V ≤ VDD≤ 3.6 V 200 KSPS
SCLK
fIN= 30 kHz, 1.2 V ≤ VDD< 1.6 V 68
fIN= 30 kHz, 1.6 V ≤ VDD≤ 3.6 V 69 70
fIN= 30 kHz, 1.2 V ≤ VDD< 1.6 V 70
fIN= 30 kHz, 1.6 V ≤ VDD≤ 3.6 V 70 71
fIN= 30 kHz, 1.2 V ≤ VDD< 1.6 V –70
(5)
fIN= 30 kHz, 1.6 V ≤ VDD≤ 3.6 V –83
fIN= 30 kHz, 1.2 V ≤ VDD< 1.6 V 75
fIN= 30 kHz, 1.6 V ≤ VDD≤ 3.6 V 85
At 0.1 dB, 1.2 V ≤ VDD< 1.6 V 2
At 0.1 dB, 1.6 V ≤ VDD≤ 3.6 V 4
(6)
At 3 dB, 1.2 V ≤ VDD< 1.6 V 3
At 3 dB, 1.6 V ≤ VDD≤ 3.6 V 8
VIN – GND 0 V
1.2 V ≤ VDD< 1.6 V 0.7 × V
1.6 V ≤ VDD< 1.8 V 0.7 × V
1.8 V ≤ VDD< 2.5 V 0.7 × V
2.5 V ≤ VDD≤ 3.6 V 2 3.6
= 3.4 MHz if 1.6 V ≤ V
SCLK
≤ 3.6 V; f
DD
= 100 KSPS and f
SAMPLE
DD
DD
DD
SCLK
= 1.7 MHz if
DD
3.6
3.6
3.6
(1)
LSB
LSB
LSB
dB
MHz
V
(1) LSB = Least Significant BIt
(2) The difference in the first code transition 000...000 to 000...001 from the ideal value of GND + 1 LSB.
(3) The difference in the last code transition 011...111 to 111...111 from the ideal value of V
(4) The absolute difference from the ideal transfer function of the converter. This specification is similar to INL error except the effects of
- 1 LSB with the offset error removed.
DD
offset error and gain error are included.
(5) The 2nd through 10th harmonics are used to determine THD.
(6) Input frequency where the amplitude of the digitized signal has decreased by 0.1 dB or 3 dB.
(7) Ideal input span which does not include gain or offset errors.
3
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ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
SPECIFICATIONS, ADS7866 (continued)
At –40 ° C to 85 ° C, f
1.2 V ≤ V
V
IL
I
SCLK
I
CS
C
IN
DIGITAL OUTPUT
V
OH
V
OL
I
SDO
C
OUT
POWER SUPPLY REQUIREMENTS
V
DD
I
DD
I
DD
POWER DISSIPATION
TEMPERATURE RANGE
DD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input logic low level V
SCLK pin leakage current Digital input = 0 V or V
CS pin leakage current ± 1 µA
Digital input pin capacitance 10 pF
Output logic high level I
Output logic low level I
SDO pin leakage current Floating output –1 1 µA
Digital output pin
capacitance
Data format, straight binary
Supply voltage 1.2 3.6 V
Supply current, Digital inputs = 0 V
normal operation or V
Power-down mode SCLK on or off 0.008 0.3 µA
Normal operation f
Power-down mode SCLK on or off, VDD= 3.6 V 1.08 µW
Specified performance –40 85 ° C
SAMPLE
< 1.6 V (unless otherwise noted)
= 200 KSPS and f
= 3.4 MHz if 1.6 V ≤ V
SCLK
≤ 3.6 V; f
DD
= 100 KSPS and f
SAMPLE
1.2 V ≤ VDD< 1.6 V –0.2 0.2 × V
1.6 V ≤ VDD< 1.8 V –0.2 0.2 × V
1.8 V ≤ VDD< 2.5 V –0.2 0.3 × V
2.5 V ≤ VDD≤ 3.6 V –0.2 0.8
DD
= 200 µA VDD–0.2 V
SOURCE
= 200 µA 0 0.2 V
SINK
–1 0.02 1 µA
Floating output 10 pF
f
f
SAMPLE
SAMPLE
f
SAMPLE
DD
= 200 KSPS, f
= 200 KSPS, f
= 100 KSPS, f
= 200 KSPS, f
SAMPLE
f
= 100 KSPS, f
SAMPLE
f
= 50 KSPS, f
SAMPLE
f
= 20 KSPS, f
SAMPLE
f
= 200 KSPS, f
SAMPLE
f
= 100 KSPS, f
SAMPLE
f
= 50 KSPS, f
SAMPLE
f
= 20 KSPS, f
SAMPLE
f
= 200 KSPS, f
SAMPLE
f
= 100 KSPS, f
SAMPLE
f
= 50 KSPS, f
SAMPLE
f
= 20 KSPS, f
SAMPLE
f
= 200 KSPS, f
SAMPLE
f
= 100 KSPS, f
SAMPLE
f
= 50 KSPS, f
SAMPLE
f
= 20 KSPS, f
SAMPLE
f
= 200 KSPS, f
SAMPLE
f
= 100 KSPS, f
SAMPLE
f
= 50 KSPS, f
SAMPLE
f
= 20 KSPS, f
SAMPLE
f
= 100 KSPS, f
SAMPLE
f
= 50 KSPS, f
SAMPLE
f
= 20 KSPS, f
SAMPLE
= 3.4 MHz, VDD= 3.6 V 1.39 1.80
SCLK
= 3.4 MHz, VDD= 1.6 V 0.39 0.53 mW
SCLK
= 1.7 MHz, VDD= 1.2 V 0.22 0.3
SCLK
= 3.4 MHz, VDD= 3.6 V 385 500
SCLK
= 3.4 MHz, VDD= 3.6 V 193
SCLK
= 3.4 MHz, VDD= 3.6 V 97
SCLK
= 3.4 MHz, VDD= 3.6 V 39
SCLK
= 3.4 MHz, VDD= 3 V 340
SCLK
= 3.4 MHz, VDD= 3 V 170
SCLK
= 3.4 MHz, VDD= 3 V 85
SCLK
= 3.4 MHz, VDD= 3 V 35
SCLK
= 3.4 MHz, VDD= 2.5 V 305
SCLK
= 3.4 MHz, VDD= 2.5 V 153
SCLK
= 3.4 MHz, VDD= 2.5 V 77
SCLK
= 3.4 MHz, VDD= 2.5 V 31
SCLK
= 3.4 MHz, VDD= 1.8 V 256
SCLK
= 3.4 MHz, VDD= 1.8 V 128
SCLK
= 3.4 MHz, VDD= 1.8 V 65
SCLK
= 3.4 MHz, VDD= 1.8 V 26
SCLK
= 3.4 MHz, VDD= 1.6 V 241 330
SCLK
= 3.4 MHz, VDD= 1.6 V 121
SCLK
= 3.4 MHz, VDD= 1.6 V 61
SCLK
= 3.4 MHz, VDD= 1.6 V 25
SCLK
= 1.7 MHz, VDD= 1.2 V 186 250
SCLK
= 1.7 MHz, VDD= 1.2 V 93 µA
SCLK
= 1.7 MHz, VDD= 1.2 V 37
SCLK
SCLK
= 1.7 MHz if
DD
DD
DD
DD
V
µA
µA
µA
µA
µA
4
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ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
SPECIFICATIONS, ADS7867
At –40 ° C to 85 ° C, f
1.2 V ≤ V
SYSTEM PERFORMANCE
SAMPLING DYNAMICS (See Timing Characteristics Section)
t
CONVERT
t
SAMPLE
f
SAMPLE
DYNAMIC CHARACTERISTICS
SINAD dB
SNR Signal-to-noise ratio dB
THD Total harmonic distortion
SFDR Spurious free dynamic range dB
ANALOG INPUT
C
S
DIGITAL INPUT
V
IH
< 1.6 V (unless otherwise noted)
DD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 10 Bits
No missing codes 10 Bits
Integral linearity –0.5 0.5 LSB
Differential linearity –0.5 0.5 LSB
Offset error
Gain error
(3)
Total unadjusted error
Conversion time f
Acquisition time f
Throughput rate f
Aperture delay 10 ns
Aperture jitter 40 ps
Signal-to-noise
and distortion
Full-power bandwidth
Full-scale input span
Input capacitance 12 pF
Input leakage current –1 1 µA
Logic family, CMOS
Input logic high level V
= 240 KSPS and f
SAMPLE
(2)
(7)
= 3.4 MHz if 1.6 V ≤ V
SCLK
≤ 3.6 V; f
DD
= 120 KSPS and f
SAMPLE
1.2 V ≤ VDD< 1.6 V –0.75 0.75
1.6 V ≤ VDD≤ 3.6 V –1 1
1.2 V ≤ VDD< 1.6 V –0.5 0.5
1.6 V ≤ VDD≤ 3.6 V –0.5 0.5
1.2 V ≤ VDD< 1.6 V –2 2
(4)
1.6 V ≤ VDD≤ 3.6 V –2 2
= 3.4 MHz, 11 SCLK cycles 3.235 µs
SCLK
= 3.4 MHz, 1.6 V ≤ VDD≤ 3.6 V 0.64 µs
SCLK
= 3.4 MHz, 1.6 V ≤ VDD≤ 3.6 V 240 KSPS
SCLK
f
= 100 KSPS, fIN= 30 kHz, 1.2 V ≤ VDD< 1.6 V 61
SAMPLE
f
= 200 KSPS, fIN= 30 kHz, 1.6 V ≤ VDD≤ 3.6 V 61 61.7
SAMPLE
f
= 100 KSPS, fIN= 30 kHz, 1.2 V ≤ VDD< 1.6 V 61.5
SAMPLE
f
= 200 KSPS, fIN= 30 kHz, 1.6 V ≤ VDD≤ 3.6 V 61.8
SAMPLE
f
= 100 KSPS, fIN= 30 kHz, 1.2 V ≤ VDD< 1.6 V -68
SAMPLE
(5)
f
= 200 KSPS, fIN= 30 kHz, 1.6 V ≤ VDD≤ 3.6 V -78 -72
SAMPLE
f
= 100 KSPS, fIN= 30 kHz, 1.2 V ≤ VDD< 1.6 V 73
SAMPLE
f
= 200 KSPS, fIN= 30 kHz, 1.6 V ≤ VDD≤ 3.6 V 74 80
SAMPLE
At 0.1 dB, 1.2 V ≤ VDD< 1.6 V 2
At 0.1 dB, 1.6 V ≤ VDD≤ 3.6 V 4
(6)
At 3 dB, 1.2 V ≤ VDD< 1.6 V 3
At 3 dB, 1.6 V ≤ VDD≤ 3.6 V 8
VIN – GND 0 V
1.2 V ≤ VDD< 1.6 V 0.7 × V
1.6 V ≤ VDD< 1.8 V 0.7 × V
1.8 V ≤ VDD< 2.5 V 0.7 × V
2.5 V ≤ VDD≤ 3.6 V 2 3.6
= 1.7 MHz if
SCLK
DD
DD
DD
DD
3.6
3.6
3.6
(1)
LSB
LSB
LSB
dB
MHz
V
(1) LSB = Least Significant BIt
(2) The difference in the first code transition 000...000 to 000...001 from the ideal value of GND + 1 LSB.
(3) The difference in the last code transition 011...111 to 111...111 from the ideal value of V
(4) The absolute difference from the ideal transfer function of the converter. This specification is similar to INL error except the effects of
- 1 LSB with the offset error removed.
DD
offset error and gain error are included.
(5) The 2nd through 10th harmonics are used to determine THD.
(6) Input frequency where the amplitude of the digitized signal has decreased by 0.1 dB or 3 dB.
(7) Ideal input span which does not include gain or offset errors.
5
www.ti.com
ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
SPECIFICATIONS, ADS7867 (continued)
At –40 ° C to 85 ° C, f
1.2 V ≤ V
V
IL
I
SCLK
I
CS
C
IN
DIGITAL OUTPUT
V
OH
V
OL
I
SDO
C
OUT
POWER SUPPLY REQUIREMENTS
V
DD
I
DD
I
DD
POWER DISSIPATION
TEMPERATURE RANGE
DD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input logic low level V
SCLK pin leakage current Digital input = 0 V or V
CS pin leakage current ± 1 µA
Digital input pin capacitance 10 pF
Output logic high level I
Output logic low level I
SDO pin leakage current Floating output –1 1 µA
Digital output pin
capacitance
Data format, straight binary
Supply voltage 1.2 3.6 V
Supply current, Digital Inputs = 0 V
normal operation or V
Power-down mode SCLK on or off 0.008 0.3 µA
Normal operation f
Power-down mode SCLK on or off, VDD= 3.6 V 1.08 µW
Specified performance –40 85 ° C
SAMPLE
< 1.6 V (unless otherwise noted)
= 240 KSPS and f
1.2 V ≤ VDD< 1.6 V –0.2 0.2 × V
1.6 V ≤ VDD< 1.8 V –0.2 0.2 × V
1.8 V ≤ VDD< 2.5 V –0.2 0.3 × V
2.5 V ≤ VDD≤ 3.6 V –0.2 0.8
= 200 µA VDD–0.2 V
SOURCE
= 200 µA 0 0.2 V
SINK
Floating output 10 pF
DD
f
= 240 KSPS, f
SAMPLE
= 240 KSPS, f
SAMPLE
f
= 120 KSPS, f
SAMPLE
= 3.4 MHz if 1.6 V ≤ V
SCLK
DD
f
= 240 KSPS, f
SAMPLE
f
= 100 KSPS, f
SAMPLE
f
= 240 KSPS, f
SAMPLE
f
= 100 KSPS, f
SAMPLE
f
= 120 KSPS, f
SAMPLE
f
= 50 KSPS, f
SAMPLE
= 3.4 MHz, VDD= 3.6 V 1.51 1.80
SCLK
= 3.4 MHz, VDD= 1.6 V 0.42 0.53 mW
SCLK
= 1.7 MHz, VDD= 1.2 V 0.24 0.30
SCLK
≤ 3.6 V; f
DD
= 120 KSPS and f
SAMPLE
–1 0.02 1 µA
= 3.4 MHz, VDD= 3.6 V 420 500
SCLK
= 3.4 MHz, VDD= 3.6 V 172
SCLK
= 3.4 MHz, VDD= 1.6 V 261 330
SCLK
= 3.4 MHz, VDD= 1.6 V 107
SCLK
= 1.7 MHz, VDD= 1.2 V 202 250
SCLK
= 1.7 MHz, VDD= 1.2 V 83
SCLK
SCLK
= 1.7 MHz if
DD
DD
DD
DD
V
µA
µA
µA
6
www.ti.com
ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
SPECIFICATIONS, ADS7868
At –40 ° C to 85 ° C, f
1.2 V ≤ V
SYSTEM PERFORMANCE
SAMPLING DYNAMICS (See Timing Characteristics Section)
t
CONVERT
t
SAMPLE
f
SAMPLE
DYNAMIC CHARACTERISTICS
SINAD dB
SNR Signal-to-noise ratio dB
THD dB
SFDR dB
ANALOG INPUT
C
S
DIGITAL INPUT
V
IH
< 1.6 V (unless otherwise noted)
DD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 8 Bits
No missing codes 8 Bits
Integral linearity –0.5 0.5 LSB
Differential linearity –0.5 0.5 LSB
Offset error
Gain error
(3)
Total unadjusted error
Conversion time f
Acquisition time f
Throughput rate f
Aperture delay 10 ns
Aperture jitter 40 ps
Signal-to-noise
and distortion
Total harmonic
(5)
distortion
Spurious free dynamic
range
Full-power bandwidth
Full-scale input span
Input capacitance 12 pF
Input leakage current –1 1 µA
Logic family, CMOS
Input logic high level V
= 280 KSPS and f
SAMPLE
(2)
(7)
= 3.4 MHz if 1.6 V ≤ V
SCLK
≤ 3.6 V; f
DD
= 140 KSPS and f
SAMPLE
1.2 V ≤ VDD< 1.6 V –0.5 0.5
1.6 V ≤ VDD≤ 3.6 V –0.5 0.5
1.2 V ≤ VDD< 1.6 V –0.5 0.5
1.6 V ≤ VDD≤ 3.6 V –0.5 0.5
1.2 V ≤ VDD< 1.6 V –1 1
(4)
1.6 V ≤ VDD≤ 3.6 V –1 1
= 3.4 MHz, 9 SCLK cycles 2.647 µs
SCLK
= 3.4 MHz, 1.6 V ≤ VDD≤ 3.6 V 0.64 µs
SCLK
= 3.4 MHz, 1.6 V ≤ VDD≤ 3.6 V 280 KSPS
SCLK
f
= 100 KSPS, fIN= 30 kHz, 1.2 V ≤ VDD< 1.6 V 49
SAMPLE
f
= 200 KSPS, fIN= 30 kHz, 1.6 V ≤ VDD≤ 3.6 V 49 49.4
SAMPLE
f
= 100 KSPS, fIN= 30 kHz, 1.2 V ≤ VDD< 1.6 V 49.4
SAMPLE
f
= 200 KSPS, fIN= 30 kHz, 1.6 V ≤ VDD≤ 3.6 V 49.8
SAMPLE
f
= 100 KSPS, fIN= 30 kHz, 1.2 V ≤ VDD< 1.6 V –65
SAMPLE
f
= 200 KSPS, fIN= 30 kHz, 1.6 V ≤ VDD≤ 3.6 V –72 -66
SAMPLE
f
= 100 KSPS, fIN= 30 kHz, 1.2 V ≤ VDD< 1.6 V 67
SAMPLE
f
= 200 KSPS, fIN= 30 kHz, 1.6 V ≤ VDD≤ 3.6 V 66 67
SAMPLE
At 0.1 dB, 1.2 V ≤ VDD< 1.6 V 2
At 0.1 dB, 1.6 V ≤ VDD≤ 3.6 V 4
(6)
At 3 dB, 1.2 V ≤ VDD< 1.6 V 3
At 3 dB, 1.6 V ≤ VDD≤ 3.6 V 8
VIN – GND 0 V
1.2 V ≤ VDD< 1.6 V 0.7 × V
1.6 V ≤ VDD< 1.8 V 0.7 × V
1.8 V ≤ VDD< 2.5 V 0.7 × V
DD
DD
DD
2.5 V ≤ VDD≤ 3.6 V 2 3.6
SCLK
= 1.7 MHz if
DD
3.6
3.6
3.6
(1)
LSB
LSB
LSB
MHz
V
(1) LSB = Least Significant BIt
(2) The difference in the first code transition 000...000 to 000...001 from the ideal value of GND + 1 LSB.
(3) The difference in the last code transition 011...111 to 111...111 from the ideal value of V
(4) The absolute difference from the ideal transfer function of the converter. This specification is similar to INL error except the effects of
- 1 LSB with the offset error removed.
DD
offset error and gain error are included.
(5) The 2nd through 10th harmonics are used to determine THD.
(6) Input frequency where the amplitude of the digitized signal has decreased by 0.1 dB or 3 dB.
(7) Ideal input span which does not include gain or offset errors.
7
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ADS7866
ADS7867
ADS7868
SLAS465 – JUNE 2005
SPECIFICATIONS, ADS7868 (continued)
At –40 ° C to 85 ° C, f
1.2 V ≤ V
V
IL
I
SCLK
I
CS
C
IN
DIGITAL OUTPUT
V
OH
V
OL
I
SDO
C
OUT
POWER SUPPLY REQUIREMENTS
V
DD
I
DD
I
DD
POWER DISSIPATION
TEMPERATURE RANGE
DD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input logic low level V
SCLK pin leakage current Digital input = 0 V or V
CS pin leakage current ± 1 µA
Digital input pin
capacitance
Output logic high level I
Output logic low level I
SDO pin leakage current Floating output –1 1 µA
Digital output pin
capacitance
Data format, straight
binary
Supply voltage 1.2 3.6 V
Supply current, Digital Inputs = 0 V
normal operation or V
Power-down mode SCLK on or off 0.008 0.3 µA
Normal operation f
Power-down mode SCLK on or off, VDD= 3.6 V 1.08 µW
Specified performance –40 85 ° C
SAMPLE
< 1.6 V (unless otherwise noted)
= 280 KSPS and f
= 3.4 MHz if 1.6 V ≤ V
SCLK
≤ 3.6 V; f
DD
= 140 KSPS and f
SAMPLE
1.2 V ≤ VDD< 1.6 V –0.2 0.2 × V
1.6 V ≤ VDD< 1.8 V –0.2 0.2 × V
1.8 V ≤ VDD< 2.5 V –0.2 0.3 × V
2.5 V ≤ VDD≤ 3.6 V –0.2 0.8
DD
= 200 µA VDD–0.2 V
SOURCE
= 200 µA 0 0.2 V
SINK
–1 0.02 1 µA
Floating output 10 pF
f
f
SAMPLE
SAMPLE
f
SAMPLE
DD
= 280 KSPS, f
= 280 KSPS, f
= 140 KSPS, f
= 280 KSPS, f
SAMPLE
f
= 100 KSPS, f
SAMPLE
f
= 280 KSPS, f
SAMPLE
f
= 100 KSPS, f
SAMPLE
f
= 140 KSPS, f
SAMPLE
f
= 50 KSPS, f
SAMPLE
= 3.4 MHz, VDD= 3.6 V 1.58 1.8
SCLK
= 3.4 MHz, VDD= 1.6 V 0.42 0.53 mW
SCLK
= 1.7 MHz, VDD= 1.2 V 0.24 0.3
SCLK
= 3.4 MHz, VDD= 3.6 V 439 500
SCLK
= 3.4 MHz, VDD= 3.6 V 154
SCLK
= 3.4 MHz, VDD= 1.6 V 264 330
SCLK
= 3.4 MHz, VDD= 1.6 V 93
SCLK
= 1.7 MHz, VDD= 1.2 V 201 250
SCLK
= 1.7 MHz, VDD= 1.2 V 70
SCLK
SCLK
= 1.7 MHz if
DD
DD
DD
10 pF
DD
V
µA
µA
µA
8
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