BURR-BROWN ADS5500 User Manual
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
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SBAS303C − DECEMBER 2003 − REVISED MARCH 200
FEATURES
D 14-Bit Resolution
D Recommended Amplifiers:
OPA695, OPA847, THS3201, THS3202,
THS4503, THS9001
D 125MSPS Sample Rate
D High SNR: 70.5dBFS at 100MHz f
D High SFDR: 82dBc at 100MHz f
D 2.3V
Differential Input Voltage
PP
IN
IN
D Internal Voltage Reference
D 3.3V Single-Supply Voltage
D Analog Power Dissipation: 578mW
− Total Power Dissipation: 780mW
D Serial Programming Interface
D TQFP-64 PowerPADE Package
APPLICATIONS
D Wireless Communication
− Communication Receivers
− Base Station Infrastructure
D Test and Measurement Instrumentation
D Single and Multichannel Digital Receivers
D Communication Instrumentation
− Radar, Infrared
D Video and Imaging
D Medical Equipment
DESCRIPTION
The ADS5500 is a high-performance, 14-bit, 125MSPS analog-to-digital converter (ADC). To provide a complete
converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed
for applications demanding the highest speed and highest dynamic performance in very little space, the ADS5500
has excellent power consumption of 780mW at 3.3V single-supply voltage. This allows an even higher system
integration density. The provided internal reference simplifies system design requirements. Parallel CMOScompatible output ensures seamless interfacing with common logic.
The ADS5500 is available in a 64-pin TQFP PowerPAD package and is specified over the full temperature range of
−40°C to +85°C.
AV
DD
DRV
DD
CLK+
−
CLK
+
V
IN
−
V
IN
CM
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
! " #$ " %$&# '( '$#"
#! "%##" % ) !" *" "$!" "'' +,(
'$# %#"" '" #"", #$' " %!"(
S&H
Internal
Reference
A
GND
Timing Circuitry
14−Bit
Pipeline
ADC Core
Serial Programming Register
SEN SDATA
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Digital
Error
Correction
Control Logic
SCLK
Output
Control
ADS5500
DR
GND
Copyright 2003−2004, Texas Instruments Incorporated
D0
D13
.
.
.
CLKOUT
OVR
DFS
HTQFP-64
(2)
ADS5500
HTQFP-64
(2)
PAP
−40°C to +85°C
ADS5500I
Voltage
ADCLK input sample
ADCLK input sample
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
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PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE−LEAD
PowerPAD
(1)
For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet.
(2)
Thermal pad size: 3.5mm x 3.5mm (min), 4mm x 4mm (max).
PACKAGE
DESIGNATOR
ABSOLUTE MAXIMUM RATINGS
over operat i n g f ree-air temperature range unless otherwise noted
ADS5500 UNIT
Supply
Analog input to A
Logic input to DR
Digital data output to DR
Input current (any input) 30 mA
Operating temperature range −40 to +85 °C
Junction temperature +105 °C
Storage temperature range −65 to +150 °C
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only , an d
functional operation of the device at these or any other conditions
beyond those specified is not implied.
AVDD to A
DRVDD to DR
A
to DR
GND
GND
GND
GND
GND
GND
GND
,
−0.3 to +3.7 V
±0.1 V
−0.15 to +2.5 V
−0.3 t o D RVDD + 0.3 V
−0.3 t o D RVDD + 0.3 V
(1)
SPECIFIED
TEMPERATURE
(1)
RANGE
PACKAGE
MARKING
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible t o damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING
NUMBER
ADS5500IPAP Tray, 160
ADS5500IPAPR Tape and Reel, 1000
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supplies
Analog supply voltage, AV
Output driver supply voltage, DRV
Analog Input
Differential input range 2.3 V
Input common-mode voltage, V
Digital Output
Maximum output load 10 pF
Clock Input
rate (sine wave) 1/t
Clock amplitude, sine wave,
differential
Clock duty cycle
Open free-air temperature range −40 +85 °C
(1)
(2)
(3)
(2)
(3)
Input common-mode should be connected to CM.
See Figure 13 for more information.
See Figure 12 for more information.
DD
CM
DLL ON 60 125 MSPS
DLL OFF 10 80 MSPS
C
MIN TYP MAX UNIT
3.0 3.3 3.6 V
3.0 3.3 3.6 V
DD
(1)
1.5 1.6 V
TRANSPORT
MEDIA, QUANTITY
PP
3 V
50 %
PP
2
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fIN = 10MHz
Signal-to-noise ratio, SNR
fIN = 70MHz
fIN = 10MHz
Spurious-free dynamic range, SFDR
fIN = 70MHz
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS
Typ, min, and max values at TA = +25°C, full temperature range is T
cycle, AVDD = DRVDD = 3.3V , DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted.
= −40°C to t
MIN
= +85°C, sampling rate = 125MSPS, 50% clock duty
MAX
PARAMETER
Resolution 14 Tested Bits
Analog Inputs
Differential input range 2.3 V
Differential input impedance See Figure 4 6.6 kΩ
Differential input capacitance See Figure 4 4 pF
Total analog input common-mode current 4
Analog input bandwidth Source impedance = 50Ω 750 MHz
Conversion Characteristics
Maximum sample rate see note (2) 125 MSPS
Data latency See timing diagram, Figure 1 16.5 Clock Cycles
Internal Reference Voltages
Reference bottom voltage, V
Reference top voltage, V
Reference error −4 ±0.9 +4 %
Common-mode voltage output, V
Dynamic DC Characteristics and Accuracy
No missing codes Tested
Differential linearity error , DNL fIN = 10MHz −0.9 ±0.75 +1.1 LSB
Integral linearity error, INL fIN = 10MHz −5 ±2.5 +5 LSB
Offset error ±1.5 mV
Offset temperature coefficient 0.0007 %/°C
Gain error ±0.45 %FS
Gain temperature coefficient 0.01 ∆%/°C
Dynamic AC Characteristics
Signal-to-noise ratio, SNR
RMS Output noise Input tied to common-mode 1.1 LSB
Spurious-free dynamic range, SFDR
(1)
2mA per input.
(2)
See Reccommended Operating Conditions on page 2.
REFM
REFP
CM
fIN = 30MHz 71.5 dBFS
fIN = 55MHz 71.5 dBFS
fIN = 100MHz 70.5 dBFS
fIN = 150MHz 70.1 dBFS
fIN = 225MHz 69.1 dBFS
fIN = 30MHz 84 dBc
fIN = 55MHz 79 dBc
fIN = 100MHz 82 dBc
fIN = 150MHz 78 dBc
fIN = 225MHz 74 dBc
CONDITIONS MIN TYP MAX UNIT
PP
(1)
0.97 V
2.11 V
1.55 ± 0.05 V
Room temp 70.5 71.5 dBFS
Full temp range 69 71.5 dBFS
Room temp 70 71.2 dBFS
Full temp range 68.5 71 dBFS
Room temp 82 84 dBc
Full temp range 78 84 dBc
Room temp 80 83 dBc
Full temp range 77 82 dBc
mA
3
fIN = 10MHz
Second-harmonic, HD2
fIN = 70MHz
fIN = 10MHz
Third-harmonic, HD3
fIN = 70MHz
Worst-harmonic/spur
Worst-harmonic/spur
fIN = 10MHz
Signal-to-noise + distortion, SINAD
fIN = 70MHz
fIN = 10MHz
Total harmonic distortion, THD
fIN = 70MHz
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (continued)
Typ, min, and max values at TA = +25°C, full temperature range is T
cycle, AVDD = DRVDD = 3.3V , DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted.
PARAMETER UNITMAXTYPMINCONDITIONS
fIN = 30MHz 86 dBc
fIN = 55MHz 84 dBc
Second-harmonic, HD2
fIN = 100MHz 84 dBc
fIN = 150MHz 78 dBc
fIN = 225MHz 74 dBc
fIN = 30MHz 90 dBc
fIN = 55MHz 79 dBc
Third-harmonic, HD3
fIN = 100MHz 82 dBc
fIN = 150MHz 80 dBc
fIN = 225MHz 76 dBc
fIN = 10MHz Room temp 88 dBc
(other than HD2 and HD3)
Signal-to-noise + distortion, SINAD
Total harmonic distortion, THD
fIN = 70MHz Room temp 86 dBc
fIN = 30MHz 70 dBc
fIN = 55MHz 69.5 dBc
fIN = 100MHz 69 dBc
fIN = 150MHz 69 dBc
fIN = 225MHz 66.4 dBc
fIN = 30MHz 82 dBc
fIN = 55MHz 77 dBc
fIN = 100MHz 79 dBc
fIN = 150MHz 75 dBc
fIN = 225MHz 71.8 dBc
= −40°C to t
MIN
Room temp 82 91 dBc
Full temp range 78 86 dBc
Room temp 80 87 dBc
Full temp range 77 83 dBc
Room temp 82 89 dBc
Full temp range 78 88 dBc
Room temp 80 85 dBc
Full temp range 77 82 dBc
Room temp 69 70 dBc
Full temp range 67.5 70 dBc
Room temp 68.5 69 dBc
Full temp range 67 69.5 dBc
Room temp 80 85 dBc
Full temp range 78 83 dBc
Room temp 77.5 81 dBc
Full temp range 76 79.5 dBc
= +85°C, sampling rate = 125MSPS, 50% clock duty
MAX
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4
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SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (continued)
Typ, min, and max values at TA = +25°C, full temperature range is T
cycle, AVDD = DRVDD = 3.3V , DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted.
PARAMETER UNITMAXTYPMINCONDITIONS
Effective number of bits, ENOB fIN = 70MHz 11.3 Bits
f = 10.1MHz, 15.1MHz
(−7dBFS each tone)
Two-tone intermodulation distortion, IMD
Power Supply
Total supply current, I
Analog supply current, I
Output buffer supply current, I
Power dissipation Total power with 10pF load on
Standby power With clocks running 181 250 mW
CC
AVDD
DRVDD
f = 30.1MHz, 35.1MHz
(−7dBFS each tone)
f = 50.1MHz, 55.1MHz
(−7dBFS each tone)
VIN = full-scale, fIN = 55MHz
AVDD = DRVDD = 3.3V
VIN = full-scale, fIN = 55MHz
AVDD = DRVDD = 3.3V
VIN = full-scale, fIN = 55MHz
AVDD = DRVDD = 3.3V
Analog only 578 627 mW
digital output to ground
= −40°C to t
MIN
= +85°C, sampling rate = 125MSPS, 50% clock duty
MAX
85 dBc
85 dBc
88 dBc
236 265 mA
175 190 mA
61 75 mA
780 875 mW
DIGITAL CHARACTERISTICS
Typ, min, and max values at TA = +25°C, full temperature range is T
cycle, AVDD = DRVDD = 3.3V , DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNIT
Digital Inputs
High-level input voltage 2.4 V
Low-level input voltage 0.8 V
High-level input current 10 µA
Low-level input current 10 µA
Input current for RESET −20 µA
Input capacitance 4 pF
Digital Outputs
Low-level output voltage C
High-level output voltage C
Output capacitance 3 pF
(1)
For optimal performance, all digital output lines (D0:D13), including the output clock, should see a similar load.
(2)
Equivalent capacitance to ground of (load + parasitics of transmission lines).
(1)
LOAD
LOAD
= 10pF
= 10pF
(2)
, fS = 125MSPS 0.3 V
(2)
, fS = 125MSPS 3.0 V
= −40°C to t
MIN
= +85°C, sampling rate = 125MSPS, 50% clock duty
MAX
5
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
TIMING CHARACTERISTCS
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Analog
Signal
Input Clock
Output Clock
Data Out
(D0−D13)
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing
matches closely with the specified values.
Input
Sample
N
N+1
t
A
N−17 N−16 N−15 N−13 N−3N−2N−1N
N+2
N+3
16.5 Clock Cycles
N+4
N+15
N+16
N+17
t
PDI
t
SETUP
Data Invalid
Figure 1. Timing Diagram
TIMING CHARACTERISTICS
Typ, min, and max values at TA = +25°C, full temperature range is T
cycle, AVDD = DRVDD = 3.3V , DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted.
PARAMETER DESCRIPTION MIN TYP MAX UNIT
Switching Specification
Aperture delay, t
Aperture jitter (uncertainty) Uncertainty in sampling instant 300 fs
Data setup time, t
Data hold time, t
Data latency, tD(Pipe)
Propagation delay, t
Data rise time Data out 20% to 80% 2.5 ns
Data fall time Data out 80% to 20% 2.5 ns
Output enable (OE) to
output stable delay
A
SETUP
HOLD
PDI
Input CLK falling edge to data sampling point 1 ns
Data valid to 50% of CLKOUT rising edge 2 ns
CLKOUT rising edge to data becoming invalid 1.7 ns
Input clock falling edge (on which sampling
takes place) to input clock rising edge (on
which the corresponding data is given out)
Input clock rising edge to data valid 7.5 ns
= −40°C to t
MIN
= +85°C, sampling rate = 125MSPS, 50% clock duty
MAX
16.5 Clock Cycles
2 ms
t
HOLD
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The device has a three-wire serial interface. The device
latches the serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
D Serial shift of bits is enabled when SEN is low.
SCLK shifts serial data at falling edge.
D Minimum width of data stream for a valid loading is
16 clocks.
6
D Data is loaded at every 16th SCLK falling edge
while SEN is low.
D In case the word length exceeds a multiple of 16
bits, the excess bits are ignored.
D Data can be loaded in multiple of 16-bit words within
a single active SEN pulse.
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SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
SDATA
A3
MSB
A2 A1 A0 D11 D10 D9 D0
ADDRESS
Figure 2. DATA Communication is 2-Byte, MSB First
t
SEN
SCLK
SDAT A
SLOADS
t
t
OS
MSB LSB LSBMSB
WSCLK
t
OH
t
WSCLK
Figure 3. Serial Programming Interface Timing Diagram
Table 1. Serial Programming Interface Timing Characteristics
SYMBOL PARAMETER MIN
t
SCLK
t
WSCLK
t
SLOADS
t
SLOADH
t
DS
t
DH
(1)
Min, typ, and max values are characterized, but not production tested.
SCLK Period 50 ns
SCLK Duty Cycle 25 50 75 %
SEN to SCLK setup time 8 ns
SCLK to SEN hold time 6 ns
Data Setup Time 8 ns
Data Hold Time 6 ns
t
SCLK
16 x M
(1)
DATA
TYP
(1)
t
SLOADH
MAX
(1)
UNIT
Table 2. Serial Register Table
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
1 1 0 1 0 0 0 0 0 0 0 0 0 0 DLL
1 1 1 0 0 TP<1> TP<0> 0 0 0 0 0 0 0 0 0 TP<1:0> − Test modes for output data capture
1 1 1 1 PDN 0 0 0 0 0 0 0 0 0 0 0 PDN = 0 : Normal mode of operation, PDN = 1 :
0 DLL OFF = 0 : internal DLL is on, recommended for
OFF
60−125MSPS clock speed
DLL OFF = 1 : internal DLL is off, recommended for
10−80MSPS clock speed
TP<1> = 0, TP<0> = 0 : Normal mode of operation,
TP<1> = 0
TP<0> = 1 : All output lines are pulled to ’0’, TP<1> = 1
TP<0> = 0 : All output lines are pulled to ’1’, TP<1> = 1
TP<0> = 1 : A continuous stream of ’10’ comes out on
all output lines
Device is put in power down (low current) mode
7
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
Table 3. DATA FORMAT SELECT (DFS TABLE)
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DFS-PIN VOLTAGE (V
1
V
t
DFS
5
AVDDu V
12
2
AVDDu V
3
V
DFS
AV
6
u
DFS
7
u
DFS
12
5
u
AV
6
PIN CONFIGURATION
1
DR
GND
2
SCLK
SEN
AV
A
GND
AV
A
GND
AV
CLKP
CLKM
A
GND
A
GND
A
GND
AV
A
GND
3
4
5
DD
6
7
DD
8
9
DD
10
11
12
13
14
15
DD
16
SDATA
) DAT A FORMAT CLOCK OUTPUT POLARITY
DFS
DD
1
3
DD
AV
AV
DD
DD
Straight Binary Data valid on rising edge
Two’s Complement Data valid on rising edge
Straight Binary Data valid on falling edge
Two’s Complement Data valid on falling edge
PAP PACKAGE
(TOP VIEW)
GND
OVR
D13 (MSB)
D12
D11
D10
DR
GND
DRVDDDR
D9
D8
64 63 62 61 60 59 58 57 56 55 54
ADS5500
PowerPAD
(Connected to Analog Ground)
17 18 19 20 21 22 23 24 25 26 27
CM
GND
INP
A
INM
DD
GND
A
AV
DD
GND
A
AV
DD
GND
A
AV
D7
D6
D5
D4
53 52 51 50 49
28 29 30 31 32
DD
GND
A
AV
REFP
REFM
GND
DR
IREF
DD
DRV
GND
A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DR
GND
D3
D2
D1
D0 (LSB)
CLKOUT
DR
GND
OE
DFS
AV
DD
A
GND
AV
DD
A
GND
RESET
AV
DD
AV
DD
8
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SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
PIN ASSIGNMENTS
TERMINAL NO.
NAME NO. OF PINS I/O DESCRIPTION
AV
DD
A
GND
DRV
DD
DR
GND
INP 19 1 I Differential analog input (positive)
INM 20 1 I Differential analog input (negative)
REFP 29 1 O Reference voltage (positive); 0.1µF capacitor in series with a 1Ω
REFM 30 1 O Reference voltage (negative); 0.1µF capacitor in series with a 1Ω
IREF 31 1 I Current set; 56kΩ resistor to GND; do not connect capacitors
CM 17 1 O Common-mode output voltage
RESET 35 1 I Reset (active high), 200kΩ resistor to AV
OE 41 1 I Output enable (active high)
DFS 40 1 I Data format and clock out polarity select
CLKP 10 1 I Data converter differential input clock (positive)
CLKM 11 1 I Data converter differential input clock (negative)
SEN 4 1 I Serial interface chip select
SDATA 3 1 I Serial interface data
SCLK 2 1 I Serial interface clock
D0 (LSB)−D13 (MSB) 44−47, 51−56, 60−63 14 O Parallel data output
OVR 64 1 O Over-range indicator bit
CLKOUT 43 1 O CMOS clock out in sync with data
NOTE:PowerPAD is connected to analog ground.
(1)
The DFS pin is programmable to four discrete voltage levels: 0, 3/8 AVDD, 5/8 AVDD, and AVDD. The thresholds are centered. More details are
listed in Table 3 on page 8.
5, 7, 9, 15, 22, 24, 26,
28, 33, 34, 37, 39
6, 8, 12, 13, 14, 16, 18,
21, 23, 25, 27, 32, 36, 38
49, 58 2 I Output driver power supply
1, 42, 48, 50, 57, 59 6 I Output driver ground
12 I Analog power supply
14 I Analog ground
resistor to GND
resistor to GND
DD
(1)
9
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