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4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
查询ADS5500供应商
SBAS303C − DECEMBER 2003 − REVISED MARCH 200
FEATURES
D 14-Bit Resolution
D Recommended Amplifiers:
OPA695, OPA847, THS3201, THS3202,
THS4503, THS9001
D 125MSPS Sample Rate
D High SNR: 70.5dBFS at 100MHz f
D High SFDR: 82dBc at 100MHz f
D 2.3V
Differential Input Voltage
PP
IN
IN
D Internal Voltage Reference
D 3.3V Single-Supply Voltage
D Analog Power Dissipation: 578mW
− Total Power Dissipation: 780mW
D Serial Programming Interface
D TQFP-64 PowerPADE Package
APPLICATIONS
D Wireless Communication
− Communication Receivers
− Base Station Infrastructure
D Test and Measurement Instrumentation
D Single and Multichannel Digital Receivers
D Communication Instrumentation
− Radar, Infrared
D Video and Imaging
D Medical Equipment
DESCRIPTION
The ADS5500 is a high-performance, 14-bit, 125MSPS analog-to-digital converter (ADC). To provide a complete
converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed
for applications demanding the highest speed and highest dynamic performance in very little space, the ADS5500
has excellent power consumption of 780mW at 3.3V single-supply voltage. This allows an even higher system
integration density. The provided internal reference simplifies system design requirements. Parallel CMOScompatible output ensures seamless interfacing with common logic.
The ADS5500 is available in a 64-pin TQFP PowerPAD package and is specified over the full temperature range of
−40°C to +85°C.
AV
DD
DRV
DD
CLK+
−
CLK
+
V
IN
−
V
IN
CM
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
! " #$ " %$&# '( '$#"
#! "%##" % ) !" *" "$!" "'' +,(
'$# %#"" '" #"", #$' " %!"(
S&H
Internal
Reference
A
GND
Timing Circuitry
14−Bit
Pipeline
ADC Core
Serial Programming Register
SEN SDATA
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Digital
Error
Correction
Control Logic
SCLK
Output
Control
ADS5500
DR
GND
Copyright 2003−2004, Texas Instruments Incorporated
D0
D13
.
.
.
CLKOUT
OVR
DFS
Page 2
HTQFP-64
(2)
ADS5500
HTQFP-64
(2)
PAP
−40°C to +85°C
ADS5500I
Voltage
ADCLK input sample
ADCLK input sample
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
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PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE−LEAD
PowerPAD
(1)
For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet.
(2)
Thermal pad size: 3.5mm x 3.5mm (min), 4mm x 4mm (max).
PACKAGE
DESIGNATOR
ABSOLUTE MAXIMUM RATINGS
over operat i n g f ree-air temperature range unless otherwise noted
ADS5500 UNIT
Supply
Analog input to A
Logic input to DR
Digital data output to DR
Input current (any input) 30 mA
Operating temperature range −40 to +85 °C
Junction temperature +105 °C
Storage temperature range −65 to +150 °C
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only , an d
functional operation of the device at these or any other conditions
beyond those specified is not implied.
AVDD to A
DRVDD to DR
A
to DR
GND
GND
GND
GND
GND
GND
GND
,
−0.3 to +3.7 V
±0.1 V
−0.15 to +2.5 V
−0.3 t o D RVDD + 0.3 V
−0.3 t o D RVDD + 0.3 V
(1)
SPECIFIED
TEMPERATURE
(1)
RANGE
PACKAGE
MARKING
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible t o damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING
NUMBER
ADS5500IPAP Tray, 160
ADS5500IPAPR Tape and Reel, 1000
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supplies
Analog supply voltage, AV
Output driver supply voltage, DRV
Analog Input
Differential input range 2.3 V
Input common-mode voltage, V
Digital Output
Maximum output load 10 pF
Clock Input
rate (sine wave) 1/t
Clock amplitude, sine wave,
differential
Clock duty cycle
Open free-air temperature range −40 +85 °C
(1)
(2)
(3)
(2)
(3)
Input common-mode should be connected to CM.
See Figure 13 for more information.
See Figure 12 for more information.
DD
CM
DLL ON 60 125 MSPS
DLL OFF 10 80 MSPS
C
MIN TYP MAX UNIT
3.0 3.3 3.6 V
3.0 3.3 3.6 V
DD
(1)
1.5 1.6 V
TRANSPORT
MEDIA, QUANTITY
PP
3 V
50 %
PP
2
Page 3
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fIN = 10MHz
Signal-to-noise ratio, SNR
fIN = 70MHz
fIN = 10MHz
Spurious-free dynamic range, SFDR
fIN = 70MHz
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS
Typ, min, and max values at TA = +25°C, full temperature range is T
cycle, AVDD = DRVDD = 3.3V , DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted.
= −40°C to t
MIN
= +85°C, sampling rate = 125MSPS, 50% clock duty
MAX
PARAMETER
Resolution 14 Tested Bits
Analog Inputs
Differential input range 2.3 V
Differential input impedance See Figure 4 6.6 kΩ
Differential input capacitance See Figure 4 4 pF
Total analog input common-mode current 4
Analog input bandwidth Source impedance = 50Ω 750 MHz
Conversion Characteristics
Maximum sample rate see note (2) 125 MSPS
Data latency See timing diagram, Figure 1 16.5 Clock Cycles
Internal Reference Voltages
Reference bottom voltage, V
Reference top voltage, V
Reference error −4 ±0.9 +4 %
Common-mode voltage output, V
Dynamic DC Characteristics and Accuracy
No missing codes Tested
Differential linearity error , DNL fIN = 10MHz −0.9 ±0.75 +1.1 LSB
Integral linearity error, INL fIN = 10MHz −5 ±2.5 +5 LSB
Offset error ±1.5 mV
Offset temperature coefficient 0.0007 %/°C
Gain error ±0.45 %FS
Gain temperature coefficient 0.01 ∆%/°C
Dynamic AC Characteristics
Signal-to-noise ratio, SNR
RMS Output noise Input tied to common-mode 1.1 LSB
Spurious-free dynamic range, SFDR
(1)
2mA per input.
(2)
See Reccommended Operating Conditions on page 2.
REFM
REFP
CM
fIN = 30MHz 71.5 dBFS
fIN = 55MHz 71.5 dBFS
fIN = 100MHz 70.5 dBFS
fIN = 150MHz 70.1 dBFS
fIN = 225MHz 69.1 dBFS
fIN = 30MHz 84 dBc
fIN = 55MHz 79 dBc
fIN = 100MHz 82 dBc
fIN = 150MHz 78 dBc
fIN = 225MHz 74 dBc
CONDITIONS MIN TYP MAX UNIT
PP
(1)
0.97 V
2.11 V
1.55 ± 0.05 V
Room temp 70.5 71.5 dBFS
Full temp range 69 71.5 dBFS
Room temp 70 71.2 dBFS
Full temp range 68.5 71 dBFS
Room temp 82 84 dBc
Full temp range 78 84 dBc
Room temp 80 83 dBc
Full temp range 77 82 dBc
mA
3
Page 4
fIN = 10MHz
Second-harmonic, HD2
fIN = 70MHz
fIN = 10MHz
Third-harmonic, HD3
fIN = 70MHz
Worst-harmonic/spur
Worst-harmonic/spur
fIN = 10MHz
Signal-to-noise + distortion, SINAD
fIN = 70MHz
fIN = 10MHz
Total harmonic distortion, THD
fIN = 70MHz
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (continued)
Typ, min, and max values at TA = +25°C, full temperature range is T
cycle, AVDD = DRVDD = 3.3V , DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted.
PARAMETER UNITMAXTYPMINCONDITIONS
fIN = 30MHz 86 dBc
fIN = 55MHz 84 dBc
Second-harmonic, HD2
fIN = 100MHz 84 dBc
fIN = 150MHz 78 dBc
fIN = 225MHz 74 dBc
fIN = 30MHz 90 dBc
fIN = 55MHz 79 dBc
Third-harmonic, HD3
fIN = 100MHz 82 dBc
fIN = 150MHz 80 dBc
fIN = 225MHz 76 dBc
fIN = 10MHz Room temp 88 dBc
(other than HD2 and HD3)
Signal-to-noise + distortion, SINAD
Total harmonic distortion, THD
fIN = 70MHz Room temp 86 dBc
fIN = 30MHz 70 dBc
fIN = 55MHz 69.5 dBc
fIN = 100MHz 69 dBc
fIN = 150MHz 69 dBc
fIN = 225MHz 66.4 dBc
fIN = 30MHz 82 dBc
fIN = 55MHz 77 dBc
fIN = 100MHz 79 dBc
fIN = 150MHz 75 dBc
fIN = 225MHz 71.8 dBc
= −40°C to t
MIN
Room temp 82 91 dBc
Full temp range 78 86 dBc
Room temp 80 87 dBc
Full temp range 77 83 dBc
Room temp 82 89 dBc
Full temp range 78 88 dBc
Room temp 80 85 dBc
Full temp range 77 82 dBc
Room temp 69 70 dBc
Full temp range 67.5 70 dBc
Room temp 68.5 69 dBc
Full temp range 67 69.5 dBc
Room temp 80 85 dBc
Full temp range 78 83 dBc
Room temp 77.5 81 dBc
Full temp range 76 79.5 dBc
= +85°C, sampling rate = 125MSPS, 50% clock duty
MAX
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4
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SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (continued)
Typ, min, and max values at TA = +25°C, full temperature range is T
cycle, AVDD = DRVDD = 3.3V , DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted.
PARAMETER UNITMAXTYPMINCONDITIONS
Effective number of bits, ENOB fIN = 70MHz 11.3 Bits
f = 10.1MHz, 15.1MHz
(−7dBFS each tone)
Two-tone intermodulation distortion, IMD
Power Supply
Total supply current, I
Analog supply current, I
Output buffer supply current, I
Power dissipation Total power with 10pF load on
Standby power With clocks running 181 250 mW
CC
AVDD
DRVDD
f = 30.1MHz, 35.1MHz
(−7dBFS each tone)
f = 50.1MHz, 55.1MHz
(−7dBFS each tone)
VIN = full-scale, fIN = 55MHz
AVDD = DRVDD = 3.3V
VIN = full-scale, fIN = 55MHz
AVDD = DRVDD = 3.3V
VIN = full-scale, fIN = 55MHz
AVDD = DRVDD = 3.3V
Analog only 578 627 mW
digital output to ground
= −40°C to t
MIN
= +85°C, sampling rate = 125MSPS, 50% clock duty
MAX
85 dBc
85 dBc
88 dBc
236 265 mA
175 190 mA
61 75 mA
780 875 mW
DIGITAL CHARACTERISTICS
Typ, min, and max values at TA = +25°C, full temperature range is T
cycle, AVDD = DRVDD = 3.3V , DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNIT
Digital Inputs
High-level input voltage 2.4 V
Low-level input voltage 0.8 V
High-level input current 10 µA
Low-level input current 10 µA
Input current for RESET −20 µA
Input capacitance 4 pF
Digital Outputs
Low-level output voltage C
High-level output voltage C
Output capacitance 3 pF
(1)
For optimal performance, all digital output lines (D0:D13), including the output clock, should see a similar load.
(2)
Equivalent capacitance to ground of (load + parasitics of transmission lines).
(1)
LOAD
LOAD
= 10pF
= 10pF
(2)
, fS = 125MSPS 0.3 V
(2)
, fS = 125MSPS 3.0 V
= −40°C to t
MIN
= +85°C, sampling rate = 125MSPS, 50% clock duty
MAX
5
Page 6
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
TIMING CHARACTERISTCS
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Analog
Signal
Input Clock
Output Clock
Data Out
(D0−D13)
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing
matches closely with the specified values.
Input
Sample
N
N+1
t
A
N−17 N−16 N−15 N−13 N−3N−2N−1N
N+2
N+3
16.5 Clock Cycles
N+4
N+15
N+16
N+17
t
PDI
t
SETUP
Data Invalid
Figure 1. Timing Diagram
TIMING CHARACTERISTICS
Typ, min, and max values at TA = +25°C, full temperature range is T
cycle, AVDD = DRVDD = 3.3V , DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted.
PARAMETER DESCRIPTION MIN TYP MAX UNIT
Switching Specification
Aperture delay, t
Aperture jitter (uncertainty) Uncertainty in sampling instant 300 fs
Data setup time, t
Data hold time, t
Data latency, tD(Pipe)
Propagation delay, t
Data rise time Data out 20% to 80% 2.5 ns
Data fall time Data out 80% to 20% 2.5 ns
Output enable (OE) to
output stable delay
A
SETUP
HOLD
PDI
Input CLK falling edge to data sampling point 1 ns
Data valid to 50% of CLKOUT rising edge 2 ns
CLKOUT rising edge to data becoming invalid 1.7 ns
Input clock falling edge (on which sampling
takes place) to input clock rising edge (on
which the corresponding data is given out)
Input clock rising edge to data valid 7.5 ns
= −40°C to t
MIN
= +85°C, sampling rate = 125MSPS, 50% clock duty
MAX
16.5 Clock Cycles
2 ms
t
HOLD
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The device has a three-wire serial interface. The device
latches the serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
D Serial shift of bits is enabled when SEN is low.
SCLK shifts serial data at falling edge.
D Minimum width of data stream for a valid loading is
16 clocks.
6
D Data is loaded at every 16th SCLK falling edge
while SEN is low.
D In case the word length exceeds a multiple of 16
bits, the excess bits are ignored.
D Data can be loaded in multiple of 16-bit words within
a single active SEN pulse.
Page 7
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SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
SDATA
A3
MSB
A2 A1 A0 D11 D10 D9 D0
ADDRESS
Figure 2. DATA Communication is 2-Byte, MSB First
t
SEN
SCLK
SDAT A
SLOADS
t
t
OS
MSB LSB LSBMSB
WSCLK
t
OH
t
WSCLK
Figure 3. Serial Programming Interface Timing Diagram
Table 1. Serial Programming Interface Timing Characteristics
SYMBOL PARAMETER MIN
t
SCLK
t
WSCLK
t
SLOADS
t
SLOADH
t
DS
t
DH
(1)
Min, typ, and max values are characterized, but not production tested.
SCLK Period 50 ns
SCLK Duty Cycle 25 50 75 %
SEN to SCLK setup time 8 ns
SCLK to SEN hold time 6 ns
Data Setup Time 8 ns
Data Hold Time 6 ns
t
SCLK
16 x M
(1)
DATA
TYP
(1)
t
SLOADH
MAX
(1)
UNIT
Table 2. Serial Register Table
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
1 1 0 1 0 0 0 0 0 0 0 0 0 0 DLL
1 1 1 0 0 TP<1> TP<0> 0 0 0 0 0 0 0 0 0 TP<1:0> − Test modes for output data capture
1 1 1 1 PDN 0 0 0 0 0 0 0 0 0 0 0 PDN = 0 : Normal mode of operation, PDN = 1 :
0 DLL OFF = 0 : internal DLL is on, recommended for
OFF
60−125MSPS clock speed
DLL OFF = 1 : internal DLL is off, recommended for
10−80MSPS clock speed
TP<1> = 0, TP<0> = 0 : Normal mode of operation,
TP<1> = 0
TP<0> = 1 : All output lines are pulled to ’0’, TP<1> = 1
TP<0> = 0 : All output lines are pulled to ’1’, TP<1> = 1
TP<0> = 1 : A continuous stream of ’10’ comes out on
all output lines
Device is put in power down (low current) mode
7
Page 8
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
Table 3. DATA FORMAT SELECT (DFS TABLE)
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DFS-PIN VOLTAGE (V
1
V
t
DFS
5
AVDDu V
12
2
AVDDu V
3
V
DFS
AV
6
u
DFS
7
u
DFS
12
5
u
AV
6
PIN CONFIGURATION
1
DR
GND
2
SCLK
SEN
AV
A
GND
AV
A
GND
AV
CLKP
CLKM
A
GND
A
GND
A
GND
AV
A
GND
3
4
5
DD
6
7
DD
8
9
DD
10
11
12
13
14
15
DD
16
SDATA
) DAT A FORMAT CLOCK OUTPUT POLARITY
DFS
DD
1
3
DD
AV
AV
DD
DD
Straight Binary Data valid on rising edge
Two’s Complement Data valid on rising edge
Straight Binary Data valid on falling edge
Two’s Complement Data valid on falling edge
PAP PACKAGE
(TOP VIEW)
GND
OVR
D13 (MSB)
D12
D11
D10
DR
GND
DRVDDDR
D9
D8
64 63 62 61 60 59 58 57 56 55 54
ADS5500
PowerPAD
(Connected to Analog Ground)
17 18 19 20 21 22 23 24 25 26 27
CM
GND
INP
A
INM
DD
GND
A
AV
DD
GND
A
AV
DD
GND
A
AV
D7
D6
D5
D4
53 52 51 50 49
28 29 30 31 32
DD
GND
A
AV
REFP
REFM
GND
DR
IREF
DD
DRV
GND
A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DR
GND
D3
D2
D1
D0 (LSB)
CLKOUT
DR
GND
OE
DFS
AV
DD
A
GND
AV
DD
A
GND
RESET
AV
DD
AV
DD
8
Page 9
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SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
PIN ASSIGNMENTS
TERMINAL NO.
NAME NO. OF PINS I/O DESCRIPTION
AV
DD
A
GND
DRV
DD
DR
GND
INP 19 1 I Differential analog input (positive)
INM 20 1 I Differential analog input (negative)
REFP 29 1 O Reference voltage (positive); 0.1µF capacitor in series with a 1Ω
REFM 30 1 O Reference voltage (negative); 0.1µF capacitor in series with a 1Ω
IREF 31 1 I Current set; 56kΩ resistor to GND; do not connect capacitors
CM 17 1 O Common-mode output voltage
RESET 35 1 I Reset (active high), 200kΩ resistor to AV
OE 41 1 I Output enable (active high)
DFS 40 1 I Data format and clock out polarity select
CLKP 10 1 I Data converter differential input clock (positive)
CLKM 11 1 I Data converter differential input clock (negative)
SEN 4 1 I Serial interface chip select
SDATA 3 1 I Serial interface data
SCLK 2 1 I Serial interface clock
D0 (LSB)−D13 (MSB) 44−47, 51−56, 60−63 14 O Parallel data output
OVR 64 1 O Over-range indicator bit
CLKOUT 43 1 O CMOS clock out in sync with data
NOTE:PowerPAD is connected to analog ground.
(1)
The DFS pin is programmable to four discrete voltage levels: 0, 3/8 AVDD, 5/8 AVDD, and AVDD. The thresholds are centered. More details are
listed in Table 3 on page 8.
5, 7, 9, 15, 22, 24, 26,
28, 33, 34, 37, 39
6, 8, 12, 13, 14, 16, 18,
21, 23, 25, 27, 32, 36, 38
49, 58 2 I Output driver power supply
1, 42, 48, 50, 57, 59 6 I Output driver ground
12 I Analog power supply
14 I Analog ground
resistor to GND
resistor to GND
DD
(1)
9
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SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of
the fundamental frequency (as determined by FFT
analysis) is reduced by 3dB.
Aperture Delay
The delay in time between the falling edge of the input
sampling clock and the actual time at which the sampling
occurs.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
A perfect differential sine wave clock results in a 50% clock
duty cycle on the internal coversion clock. Pulse width high
is the minimum amount of time that the ENCODE pulse
should be left in logic ‘1’ state to achieve rated
performance. Pulse width low is the minimum time that the
ENCODE pulse should be left in a low state (logic ‘0’). At
a given clock rate, these specifications define an
acceptable clock duty cycle.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1
LSB apart. DNL is the deviation of any single LSB
transition at the digital output from an ideal 1 LSB step at
the analog input. If a device claims to have no missing
codes, it means that all possible codes (for a 14-bit
converter, 16384 codes) are present over the full operating
range.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its
measured SINAD using the following formula:
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Integral Nonlinearity (INL)
INL is the deviation of the transfer function from a
reference line measured in fractions of 1 LSB using a “best
straight line” or “best fit” determined by a least square
curve fit. INL is independent from effects of offset, gain or
quantization errors.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
This is the maximum sampling rate where certified
operation is given.
Minimum Conversion Rate
This is the minimum sampling rate where the ADC still
works.
Nyquist Sampling
When the sampled frequencies of the analog input signal
are below f
Nyquist frequency is f
on the sample rate (f
/2, it is called Nyquist sampling. The
CLOCK
/2, which can vary depending
CLOCK
).
CLOCK
Offset Error
Offset error is the deviation of output code from
mid-code when both inputs are tied to common-mode.
Propagation Delay
This is the delay between the input clock rising edge and
the time when all data bits are within valid logic levels.
Signal-to-Noise and Distortion (SINAD)
The RMS value of the sine wave f
(input sine wave for an
IN
ADC) to the RMS value of the noise of the converter from
DC to the Nyquist frequency, including harmonic content.
It is typically expressed in decibels (dB). SINAD includes
harmonics, but excludes DC.
ENOB +
SINAD* 1.76
6.02
If SINAD is not known, SNR can be used exceptionally to
calculate ENOB (ENOB
SNR
).
Effective Resolution Bandwidth
The highest input frequency where the SNR (dB) is
dropped by 3dB for a full-scale input amplitude.
Gain Error
The amount of deviation between the ideal transfer
function and the measured transfer function (with the offset
error removed) when a full-scale analog input voltage is
applied to the ADC, resulting in all 1s in the digital code.
Gain error is usually given in LSB or as a percent of
full-scale range (%FSR).
10
SINAD + 20Log
(10)
Input(VS)
Noise ) Harmonics
Signal-to-Noise Ratio (without harmonics)
SNR is a measure of signal strength relative to background
noise. The ratio is usually measured in dB. If the incoming
signal strength in µV is V
, then the SNR in dB is given by the formula:
is V
N
SNR + 20Log
, and the noise level (also in µV)
S
V
S
(10)
V
N
This is the ratio of the RMS signal amplitude, VS (set 1dB
below full-scale), to the RMS value of the sum of all other
spectral components, V
, excluding harmonics and DC.
N
Page 11
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SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
Spurious-Free Dynamic Range (SFDR)
The ratio of the RMS value of the analog input sine wave
to the RMS value of the peak spur observed in the
frequency domain. It may be reported in dBc (that is, it
degrades as signal levels are lowered), or in dBFS (always
related back to converter full-scale). The peak spurious
component may or may not be a harmonic.
Temperature Drift
Temperature drift (for offset error and gain error) specifies
the maximum change from the initial temperature value to
the value at T
MIN
or T
MAX
.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS signal amplitude of the input
sine wave to the RMS value of distortion appearing at
multiples (harmonics) of the input, typically given in dBc.
Two-Tone Intermodulation Distortion Rejection
The ratio of the RMS value of either input tone (f
, f2) to the
1
RMS value of the worst third-order intermodulation
product (2f
− f2; 2f2 − f1). It is reported in dBc.
1
11
Page 12
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SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V , differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless
otherwise noted.
SPECTRAL PERFORMANCE
0
−
10
−
20
−
30
−
40
−
50
−
60
−
70
−
80
−
90
Amplitude (dB)
−
100
−
110
−
120
−
130
−
140
0102030405060
0
−
10
SFDR = 81.0dBc
−
20
SNR = 71.2dBFS
−
30
THD = 80.2dBc
−
40
SINAD = 70.7dBFS
−
50
−
60
−
70
−
80
−
90
Amplitude (dB)
−
100
−
110
−
120
−
130
−
140
0 102030405060
(FFTfor 2MHz InputSignal)
SFDR = 84.0dBc
SNR = 71.2dBFS
THD = 84.0dBc
SINAD = 71.0dBFS
Frequency (MHz)
SPECTRAL PERFORMANCE
(FFTfor 60MHz InputSignal)
Frequency (MHz)
SPECTRAL PERFORMANCE
0
−
10
−
20
−
30
−
40
−
50
−
60
−
70
−
80
−
90
Amplitude (dB)
−
100
−
110
−
120
−
130
−
62.5
62.5
140
0102030405060
0
−
10
SFDR = 85.1dBc
−
SNR = 71.4dBFS
20
−
30
THD =83.6dBc
−
SINAD= 71.1dBFS
40
−
50
−
60
−
70
−
80
−
90
Amplitude (dB)
−
100
−
110
−
120
−
130
−
140
0102030405060
(FFT for 15MHz Input Signal)
SFDR = 84.8dBc
SNR = 71.5dBFS
THD = 83.2dBc
SINAD = 71.2dBFS
62.5
Frequency (MHz)
SPECTRAL PERFORMANCE
(FFT for 70MHz Input Signal)
62.5
Frequency (MHz)
12
SPECTRAL PERFORMANCE
0
−
10
SFDR = 84.4dBc
−
20
SNR = 71.2dBFS
−
30
THD = 81.3dBc
−
40
SINAD = 70.9dBFS
−
50
−
60
−
70
−
80
−
90
Amplitude (dB)
−
100
−
110
−
120
−
130
−
140
0102030405060
(FFTfor 80MHz InputSignal)
Frequency (MHz)
SPECTRAL PERFORMANCE
0
−
SFDR = 84.3dBc
10
−
SNR = 71.1dBFS
20
−
THD = 81.6dBc
30
−
SINAD = 70.7dBFS
40
−
50
−
60
−
70
−
80
−
90
Amplitude (dB)
−
100
−
110
−
120
−
130
−
62.5
140
0102030405060
(FFT for100MHzInputSignal)
62.5
Frequency (MHz)
Page 13
www.ti.com
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V , differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless
otherwise noted.
SPECTRAL PERFORMANCE
0
−
10
SFDR = 77.8dBc
−
20
SNR = 70.0dBFS
−
30
THD = 75.3dBc
−
40
SINAD = 69.0dBFS
−
50
−
60
−
70
−
80
−
90
Amplitude (dB)
−
100
−
110
−
120
−
130
−
140
0102030405060
0
−
10
SFDR = 67.4dBc
−
SNR = 68.0dBFS
20
−
30
THD = 64.7dBc
−
SINAD = 63.0dBFS
40
−
50
−
60
−
70
−
80
−
90
Amplitude (dB)
−
100
−
110
−
120
−
130
−
140
0102030405060
(FFT for150MHzInputSignal)
Frequency (MHz)
SPECTRAL PERFORMANCE
(FFT for300MHzInputSignal)
Frequency (MHz)
SPECTRAL PERFORMANCE
0
−
10
SFDR = 73.0dBc
−
20
SNR = 69.1dBFS
−
30
THD = 70.0dBc
−
40
SINAD= 66.5dBFS
−
50
−
60
−
70
−
80
−
90
Amplitude (dB)
−
100
−
110
−
120
−
130
−
62.5
62.5
140
0102030405060
0
−
20
−
40
−
60
−
80
Power (dBFS)
−
100
−
120
−
140
02010 30 5040 60
(FFT for225MHzInputSignal)
Frequency (MHz)
TWO−TONE INTERMODULATION
f1= 10.1MHz,−7dBFS
= 15.1MHz,−7dBFS
f
2
2−tone IMD = 88.0dBc
Frequency (MHz)
62.5
62.5
0
f1= 30.1MHz,−7dBFS
−
20
f
2
2−tone IMD = 87.0dBc
−
40
−
60
−
80
Power (dBFS)
−
100
−
120
−
140
02010 30 5040 60
TWO−TONE INTERMODULATION
= 35.1MHz,−7dBFS
Frequency (MHz)
0
f1= 50.1MHz,−7dBFS
−
20
f
2
2−tone IMD = 89.0dBc
−
40
−
60
−
80
Power(dBFS)
−
100
−
120
−
62.5
140
0102030405060
TWO−TONE INTERMODULATION
= 55.1MHz,−7dBFS
62.5
Frequency (MHz)
13
Page 14
www.ti.com
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V , differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless
otherwise noted.
1.50
DIFFERENTIAL NONLINEARITY (DNL)
1.25
1.00
0.75
0.50
0.25
0
LSB
−
0.25
−
0.50
−
0.75
−
1.00
−
1.25
−
1.50
0
2048
4096
6144
8192
10240
Code
SPURIOUS−FREE DYNAMIC RANGE vs
INPUT FREQUENCY
90
85
80
75
70
65
SFDR(dBc)
60
fS= 125MSPS
55
DLL On
50
0 50 100 150 200 250 300
Input Frequency (MHz)
fS= 125MSPS
=10MHz
f
IN
=−0.5dBFS
A
IN
12288
14336
16384
3.5
INTEGRAL NONLINEARITY (INL)
3.0
2.5
2.0
1.5
1.0
0.5
0
LSB
−
0.5
−
1.0
−
1.5
−
2.0
−
2.5
−
3.0
−
3.5
−
4.0
0
2048
4096
6144
8192
fS= 125MSPS
f
IN
A
10240
Code
SIGNAL−TO−NOISE RATIO vs INPUT FREQUENCY
76
74
72
70
68
66
SNR (dBFS)
64
fS= 125MSPS
62
DLL On
60
0 50 100 150 200 250 300
Input Frequency (MHz)
= 10MHz
=−0.5dBFS
IN
12288
14336
16384
14
AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE
90
85
80
SFDR
75
SFDR (dBc)
SNR (dBFS)
70
fS=125MSPS
65
= 150MHz
f
IN
=3.3V
DRV
DD
SNR
60
3.0 3.1 3.2 3.3 3.4 3.5 3.6
AVDD(V)
AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE
90
85
SFDR
80
75
SNR
SFDR (dBc)
SNR (dBFS)
70
fS=125MSPS
65
=70MHz
f
IN
=3.3V
DRV
DD
60
3.0 3.1 3.2 3.3 3.4 3.5 3.6
AVDD(V)
Page 15
www.ti.com
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V , differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless
otherwise noted.
AC PERFORMANCE vs DIGITALSUPPLYVOLTAGE
79
78
77
76
fS= 125MSPS
75
= 150MHz
f
IN
74
73
SFDR (dBc)
SNR (dBFS)
72
71
70
69
850
800
750
700
650
600
Power Dissipation(mW)
550
=3.3V
AV
DD
3.0 3.1 3.2 3.3 3.4 3.5 3.6
POWER DISSIPATION vs SAMPLE RATE
AVDD=DRVDD=3.3V
= 150MHz
f
IN
SFDR
SNR
DRVDD(V)
AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE
84
82
80
fS= 125MSPS
78
76
SFDR (dBc)
SNR (dBFS)
74
72
70
800
750
700
650
600
Power Dissipation (mW)
550
=70MHz
f
IN
=3.3V
AV
DD
3.03.13.23.33.43.53.6
POWER DISSIPATION vs SAMPLING FREQUENCY
fIN=70MHz
DLL Off
SFDR
SNR
DRVDD(V)
DLL On
500
10 30 50 70 90 110 130 150
Sample Rate (MSPS)
SPURIOUS−FREE DYNAMIC RANGE vs TEMPERATURE
90
85
80
75
SFDR (dBc)
SNR (dBFS)
70
fS= 125MSPS
65
f
IN
DLL On
60
−
40 0 25 40 85
SIGNAL−TO−NOISE RATIOAND
SFDR
SNR
= 70MHz
Temperature (_C)
500
10 20 30 40 50 60 70 80 90 100 110 120
SamplingFrequency (MSPS)
90
80
70
60
50
40
30
20
10
AC Performance (dB)
0
−
10
−
20
−
30
−
AC PERFORMANCE vs INPUT AMPLITUDE
SNR (dBFS)
SFDR (dBc)
SNR (dBc)
fS= 125MSPS
=70MHz
f
IN
DLL On
100−90−80−70−60−50−40−30−20−10 0
Input Amplitude (dBFS)
125
15
Page 16
www.ti.com
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V , differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless
otherwise noted.
90
80
70
60
50
40
30
20
10
AC Performance (dB)
0
−
10
−
20
−
30
−
40
35
30
25
20
15
Occurrence(%)
10
5
0
AC PERFORMANCE vs INPUT AMPLITUDE
SNR (dBFS)
SFDR (dBc)
SNR (dBc)
f
=125MSPS
S
=150MHz
f
IN
DLL On
100−90−80−70−60−50−40−30−20−10 0
Input Amplitude (dBFS)
OUTPUT NOISEHISTOGRAM
8211
8209
8210
8212
8213
8214
8215
8216
8217
8218
8219
Output Code
90
80
70
60
50
40
30
20
10
AC Performance (dB)
0
−
10
−
20
−
30
90
85
80
75
70
65
SFDR (dBc)
SNR (dBFS)
60
55
50
8220
8221
8222
AC PERFORMANCE vs INPUT AMPLITUDE
SNR (dBFS)
SFDR(dBc)
SNR (dBc)
= 125MSPS
f
S
= 220MHz
f
IN
DLL On
−90−80−70−60−50−40−30−20−
Input Amplitude (dBFS)
AC PERFORMANCE vs CLOCK AMPLITUDE
SFDR
SNR
0 0.5 1.0 1.5 2.0 2.5 3.0
Differential Clock Amplitude (V)
10 0
fS= 125MSPS
= 70MHz
f
IN
16
0
fS= 150MSPS
−
20
= 125MHz
f
IN
−
40
−
60
−
80
Amplitude (dB)
−
100
−
120
−
140
0 102030405060
WCDMA TONE
Frequency (MHz)
Page 17
www.ti.com
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V , differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless
otherwise noted.
150
SIGNAL−TO−NOISE RATIO (SNR) WITH DLL ON
73
71
140
71
130
120
110
71
72
69
69
70
100
90
80
Sample Frequency (MSPS)
73
70
60
73
72
71
70
72
70
69
69
68
68
69
50
40
72
500 100 150 200 250 300
71
Input Frequency (MHz)
69
68
67
72
71
70
SNR (dB)
69
68
67
66
Sample Frequency (MSPS)
80
SIGNAL−TO−NOISE RATIO (SNR) WITH DLL O FF
71
73
70
73
60
50
40
72
71
72
70
69
70
73
30
73
69
68
67
70
20
71
72
10
500 100 150 200 250 300
71
69
68
Input Frequency (MHz)
67
66
68
65
69
63
62
66
64
67
72
70
68
66
64
62
60
SNR (dB)
17
Page 18
www.ti.com
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V , differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless
otherwise noted.
SPURIOUS−FREE DYNAMIC RANGE (SFDR) WITH DLL ON
150
83
140
130
80
77
80
71
68
85
120
110
100
86
90
80
Sample Frequency (MSPS)
70
60
50
40
89
89
83
83
77
77
74
86
83
86
80
71
68
74
83
86
83
86
500 100 150 200 250 300
Input Frequency (MHz)
77
83
80
77
74
71
68
80
75
70
65
SFDR (dBc)
SPURIOUS−FREE DYNAMIC RANGE (SFDR) WITH DLL OFF
80
70
60
50
88
88
86
84
86
88
86
84
80
82
80
78
78
76
74
72
70
70
68
88
86
84
82
80
78
18
40
Sample Frequency (MSPS)
30
86
84
88
20
10
86
82
76
74
72
82
80
78
76
Input Frequency (MHz)
74
72
70
86
84
500 100 150 200 250 300
70
68
76
SFDR (dBc)
74
72
70
68
66
Page 19
www.ti.com
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V , differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless
otherwise noted.
150
140
130
120
110
100
90
80
Sample Frequency (MSPS)
70
60
50
40
95
98
98
98
92
89
95
95
86
92
83
86
89
86
92
89
86
86
86
92
92
89
95
92
89
86
83
80
83
86
89
89
89
92
98
83
89
86
83
86
92
92
95
500 100 150 200 250 300
95
98
Input Frequency (MHz)
89
86
77
80
80
77
83
77
77
74
74
74
80
71
77
71
74
71
68
68
71
68
95
90
85
80
HD2 (dBc)
75
70
65
SECOND HARMONIC (HD2) WITH DLL ON
80
93
70
60
50
40
Sample Frequency (MSPS)
30
99
99
96
99
99
99
96
93
20
87
84
10
500 100 150 200 250 300
90
93
96
99
93
90
87
84
81
78
75
Input Frequency (MHz)
87
87
84
84
81
72
81
78
78
75
75
72
72
68
68
68
95
90
85
HD2 (dBc)
80
75
70
SECOND HARMONIC (HD2) WITH DLL OFF
19
Page 20
www.ti.com
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V , differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless
otherwise noted.
THIRDHARMONIC(HD3)WITHDLLON
150
140
130
120
110
100
90
80
70
60
50
40
86
86
92
89
83
89
80
77
89
74
71
86
86
83
86
83
80
77
77
74
77
80
86
89
83
86
83
89
86
86
86
86
83
500 100 150 200 250 300
Input Frequency (MHz)
83
89
92
68
71
90
85
80
HD3 (dBc)
75
70
65
THIRD HARMONIC (HD3) WITH DLL OFF
80
90
70
84
87
90
87
84
81
78
78
60
87
84
72
75
50
40
Sample Frequency (MSPS)
30
84
20
10
87
90
81
87
500 100 150 200 250 300
84
87
84
81
78
81
78
84
Input Frequency (MHz)
75
72
75
72
72
90
85
80
HD3(dBc)
75
70
20
Page 21
www.ti.com
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5500 is a low-power, 14-bit, 125MSPS,
CMOS, switched capacitor, pipeline ADC that operates
from a single 3.3V supply. The conversion process is
initiated by a falling edge of the external input clock.
Once the signal is captured by the input S&H, the input
sample is sequentially converted by a series of small
resolution stages, with the outputs combined in a digital
correction logic block. Both the rising and the falling
clock edges are used to propagate the sample through
the pipeline every half clock cycle. This process results
SAMPLE
PHASE
W
SWITCH
SAMPLE
PHASE
Ω
1a
W
1b
Ω
Ω
INP
INM
L
1
CP
L
2
CP
L1,L2: 6nh to 10nh effective
:25Ωto 35
R
1a,R1b
C
: 2.2pF to 2.6pF
1a,C1b
,CP2: 2.5pFto 3.5pF
CP
1
,CP4, : 1.2pF to 1.8pF
CP
3
: 0.8pFto 1.2pF
C
ACROSS
:80Ωto 120
R
3
Switches:
All switches are on in sample phase.
Approximately half of every clock period is a sample phase.
Ω
Ω
W
W
W
W
: On Resistance: 25Ωto 35
1a,W1b
: On Resistance: 7.5Ωto 15
2
: On Resistance: 40Ωto 60
3a,W3b
1a,W1b,W2,W3a,W3b
R
1a
1 CP
C
ACROSS
R
1b
2
: Off Resistance: 1e10
in a data latency of 16.5 clock cycles, after which the
output data is available as a 14-bit parallel word, coded
in either straight offset binary or binary two’s
complement format.
INPUT CONFIGURATION
The analog input for the ADS5500 consists of a
differential sample-and-hold architecture implemented
using a switched capacitor technique, shown in
Figure 4.
SAMPLE
C
SAMPLE
PHASE
C
SAMPLE
PHASE
1a
W
2
1b
PHASE
W
3a
W
3a
SWITCH
3
R
3
SWITCH
CP
4
SWITCH
VINCM
1V
Figure 4. Analog Input Stage
21
Page 22
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
www.ti.com
This differential input topology produces a high level of
AC performance for high sampling rates. It also results
in a very high usable input bandwidth, especially
important for high intermediate-frequency (IF) or
undersampling applications. The ADS5500 requires
each of the analog inputs (INP, INM) to be externally
biased around the common-mode level of the internal
circuitry (CM, pin 17). For a full-scale differential input,
each of the differential lines of the input signal (pins 19
and 20) swings symmetrically between CM + 0.575V
and CM – 0.575V. This means that each input is driven
with a signal of up to CM ± 0.575V, so that each input
has a maximum differential signal of 1.15V
for a total
PP
differential input signal swing of 2.3VPP. The maximum
swing is determined by the two reference voltages, the
top reference (REFP, pin 29), and the bottom reference
(REFM, pin 30).
The ADS5500 obtains optimum performance when the
analog inputs are driven dif ferentially. The circuit shown
in Figure 5 shows one possible configuration using an
RF transformer.
R
50
AC Signal
Source
Z
0
Ω
50
0
Ω
1:1
ADT1−1WT
1nF
INP
R
50
ADS5500
Ω
INM
CM
Ω
10
0.1µF
Figure 5. Transformer Input to Convert
Single-Ended Signal to Differential Signal
The single-ended signal is fed to the primary winding of
an RF transformer. Since the input signal must be
biased around the common-mode voltage of the
internal circuitry, the common-mode voltage (VCM) from
the ADS5500 is connected to the center-tap of the
secondary winding. To ensure a steady low-noise V
CM
reference, best performance is obtained when the CM
(pin 17) output is filtered to ground with 0.1µF and
0.01µF low-inductance capacitors.
Output VCM (pin 17) is designed to directly drive the
ADC input. When providing a custom CM level, be
aware that the input structure of the ADC sinks a
common-mode current in the order of 4mA (2mA per
input). Equation (1) describes the dependency of the
common-mode current and the sampling frequency:
4mA f
125MSPS
s
(1)
Where:
fS > 60MSPS.
This equation helps to design the output capability and
impedance of the driving circuit accordingly.
When it is necessary to buffer or apply a gain to the
incoming analog signal, it is possible to combine
single-ended operational amplifiers with an RF
transformer, or to use a differential input/output
amplifier without a transformer, to drive the input of the
ADS5500. TI offers a wide selection of single-ended
operational amplifiers (including the THS3201,
THS3202, OPA847, and OPA695) that can be selected
depending on the application. An RF gain block
amplifier, such as TI’s THS9001, can also be used with
an RF transformer for very high input frequency
applications. The THS4503 is a recommended
differential input/output amplifier. Table 4 lists the
recommended amplifiers.
When using single-ended operational amplifiers (such
as the THS3201, THS3202, OPA847, or OPA695) to
provide gain, a three-amplifier circuit is recommended
with one amplifier driving the primary of an RF
transformer and one amplifier in each of the legs of the
secondary driving the two differential inputs of the
ADS5500. These three amplifier circuits minimize
even-order harmonics. For very high frequency inputs,
an RF gain block amplifier can be used to drive a
transformer primary; in this case, the transformer
secondary connections can drive the input of the
ADS5500 directly, as shown in Figure 5, or with the
addition of the filter circuit shown in Figure 6.
Figure 6 illustrates how R
and CIN can be placed to
IN
isolate the signal source from the switching inputs of the
ADC and to implement a low-pass RC filter to limit the
input noise in the ADC. It is recommended that these
components be included in the ADS5500 circuit layout
when any of the amplifier circuits discussed previously
are used. The components allow fine-tuning of the
circuit performance. Any mismatch between the
differential lines of the ADS5500 input produces a
degradation in performance at high input frequencies,
mainly characterized by an increase in the even-order
harmonics. In this case, special care should be taken to
keep as much electrical symmetry as possible between
both inputs.
Another possible configuration for lower-frequency signals is the use of differential input/output amplifiers that
can simplify the driver circuit for applications requiring
DC coupling of the input. Flexible in their configurations
(see Figure 7), such amplifiers can be used for singleended-to-differential conversion, signal amplification.
22
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10MHz to 120MHz
www.ti.com
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
Table 4. Recommended Amplifiers to Drive the Input of the ADS5500
INPUT SIGNAL FREQUENCY RECOMMENDED AMPLIFIER TYPE OF AMPLIFIER USE WITH TRANSFORMER?
DC to 20MHz THS4503 Differential In/Out Amp No
DC to 50MHz OPA847 Operational Amp Yes
OPA695 Operational Amp Yes
10MHz to 120MHz
Over 100MHz THS9001 RF Gain Block Yes
−
+5V
5V
V
IN
OPA695
R
400
R
2
Ω
57.5
1
Ω
AV=8V/V
(18dB)
THS3201 Operational Amp Yes
THS3202 Operational Amp Yes
R
100
S
Ω
0.1µF
1:1
1000pF
R
100
R
IN
INP
T
R
IN
Ω
C
IN
INM
ADS5500
CM
Ω
10
0.1µF
Figure 6. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
THS4503
5V
R
10µF
R
F
0.1µF
R
IN
R
IN
0.1µF10µF
F
+3.3V
INP
ADS5500
14−Bit/125MSPS
INM
CM
Ω
10
0.1µF
R
S
R
G
R
T
+5V
V
OCM
1µF
R
G
−
Figure 7. Using the THS4503 with the ADS5500
23
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SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
www.ti.com
POWER SUPPLY SEQUENCE
The ADS5500 requires a power-up sequence where the
DRVDD supply must be at least 0.4V by the time the
AVDD supply reaches 3.0V. Powering up both supplies
at the same time will work without any problem. If this
sequence is not followed, the device may stay in
power-down mode.
POWER DOWN
The device will enter power-down in one of two ways:
either by reducing the clock speed to between DC and
1MHz, or by setting a bit through the serial
programming interface. Using the reduced clock speed,
the power-down may be initiated for clock frequencies
below 10MHz. For clock frequencies between 1MHz
and 10Mhz, this can vary from device to device, but will
power-down for clock speeds below 1MHz.
The device can be powered down by programming the
internal register (see Serial Programming Interface
section). The outputs become tri-stated and only the
internal reference is powered up to shorten the
power-up time. The Power-Down mode reduces power
dissipation to a minimum of 180mW.
CLOCK INPUT
The ADS5500 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between both
configurations. The common-mode voltage of the clock
inputs is set internally to CM (pin 17) using internal 5kΩ
resistors that connect CLKP (pin 10) and CLKM (pin 11)
to CM (pin 17), as shown in Figure 9.
CM CM
Ω
5k
6pF
Ω
5k
CLKMCLKP
3pF3pF
REFERENCE CIRCUIT
The ADS5500 has built-in internal reference
generation, requiring no external circuitry on the printed
circuit board (PCB). For optimum performance, it is best
to connect both REFP and REFM to ground with a 1µF
decoupling capacitor in series with a 1Ω resistor, as
shown in Figure 8. In addition, an external 56.2kΩ
resistor should be connected from IREF (pin 31) to
AGND to set the proper current for the operation of the
ADC, as shown in Figure 8. No capacitor should be
connected between pin 31 and ground; only the 56.2kΩ
resistor should be used.
Ω
1µF
1µF
56k
1
Ω
1
Ω
REFP
29
REFM
30
31
IREF
Figure 9. Clock Inputs
When driven with a single-ended CMOS clock input, it
is best to connect CLKM (pin 11) to ground with a
0.01µF capacitor, while CLKP is AC-coupled with a
0.01µF capacitor to the clock source, as shown in
Figure 10.
Square Wave
or Sine Wave
(3V
0.01µF
)
PP
CLKP
ADS5500
CLKM
0.01µF
Figure 10. AC-Coupled, Single-Ended Clock Input
The ADS5500 clock input can also be driven
differentially, reducing susceptibility to common-mode
noise. In this case, it is best to connect both clock inputs
to the differential input clock signal with 0.01µF
capacitors, as shown in Figure 11.
Figure 8. REFP, REFM, and IREF Connections for
Optimum Performance
24
Page 25
www.ti.com
Differential Square Wave
or Sine Wave
(3V
SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
amplitudes without exceeding the supply rails and
0.01µF
CLKP
)
0.01µF
PP
ADS5500
CLKM
absolute maximum ratings of the ADC clock input.
Figure 13 shows the performance variation of the
device versus input clock amplitude. For detailed
clocking schemes based on transformer or PECL-level
clocks, refer to the ADS5500EVM User’s Guide
(SLWU010), available for download from www.ti.com.
Figure 11. AC-Coupled, Differential Clock Input
For high input frequency sampling, it is recommended
to use a clock source with very low jitter. Additionally,
the internal ADC core uses both edges of the clock for
the conversion process. This means that, ideally, a 5 0 %
duty cycle should be provided. Figure 12 shows the
performance variation of the ADC versus clock duty
cycle.
90
fS=125MSPS
=20MHz
f
IN
85
80
75
SFDR (dBc)
SNR (dBFS)
70
65
60
30 35 40 45 50 55 60 65 70
SFDR
SNR
Clock Duty Cycle (%)
Figure 12. AC Performance vs Clock Duty Cycle
Bandpass filtering of the source can help produce a
50% duty cycle clock and reduce the effect of jitter.
When using a sinusoidal clock, the clock jitter will further
improve as the amplitude is increased. In that sense,
using a differential clock allows for the use of larger
90
85
80
75
70
65
SFDR (dBc)
SNR (dBFS)
60
55
50
AC PERFORMANCE vs CLOCK AMPLITUDE
SFDR
SNR
fS=125MSPS
=70MHz
f
IN
0 0.5 1.0 1.5 2.0 2.5 3.0
Differential Clock Amplitude (V)
Figure 13. AC Performance vs Clock Amplitude
INTERNAL DLL
In order to obtain the fastest sampling rates achievable
with the ADS5500, the device uses an internal digital
phase lock loop (DLL). Nevertheless, the limited
frequency range of operation of DLL degrades the
performance at clock frequencies below 60MSPS. In
order to operate the device below 60MSPS, the internal
DLL must be shut off using the DLL OFF mode
described in th e Serial Interface Programming section.
The Typical Performance Curves show the
performance obtained in both modes of operation: DLL
ON (default), and DLL OFF. In either of the two modes,
the device will enter power down mode if no clock or
slow clock is provided. The limit of the clock frequency
where the device will function properly is ensured to be
over 10MHz.
25
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SBAS303C − DECEMBER 2003 − REVISED MARCH 2004
www.ti.com
OUTPUT INFORMATION
The ADC provides 14 data outputs (D13 to D0, with D13
being the MSB and D0 the LSB), a data-ready signal
(CLKOUT, pin 43), and an out-of-range indicator (OVR,
pin 64) that equals 1 when the output reaches the
full-scale limits.
Two different output formats (straight offset binary or
two’s complement) and two different output clock
polarities (latching output data on rising or falling edge
of the output clock) can be selected by setting DFS
(pin 40) to one of four different voltages. Table 3 details
the four modes. In addition, output enable control (OE,
pin 41, active high) is provided to tri-state the outputs.
The output circuitry of the ADS5500 has being designed
to minimize the noise produced by the transients of the
data switching, and in particular its coupling to the ADC
analog circuitry. Output D4 (pin 51) senses the load
capacitance and adjusts the drive capability of all the
output pins of the ADC to maintain the same output slew
rate described in the timing diagram of Figure 1, as long
as all outputs (including CLKOUT) have a similar load
as the one at D4 (pin 51). This circuit also reduces the
sensitivity of the output timing versus supply voltage or
temperature. External series resistors with the output
are not necessary.
SERIAL PROGRAMMING INTERFACE
The ADS5500 has internal registers for the
programming of some of the modes described in the
previous sections. The registers should be reset after
power-up by applying a 2µs (minimum) high pulse on
RESET (pin 35); this also resets the entire ADC and
sets the data outputs to low. This pin has a 200kΩ
internal pull-up resistor to AVDD. The programming is
done through a three-wire interface. The timing diagram
and serial register setting in the Serial Programing
Interface section describe the programming of this
register.
Table 2 shows the different modes and the bit values to
be written on the register to enable them.
Note that some of these modes may modify the
standard operation of the device and possibly vary the
performance with respect to the typical data shown in
this data sheet.
26
Page 27
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2004
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
ADS5500IPAP ACTIVE HTQFP PAP 64 160 None CU NIPDAU Level-3-235C-168 HR
ADS5500IPAPR ACTIVE HTQFP PAP 64 1000 None CU NIPDAU Level-3-235C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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