BURR-BROWN ADS1281 User Manual

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ADS1281

4th-Order

Modulator

Programmable

DigitalFilter

Serial

Interface

Calibration

Control

AINP

CLK

AVDD

AVSS

DVDD

DGND

AINN

Over-Range

ModulatorOutput

ADS1281

DOUT DIN

DRDY

SCLK

SYNC RESET PWDN

VREFN VREFP

SBAS378A – SEPTEMBER 2007 – REVISED NOVEMBER 2007

High-Resolution Analog-to-Digital Converter

FEATURES DESCRIPTION

• High Resolution:

– 130dB SNR (250SPS) – 127dB SNR (500SPS)

• High Accuracy: – THD: – 122dB (typ), – 115dB (max) for improvements in high-density applications. – INL: 0.6ppm

• Inherently Stable Modulator with Fast Responding Over-Range Detection

• Flexible Digital Filter: – Sinc + FIR + IIR (Selectable) – Linear or Minimum Phase Response – Programmable High-Pass Filter – Selectable FIR Data Rates:

– 250SPS to 4kSPS

• Filter Bypass Option

• Low Power Consumption:

– Operating: 12mW – Shutdown: 10 µ W

• Calibration Engine for Offset and Gain Correction

• Synchronization Input

• Analog Supply:

– Unipolar (+5V) or Bipolar ( ± 2.5V)

• Digital Supply: 1.8V to 3.3V

APPLICATIONS

• Energy Exploration

• Seismic Monitoring

• High-Accuracy Instrumentation

The ADS1281 is an extremely high-performance, single-chip analog-to-digital converter (ADC) designed for the demanding needs of energy exploration and seismic monitoring environments. The single-chip design promotes board area savings

The converter uses a fourth-order, inherently stable, delta-sigma ( Δ Σ ) modulator that provides outstanding noise and linearity performance. The modulator is used either in conjunction with the on-chip digital filter, or can be bypassed for use with post-processing filters.

The digital filter consists of sinc and finite impulse response (FIR) low-pass stages followed by an infinite impulse response (IIR) high-pass filter (HPF) stage. Selectable decimation provides data rates from 250 to 4000 samples per second (SPS). The FIR low-pass stage provides both linear and minimum phase response. The HPF features an adjustable corner frequency. On-chip gain and offset scaling registers support system calibration.

The synchronization input (SYNC) can be used to synchronize the conversions of multiple ADS1281s. The SYNC input also accepts a clock input for continuous alignment of conversions from an external source.

Together, the modulator and filter dissipate only 12mW. The ADS1281 is available in a compact TSSOP-24 package and is fully specified from – 40 ° C to +85 ° C, with a maximum operating range to +125 ° C.

ADS1281

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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ADS1281

SBAS378A – SEPTEMBER 2007 – REVISED NOVEMBER 2007

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com .

ABSOLUTE MAXIMUM RATINGS

(1)

Over operating free-air temperature range, unless otherwise noted.

ADS1281 UNIT

AVDD to AVSS – 0.3 to +5.5 V AVSS to DGND – 2.8 to +0.3 V DVDD to DGND – 0.3 to +3.9 V Input current 100, momentary mA Input current 10, continuous mA Analog input voltage AVSS – 0.3 to AVDD + 0.3 V Digital input voltage to DGND – 0.3 to DVDD + 0.3 V Maximum junction temperature +150 ° C Operating temperature range – 40 to +125 ° C Storage temperature range – 60 to +150 ° C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

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ADS1281

SBAS378A – SEPTEMBER 2007 – REVISED NOVEMBER 2007

ELECTRICAL CHARACTERISTICS

Limit specifications at – 40 ° C to +85 ° C, typical specifications at +25 ° C, AVDD = +2.5V, AVSS = – 2.5V, f VREFN = – 2.5V, DVDD = +3.3V, and f

PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS

Full-scale input voltage VIN= AINP – AINN ± V Absolute input range AINP or AINN AVSS – 0.1 AVDD + 0.1 V Differential input impedance 55 k Ω

AC PERFORMANCE

Signal-to-noise ratio

(2)

Total harmonic distortion THD – 122 – 115 dB Spurious-free dynamic

(3)

range

DC PERFORMANCE

Resolution No missing codes 31 Bits

Data rate f

Integral nonlinearity

(4)

Offset error 10 200 µ V Offset error after calibration

(6)

Offset drift 0.06 µ V/ ° C Gain error 0.1 0.3 % Gain error after calibration

(6)

Gain drift 0.4 ppm/ ° C Common-mode rejection fCM= 60Hz 105 120 dB

Power-supply rejection fPS= 60Hz dB

AVDD, AVSS 85 95

FIR DIGITAL FILTER RESPONSE

Passband ripple ± 0.003 dB Passband ( – 0.01dB) 0.375 × f Stop band attenuation

(7)

Stop band 0.500 × f Bandwidth ( – 3dB) 0.413 × f

Group delay s

Settling time (latency) s

High-pass filter corner 0.1 10 Hz

(1) f (2) SNR = signal-to-noise ratio = 20 log (V

= system clock.

CLK

(3) Highest spurious component including harmonics.

= 1000SPS, unless otherwise noted.

DATA

= 250SPS 130

DATA

= 500SPS 127

DATA

SNR f

SFDR 123 dB

DATA

VIN= 31.25Hz, – 0.5dBFS

= 1000SPS 120 124 dB

DATA

= 2000SPS 121

DATA

= 4000SPS 118

DATA

FIR filter mode 250 4000 SPS

Sinc filter mode 8,000 128,000 SPS

INL Differential input 0.00006 0.0005 % FSR

Shorted input 1 µ V

DVDD 85 105

135 dB

FIR filter, minimum phase 5/f

FIR filter, linear phase 31/f

FIR filter, minimum phase 10/f

FIR filter, linear phase 62/f

Full-Scale/V

RMS

Noise), VIN= 20mV

(4) Best-fit method. (5) FSR: Full-scale range = ± V (6) Calibration accuracy is on the level of noise reduced by 4 (calibration averages 16 readings). (7) Input frequencies in the range of Nf

ranges intermodulation = 120dB, typ.

/2.

REF

CLK

/512 ± f

/2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency

DATA

(1)

= 4.096MHz, VREFP = +2.5V,

CLK

ADS1281

/2 V

REF

0.0002 %

DATA

DATA DATA

DATA

DATA DATA DATA

(5)

Hz Hz

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ADS1281

SBAS378A – SEPTEMBER 2007 – REVISED NOVEMBER 2007

ELECTRICAL CHARACTERISTICS (continued)

Limit specifications at – 40 ° C to +85 ° C, typical specifications at +25 ° C, AVDD = +2.5V, AVSS = – 2.5V, f VREFN = – 2.5V, DVDD = +3.3V, and f

PARAMETER CONDITIONS MIN TYP MAX UNIT VOLTAGE REFERENCE INPUTS

Reference input voltage (AVDD – AVSS) V

= VREFP – VREFN + 0.2

REF

Negative reference input VREFN AVSS – 0.1 VREFP – 0.5 V Positive reference input VREFP VREFN + 0.5 AVDD + 0.1 V Reference input impedance 85 k Ω

DIGITAL INPUT/OUTPUT

Input leakage 0 < V Clock input f

POWER SUPPLY

AVSS – 2.6 0 V AVDD AVSS + 4.75 AVSS + 5.25 V DVDD 1.65 3.6 V

AVDD, AVSS current Standby mode 1 15 | µ A |

DVDD current

Power dissipation Standby mode 90 250 µ W

= 1000SPS, unless otherwise noted.

DATA

CLK

Power-Down mode 1 15 | µ A |

Power-Down mode

Power-Down mode 10 150 µ W

0.5 5 V

0.8 × DVDD DVDD V DGND 0.2 × DVDD V

IOH= 1mA 0.8 × DVDD V IOL= 1mA 0.2 × DVDD V

< DVDD ± 10 µ A

DIGITAL IN

1 4.096 MHz

Operating mode 2 3 | mA |

Operating mode 0.6 0.8 mA Modulator mode 0.1 mA

Standby mode 25 50 µ A

(8)

Operating mode 12 18 mW

(8) CLK input stopped.

= 4.096MHz, VREFP = +2.5V,

CLK

ADS1281

1 15 µ A

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CLK

SCLK

DRDY

DOUT

MOD/DIN

DGND

PHS/MCLK

DR1/M1

DR0/M0

HPF/SYNC

MFLAG

DGND

BYPAS

DGND

DVDD

PINMODE

RESET

PWDN

VREFP

VREFN

AVSS

AVDD

AINN

AINP

ADS1281

SBAS378A – SEPTEMBER 2007 – REVISED NOVEMBER 2007

DEVICE INFORMATION

TSSOP-24

Top View

TERMINAL FUNCTIONS

DESCRIPTION

NAME NO. FUNCTION PIN MODE (PINMODE = 1) REGISTER MODE (PINMODE = 0)

CLK 1 Digital input Master clock input Master clock input

SCLK 2 Digital input SPI serial clock input SPI serial clock input DRDY 3 Digital output Data ready output: read data on falling edge Data ready output: read data on falling edge DOUT 4 Digital output SPI serial data output SPI serial data output

MOD/DIN 5 Digital input DIN: SPI serial data input

PHS/MCLK 7 Digital I/O 0 = Linear phase filter, 1 = Minimum phase filter MCLK: Modulator clock output

DR1/M1 8 Digital I/O M1: Modulator data output 1

DR0/M0 9 Digital I/O M0: Modulator data output 0

HPF/SYNC 10 Digital input SYNC: Synchronize input

(MOD = 0) HPF: 0 = High-pass filter off, 1 = HPF on

MFLAG 11 Digital output

DGND 6, 12, 23 Digital ground Digital ground, pin 12 is the key ground point Digital ground, pin 12 is the key ground point

AINP 13 Analog input Positive analog input Positive analog input

AINN 14 Analog input Negative analog input Negative analog input AVDD 15 Analog supply Positive analog power supply Positive analog power supply AVSS 16 Analog supply Negative analog power supply Negative analog power supply

VREFN 17 Analog input Negative reference input Negative reference input VREFP 18 Analog input Positive reference input Positive reference input

PWDN 19 Digital input Power-down input, active low Power-down input, active low

RESET 20 Digital input Synchronize input Reset input

PINMODE 21 Digital input 1 = Pin mode 0 = Register mode

DVDD 22 Digital supply Digital power supply: +1.8V to +3.3V Digital power supply: +1.8V to +3.3V

BYPAS 24 Capacitor bypass Digital core bypass; 1 µ F bypass capacitor to GND Digital core bypass; 1 µ F bypass capacitor to GND

MOD: 0 = Digital filter mode

1 = Filter bypass (modulator output)

(MOD = 0) PHS: If in modulator mode: (MOD = 1) MCLK: Modulator clock output Otherwise, the pin is an unused input (must be tied). (MOD = 0) DR1 = Data rate select input 1

(MOD = 1) M1 = Modulator data output 1

(MOD = 0) DR0 = Data rate select input 0

(MOD = 1) M0 = Modulator data output 0

Otherwise, the pin is an unused input (must be tied).

If in modulator mode:

(MOD = 1) SYNC = Synchronize Input

Modulator over-range flag: Modulator over-range flag:

0 = Normal, 1 = Modulator over-range 0 = Normal, 1 = Modulator over-range

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SCLK

DIN

DOUT

SCLK

SPWH

SCDL

DIST

DIHD

SPWL

SCDL

DOHD

DOPD

ADS1281

SBAS378A – SEPTEMBER 2007 – REVISED NOVEMBER 2007

TIMING DIAGRAM

TIMING REQUIREMENTS

At TA= – 40 ° C to +85 ° C and DVDD = 1.65V to 3.6V, unless otherwise noted.

PARAMETER DESCRIPTION MIN MAX UNITS

SCLK

SPWH, L

DIST

DIHD

DOPD

DOHD

SCDL

(1) Holding SCLK low for 64 DRDY falling edges resets the SPI interface. (2) Load on DOUT = 20pF || 100k Ω .

SCLK period 2 16 1/f SCLK pulse width, high and low

(1)

0.8 10 1/f DIN valid to SCLK rising edge: setup time 50 ns Valid DIN to SCLK rising edge: hold time 50 ns SCLK falling edge to valid new DOUT: propagation delay

(2)

SCLK falling edge to DOUT invalid: hold time 0 ns Final SCLK rising edge of command to first SCLK rising edge for register read/write

data. (Also between consecutive commands.)

24 1/f

CLK CLK

100 ns

CLK

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TYPICAL CHARACTERISTICS

0 50

Frequency(Hz)

-20

-40

-60

-80

-180

Amplitude(dB)

100 150 500250 350 450200 300 400

-100

-120

-140

-160

V = 0.5dBFS,31.25Hz

THD= 121.8dB

0 50

Frequency(Hz)

-20

-40

-60

-80

-180

Amplitude(dB)

100 150 500250 350 450200 300 400

-100

-120

-140

-160

V = 20dBFS,31.25Hz

THD= 120.1dB

0 50

Frequency(Hz)

-20

-40

-60

-80

-180

Amplitude(dB)

100 150 500250 350 450200 300 400

-100

-120

-140

-160

ShortedInput

SNR=124.1dB

0 50

Frequency(Hz)

-20

-40

-60

-80

-180

Amplitude(dB)

100 150 500250 350 450200 300 400

-100

-120

-140

-160

V =20mV

SNR=124.3dB

IN DC

10 20

InputFrequency(Hz)

-100

-105

-110

-115

-120

-130

THD(dB)

30 40 10060 8050 70 90

-125

THDLimitedby SignalGenerator

V = 0.5dBFS-

122.00

SNR(dB)

Occurences

122.50

123.00

123.50

124.00

124.50

125.00

122.25

122.75

123.25

123.75

124.25

124.75

25Units ShortedInput

At TA= +25 ° C, AVDD = +2.5V, AVSS = – 2.5V, f

= 1000SPS, unless otherwise noted.

DATA

OUTPUT SPECTRUM OUTPUT SPECTRUM

Figure 1. Figure 2.

SBAS378A – SEPTEMBER 2007 – REVISED NOVEMBER 2007

= 4.096MHz, VREFP = +2.5V, VREFN = – 2.5V, DVDD = +3.3V, and

CLK

ADS1281

OUTPUT SPECTRUM OUTPUT SPECTRUM

Figure 3. Figure 4.

THD vs INPUT FREQUENCY SNR HISTOGRAM

Figure 5. Figure 6.

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-55 -35 Temperature( C)°

125

124

123

122

121

120

SNR(dB)

-15 5 12545 8525 65 105

SNR:ShortedInput

THD:V =31.25Hz, 0.5dBFS-

-115

-117

-119

-121

-123

-125

THD(dB)

0 1

V (V)

REF

Noise( V

)

2 3 654

-105

-110

-115

-135

THD(dB)

-120

Noise:ShortedInput

THD:V =31.25Hz, 0.5dBFS-

2 -125

1 -130

1.0 1.5 f (MHz)

CLK

125

123

121

117

SNR(dB)

2.0 2.5 4.53.53.0 4.0

119

-105

-110

-115

-125

THD(dB)

-120

SNR:ShortedInput

THD:V =31.25Hz, 0.5dBFS-

DataRate=f /4096

CLK

10 100

PowerSupplyandCommon-ModeFrequency(Hz)

140

120

100

PSRandCMR(dB)

1k 10k 1M100k

CMR

AVDD

AVSS

DVDD

-2.5 -2.0

InputLevel(V)

-1

-3

LinearityError(ppm)

-1.5 -1.0 2.50 1.0 2.0-0.5 0.5 1.5

-2

IntegralNonlinearity= 0.5ppm±

-55 -35 Temperature( C)°

INL(ppm)

-15 5 1256525 85 105

Power(mW)

INL

Power

ADS1281

SBAS378A – SEPTEMBER 2007 – REVISED NOVEMBER 2007

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, AVDD = +2.5V, AVSS = – 2.5V, f f

= 1000SPS, unless otherwise noted.

DATA

= 4.096MHz, VREFP = +2.5V, VREFN = – 2.5V, DVDD = +3.3V, and

CLK

SNR AND THD vs TEMPERATURE NOISE AND THD vs V

Figure 7. Figure 8.

POWER-SUPPLY AND COMMON-MODE REJECTION

SNR AND THD vs f

CLK

vs FREQUENCY

REF

Figure 9. Figure 10.

LINEARITY ERROR vs INPUT LEVEL INL AND POWER vs TEMPERATURE

Figure 11. Figure 12.

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-55 -35 Temperature( C)°

200

100

-100

-200

-400

NormalizedGainError(ppm)

-15 5 12545 8525 65 105

-300

GainError

5Units

Offset

100

-50

NormalizedOffset(

-25

0 0.5

f (MHz)

CLK

Power(mW)

1.0 1.5 4.52.5 3.52.0 3.0 4.0

-100

Offset( V)m

Occurences

-80

-60

-40

-20

100

-70

-50

-30

-10

25Units

-0.50

GainError(%)

Occurences

-0.40

-0.30

-0.20

-0.10

0.10

0.20

0.30

0.40

0.50

-0.45

-0.35

-0.25

-0.15

-0.05

0.05

0.15

0.25

0.35

0.45

25Units

-1.0

OffsetDrift( V/ C)m °

Occurences

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

0.9

-0.7

-0.5

-0.3

0.1

0.3

0.5

0.7

0.9

25Units Basedon20 C IntervalsOvertheRange

40 Cto+85 C.

°- °

-2.0

GainDrift(ppm/ C)°

Occurences

-1.6

-1.2

-0.8

-0.4

0.4

0.8

1.2

1.6

2.0

1.8

-1.4

-1.0

-0.6

0.2

0.6

1.0

1.4

1.8

25Units

Basedon20 CIntervals

OvertheRange

40 Cto+85 C.

° °-

TYPICAL CHARACTERISTICS (continued)

At TA= +25 ° C, AVDD = +2.5V, AVSS = – 2.5V, f f

= 1000SPS, unless otherwise noted.

DATA

SBAS378A – SEPTEMBER 2007 – REVISED NOVEMBER 2007

= 4.096MHz, VREFP = +2.5V, VREFN = – 2.5V, DVDD = +3.3V, and

CLK

ADS1281

POWER vs f

CLK

GAIN AND OFFSET vs TEMPERATURE

Figure 13. Figure 14.

OFFSET HISTOGRAM GAIN ERROR HISTOGRAM

Figure 15. Figure 16.

OFFSET DRIFT HISTOGRAM GAIN DRIFT HISTOGRAM

Figure 17. Figure 18.

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4th-Order

Modulator

Programmable

DigitalFilter

Serial

Interface

Calibration

Control

AINP

AVDD

AVSS

DVDDCLK

DGND

HPF/SYNC

AINN

VREFN

MFLAG

VREFP

ADS1281

RESET

PINMODE

PWDN

Over-Range

Detection

MOD/DIN DOUT

DRDY

SCLK

LDO

PHS/MCLK

DR0/M0

DR1/M1

+1.8V

(DigitalCore)

BYPAS

ADS1281

SBAS378A – SEPTEMBER 2007 – REVISED NOVEMBER 2007

OVERVIEW

The ADS1281 is a high-performance analog-to-digital The digital filter is comprised of a variable decimation converter (ADC) intended for energy exploration, rate, fifth-order sinc filter followed by a seismic monitoring, chromatography, and other decimate-by-32, FIR low-pass filter with exacting applications. The converter provides 24- or programmable phase, and then by an adjustable 32-bit output data in data rates from 4000SPS to high-pass filter for dc removal of the output reading. 250SPS. The output of the digital filter can be taken from the

Figure 19 shows the block diagram of the ADS1281.

The device features unipolar and bipolar analog Gain and offset registers scale the digital filter output power supplies (AVDD and AVSS, respectively) for to produce the final code value. The scaling feature input range flexibility and a digital supply accepting can be used for calibration and sensor gain matching.

1.8V to 3.3V. The analog supplies may be set to +5V The output data are provided with either a 24-bit word to accept unipolar signals (with input offset) or set or a full 32-bit word, allowing full utilization of the lower in the range of ± 2.5V to accept true bipolar inherently high resolution. input signals (ground referenced).

An internal low-dropout (LDO) regulator is used to device: Pin control or Register control. In Pin control power the digital core from DVDD. The BYPAS pin is mode, the device is controlled by simple pin settings; the LDO output and requires a 0.1 µ F capacitor for there are no registers to program. In Register control noise reduction (BYPAS should not be used to drive mode, the device is controlled by register settings. external circuitry). The functionality of several device pins depends on

The inherently-stable, fourth-order, Δ Σ modulator measures the differential input signal V

= (AINP –

AINN) against the differential reference The SYNC input resets the operation of both the V

= (VREFP – VREFN). A digital output (MFLAG) digital filter and the modulator, allowing synchronized

REF

indicates that the modulator is in over-range resulting conversions of multiple ADS1281 devices to an from an input overdrive condition. The modulator external event. The SYNC input supports a output is available directly on the MCLK, M0, and M1 continuously-toggled input mode that accepts an output pins. The modulator connects to an on-chip external data frame clock locked to an integer of the digital filter that provides the output code readings. conversion rate.

sinc, the FIR low-pass, or the IIR high-pass section.

The PINMODE input pin determines the mode of the

the control mode selected (see the Pin and Register

Modes section).

Figure 19. ADS1281 Block Diagram

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2nd-Order

2nd-Stage

2nd-Order

1st-Stage

AnalogInput(V )

4th-OrderModulator

PHS/MCLK

DR0/M0

DR1/M1

CLK

Y[n]=3M0[n 2] 6M0[n 3]+4M0[n 4]

+9(M1[n] 2M1[n 1]+M1[n 2])

- - - -

- - -

ADS1281

SBAS378A – SEPTEMBER 2007 – REVISED NOVEMBER 2007

The RESET input resets the register settings (Register mode) and also restarts the conversion process.

MODULATOR

The high-performance modulator is an

inherently-stable, fourth-order, Δ Σ , 2 + 2 pipelined The PWDN input sets the device into a micro-power structure, as shown in Figure 20 . It shifts the state. Note that register settings are not retained in quantization noise to a higher frequency (out of the PWDN mode. Use the STANDBY command in its passband) where digital filtering can easily remove it. place if it is desired to retain register settings (the The modulator can be filtered either by the on-chip quiescent current in the Standby mode is slightly digital filter or by use of post-processing filters. higher).

Noise-immune Schmitt-trigger and clock-qualified inputs ( RESET and SYNC) provide increased reliability in high-noise environments.

The serial interface is used to read conversion data, in addition to reading from and writing to the configuration registers.

NOISE PERFORMANCE

The ADS1281 offers outstanding noise performance (SFDR). Table 1 summarizes the typical noise performance.

Table 1. Noise Performance (Typical)

DATA RATE FILTER – 3dB BW (Hz) SNR (dB)

250 FIR 103 130

500 FIR 206 127 1000 FIR 413 124 2000 FIR 826 121 4000 FIR 1652 118

(1) VIN= 20mV

(1)

IDLE TONES

The ADS1281 modulator incorporates an internal dither signal that randomizes the idle tone energy. Low-level idle tones may still be present, typically – 137dB below full-scale. The low-level idle tones can be shifted out of the passband with the application of an external 20mV offset.

The modulator first stage converts the analog input voltage into a pulse-code modulated (PCM) stream. When the level of differential analog input (AINP – AINN) is near one-half the level of the reference voltage 1/2 × (VREFP – VREFN), the ‘ 1 ’ density of the PCM data stream is at its highest. When the level of the differential analog input is near zero, the PCM ‘ 0 ’ and ‘ 1 ’ densities are nearly equal. At the two extremes of the analog input levels (+FS and – FS), the ‘ 1 ’ density of the PCM streams are approximately +90% and +10%, respectively.

The modulator second stage produces a '1' density data stream designed to cancel the quantization noise of the first stage. The data streams of the two stages are then combined before input to the digital filter stage, as shown in Equation 1 .

Figure 20. Fourth-Order Modulator

ADC

The ADC block of the ADS1281 is composed of two blocks: a high-accuracy modulator and a programmable digital filter.

(1)

M0[n] represents the most recent first-stage output while M0[n – 1] is the previous first-stage output. When the modulator output is enabled, the digital filter shuts down to save power.

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Amplitude(dB)

Frequency(Hz)

-20

-40

-60

-80

-100

-180

1 10

100 100k

1k 10k

-120

-140

-160

1HzResolution

V =20mV

IN DC

MOD

MFLAG

100%FS

AINN

AINP

IABSI

ThresholdTolerance: 2.5%Typical±

ADS1281

SBAS378A – SEPTEMBER 2007 – REVISED NOVEMBER 2007

The modulator is optimized for input signals within a If the inputs are sufficiently overdriven to drive the 4kHz passband. As Figure 21 shows, the noise modulator to full duty cycle, all 1s or all 0s shaping of the modulator results in a sharp increase ( ± 110%FSR), the modulator enters a stable saturated in noise above 6kHz. The modulator has a chopped state. The digital output code may clip to +FS or – FS, input structure that further reduces noise within the again depending on the duration. A small duration passband. The noise is moved out of the passband overdrive may not always clip the output code. When and appears at the chopping frequency (f 8kHz). The component at 6.5kHz is the tone requires up to 12 modulator clock cycles (f frequency, shifted out of band by a 20mV external saturation and return to the linear region. The digital input. The frequency of the tone is approximately filter requires an additional 62 conversion for fully V

/3 (in kHz). settled data (linear phase FIR).

/512 = the input returns to the normal range, the modulator

CLK

In the extreme case of over-range, either input is overdriven exceeding that either analog supply voltage plus an internal ESD diode drop. The internal ESD diodes begin to conduct and the signal on the input is clipped. If the differential input signal range is not exceeded, the modulator remains in linear operation. If the differential input signal range is exceeded, the modulator is saturated but stable, and outputs all 1s or 0s. When the input overdrive is removed, the diodes recovery quickly and the ADS1281 recovers as normal. Note that the linear input range is ± 100mV beyond the analog supply voltages; with input levels above this, use care to limit the input current to 100mA peak transient and 10mA continuous.

) to exit

MOD

Figure 21. Modulator Output Spectrum

MODULATOR OVER-RANGE DETECTION (MFLAG)

MODULATOR OVER-RANGE

The ADS1281 modulator is inherently stable and, therefore, has predictable recovery behavior that results from an input overdrive condition. The modulator does not exhibit self-resetting behavior, which often results in an unstable output data stream.

The ADS1281 modulator outputs a 1s density data stream at 90% duty cycle with the positive full-scale input signal applied (10% duty cycle with the negative full-scale signal). If the input is overdriven past 90% modulation, but below 100% modulation (10% and 0% for negative overdrive, respectively), the modulator remains stable and continues to output the 1s density data stream. The digital filter may or may not clip the output codes to +FS or – FS, depending on the duration of the overdrive. When the input is returned to the normal range from a long duration overdrive (worst case), the modulator returns immediately to the normal range, but the group delay of the digital filter delays the return of the conversion result to within the linear range (31 readings for linear phase FIR). 31 additional readings (62 total) are required for completely settled data.

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The ADS1281 has a fast-responding over-range detection, indicating when the differential input exceeds approximately 100% over-range. The threshold tolerance is ± 2.5%.The MFLAG output asserts high when in an over-range condition. As

Figure 22 and Figure 23 illustrate, the absolute value

of the input is compared to 100% of range. The output of the comparator is sampled at the rate of f

/2, yielding the MFLAG output. The minimum

MOD

MFLAG pulse width is f

/2.

MOD

Figure 22. Modulator Over-Range Block Diagram

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MFLAG

+100%

(AINP AINN)-

-100%

CLK

SYNC

PHS/MCLK

DR0/M0 DR1/M1

MCM0, 1

(MCLK=CLK/4)

SCSU

CSHD

CMD

1 2 543

SYMD

Figure 23. Modulator Over-Range Flag Operation (f

MODULATOR OUTPUT MODE

The modulator digital stream output is available directly, bypassing and disabling the internal digital filter. The modulator output mode is activated in the Pin mode by setting MOD/DIN = 1, and in Register mode by setting the CONFIG0 register bits

ADS1281

SBAS378A – SEPTEMBER 2007 – REVISED NOVEMBER 2007

FILTR[1:0] = 00. Pins DR0/M0 and DR1/M1 then become the modulator data outputs and the PHS/MCLK becomes the modulator clock output. When not in the modulator mode, these pins are inputs and must not float.

The modulator output is composed of three signals: one output for the modulator clock (PHS/MCLK) and two outputs for the modulator data (DR0/M0 and DR1/M1). The modulator clock output rate is f

/4). The SYNC input resets the MODCLK phase,

CLK

as shown in Figure 24 . The SYNC input is latched on the rising edge of CLK. The MODCLK resets and the next rising edge of MODCLK occurs five CLK periods later.

The modulator output data are two bits wide, which must be merged together before being filtered. Use the time domain equation of Equation 1 to merge the data outputs.

MOD

Figure 24. Modulator Mode Timing

Modulator Output Timing for Figure 24

PARAMETER DESCRIPTION MIN TYP MAX UNIT

MCD0, 1

CMD

CSHD

SCSU

SYMD

(1) Load on M0 and M1 = 20pF || 100k Ω .

MODCLK rising edge to M0, M1 valid propagation delay CLK rising edge (after SYNC rising edge) to MODCLK rising edge

reset time CLK to SYNC hold time to not latch on CLK edge 10 ns SYNC to CLK setup time to latch on CLK edge 10 ns SYNC to stable bit stream 16 1/f

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(1)

5 1/f

100 ns

CLK

MOD

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H(Z)=

1 Z-

-1

SincFilter

Decimateby

8to128

FIRFilter Decimate

by32

High-Pass

Filter

(IIR)

Filter MUX

ToCalibrationBlock

FromModulator

DirectModulator BitStream

ADS1281

SBAS378A – SEPTEMBER 2007 – REVISED NOVEMBER 2007

DIGITAL FILTER

The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of filtering, tradeoffs can be made between resolution

Table 3. Digital Filter Selection, Pin Mode

MOD/DIN HPF/SYNC

PIN PIN DIGITAL FILTERS SELECTED

1 X Bypass; modulator output mode

and data rate: filter more for higher resolution, filter 0 0 Sinc + FIR less for higher data rate.

The digital filter is comprised of three cascaded filter

0 1

Sinc + FIR + HPF (low-pass and high-pass)

stages: a variable-decimation, fifth-order sinc filter; a fixed-decimation FIR, low-pass filter (LPF) with selectable phase; and a programmable, first-order, high-pass filter (HPF), as shown in Figure 25 .

The output can be taken from one of the three filter blocks, as shown in Figure 25 . To implement the digital filter completely off-chip, select the filter bypass setting (modulator output). For partial filtering by the ADS1281, select the sinc filter output. For complete on-chip filtering, activate both the sinc and FIR stages. The HPF can then be included to remove dc and low frequencies from the data. Table 2 shows the filter options in Register mode. Table 3 shows the

Sinc Filter Stage (sinx/x)

The sinc filter is a variable decimation rate, fifth-order, low-pass filter. Data are supplied to this section of the filter from the modulator at the rate of f The sinc filter attenuates the high-frequency noise of the modulator, then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the converter; it is set by the DR[1:0] and MODE selections, as shown in Table 4 .

Equation 2 shows the scaled Z-domain transfer

function of the sinc filter.

filter options in Pin mode.

Table 2. Digital Filter Selection, Register Mode

FILTR[1:0] BITS DIGITAL FILTERS SELECTED

00 Bypass; modulator output mode 01 Sinc 10 Sinc + FIR

Sinc + FIR + HPF (low-pass and high-pass)

MOD

/4).

CLK

(2)

Figure 25. Digital Filter

Table 4. Sinc Filter Data Rates (CLK = 4.096MHz)

DR[1:0] PINS DR[2:0] REGISTER DECIMATION RATIO (N) SINC DATA RATE (SPS)

00 000 128 8,000 01 001 64 16,000 10 010 32 32,000 11 011 16 64,000

— 100 8 128,000

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+ 32 hidden pages

BURR-BROWN ADS1281 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES DESCRIPTION

APPLICATIONS

ORDERING INFORMATION

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

DEVICE INFORMATION

TIMING DIAGRAM

TIMING REQUIREMENTS

TYPICAL CHARACTERISTICS

OVERVIEW

MODULATOR

NOISE PERFORMANCE

IDLE TONES

MODULATOR OVER-RANGE DETECTION (MFLAG)

MODULATOR OVER-RANGE

MODULATOR OUTPUT MODE

DIGITAL FILTER

Sinc Filter Stage (sinx/x)