BURR-BROWN ADS1210, ADS1211 User Manual
A
D
S
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2
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0
A
D
S
1
2
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1
A
D
S
1
2
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ADS1211
0
A
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ADS1210
ADS1211
SBAS034B – JANUARY 1996 – REVISED SEPTEMBER 2005
24-Bit ANALOG-TO-DIGITAL CONVERTER
FEATURES
● DELTA-SIGMA A/D CONVERTER
● 23 BITS EFFECTIVE RESOLUTION AT 10Hz
AND 20 BITS AT 1000Hz
● DIFFERENTIAL INPUTS
● PROGRAMMABLE GAIN AMPLIFIER
● FLEXIBLE SPI™-COMPATIBLE SSI
INTERFACE WITH 2-WIRE MODE
● PROGRAMMABLE CUT-OFF FREQUENCY
UP TO 15.6kHz
● INTERNAL/EXTERNAL REFERENCE
● ON-CHIP SELF-CALIBRATION
● ADS1211 INCLUDES 4-CHANNEL MUX
APPLICATIONS
● INDUSTRIAL PROCESS CONTROL
● INSTRUMENTATION
● BLOOD ANALYSIS
● SMART TRANSMITTERS
● PORTABLE INSTRUMENTS
● WEIGH SCALES
● PRESSURE TRANSDUCERS
DESCRIPTION
The ADS1210 and ADS1211 are precision, wide dynamic
range, delta-sigma Analog-to-Digital (A/D) converters with
24-bit resolution operating from a single +5V supply. The
differential inputs are ideal for direct connection to transducers or low-level voltage signals. The delta-sigma architecture is used for wide dynamic range and to ensure 22 bits
of no-missing-code performance. An effective resolution of
23 bits is achieved through the use of a very low-noise input
amplifier at conversion rates up to 10Hz. Effective resolutions of 20 bits can be maintained up to a sample rate of
1kHz through the use of the unique Turbo modulator mode
of operation. The dynamic range of the converters is further
increased by providing a low-noise programmable gain
amplifier with a gain range of 1 to 16 in binary steps.
The ADS1210 and ADS1211 are designed for high resolution
measurement applications in smart transmitters, industrial
process control, weigh scales, chromatography, and portable
instrumentation. Both converters include a flexible synchronous serial interface that is SPI-compatible and also offers a
two-wire control mode for low cost isolation.
The ADS1210 is a single-channel converter and is offered in
both 18-pin DIP and 18-lead SOIC packages. The ADS1211
includes a 4-channel input multiplexer and is available in 24pin DIP, 24-lead SOIC, and 28-lead SSOP packages.
AGND AVDDREF
1P
A
IN
A
1N
IN
A
2P
IN
A
2N
IN
A
3P
IN
A
3N
IN
AIN4P
A
4N
IN
MUX
AINP
A
IN
N
Reference
PGA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
OUT
+2.5V
Modulator Control
REF
IN
Second-Order
∆∑
Modulator
www.ti.com
V
BIAS
+3.3V Bias
Generator
Third-Order
Digital Filter
X
IN
Clock Generator
DSYNCADS1211 Only ADS1210/11 CS DRDY
X
OUT
Micro Controller
Instruction Register
Command Register
Data Output Register
Offset Register
Full-Scale Register
Serial Interface
MODE
DGND
DV
DD
SCLK
SDIO
SDOUT
Copyright © 1996-2005, Texas Instruments Incorporated
SPECIFICATIONS
All specifications T
and external 2.5V reference, unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Input Voltage Range
Input Impedance G = Gain, TMR = Turbo Mode Rate 4/(G • TMR)
Programmable Gain Amplifier User Programmable: 1, 2, 4, 8, or 16 1 16
Input Capacitance 8pF
Input Leakage Current At +25°C550pA
SYSTEMS PERFORMANCE
Resolution 24 Bits
No Missing Codes f
Integral Linearity f
Unipolar Offset Error
Unipolar Offset Drift
Gain Error
Gain Error Drift
Common-Mode Rejection
Normal-Mode Rejection 50Hz, f
Output Noise See Typical Performance Curves
Power Supply Rejection DC, 50Hz, and 60Hz 65 dB
VOLTAGE REFERENCE
Internal Reference (REF
Drift 25 ppm/°C
Noise 50 µVp-p
Load Current Source or Sink 1 mA
Output Impedance 2 Ω
External Reference (REF
Load Current 2.5 µA
V
Output Using Internal Reference 3.15 3.3 3.45 V
BIAS
Drift 50 ppm/°C
Load Current Source or Sink 10mA
DIGITAL INPUT/OUTPUT
Logic Family TTL Compatible CMOS
Logic Level: (all except X
X
Input Levels: V
IN
X
Frequency Range (f
IN
Output Data Rate (f
Data Format User Programmable
SYSTEM CALIBRATION
Offset and Full-Scale Limits V
VFS – | VOS |V
to T
MIN
, AVDD = DVDD = +5V, f
MAX
= 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REF
XIN
disabled,V
OUT
BIAS
disabled,
ADS1210U, P/ADS1211U, P, E
(1)
With V
At T
DATA
DATA
f
= 1000Hz, TMR of 16 ±0.0015 %FSR
(4)
(6)
(4)
(6)
(9)
DATA
At DC, +25°C 100 115 dB
At DC, T
50Hz, f
60Hz, f
60Hz, f
) 2.4 2.5 2.6 V
OUT
) 2.0 3.0 V
IN
)
V
IH
V
IL
V
OH
V
OL
IN
IOH = 2 TTL Loads 2.4 V
IOL = 2 TTL Loads 0.4 V
IH
V
IL
) 0.5 10 MHz
XIN
) User Programmable 2.4 15,625 Hz
DATA
f
XIN
(2)
BIAS
to T
MIN
MAX
= 60Hz 22 Bits
= 60Hz ±0.0015 %FSR
to T
MIN
MAX
(7)
= 50Hz
DATA
DATA
DATA
DATA
= 60Hz
= 50Hz
= 60Hz
(7)
(7)
(7)
IIH = +5µA 2.0 DV
IIL = +5µA –0.3 0.8 V
= 500kHz 0.12 781 Hz
0+5V
–10 +10 V
(3)
MΩ
1nA
See Note 5
1 µV/°C
See Note 5
1 µV/°C
90 115 dB
160 dB
160 dB
100 dB
100 dB
+0.3 V
DD
3.5 DV
–0.3 0.8 V
+0.3 V
DD
Two’s Complement
or Offset Binary
= Full-Scale Differential Voltage
FS
= Offset Differential Voltage
OS
(8)
0.7 • (2 • REFIN)/G
(8)
1.3 • (2 • REFIN)/G
2
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ADS1210, ADS1211
SBAS034B
SPECIFICATIONS (CONT)
All specifications T
and external 2.5V reference, unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY REQUIREMENTS
Power Supply Voltage 4.75 5.25 V
Power Supply Current:
Analog Current 2mA
Digital Current 3.5 mA
Additional Analog Current with
REF
V
BIAS
Power Dissipation 26 40 mW
TEMPERATURE RANGE
Specified –40 +85 °C
Storage –60 +125 °C
NOTES: (1) In order to achieve the converter’s full-scale range, the input must be fully differential (A
A
P is fixed), then the full-scale range is one-half that of the differential range. (2) This range is set with external resistors and V
IN
Other ranges are possible. (3) Input impedance is higher with lower f
of the effective resolution of the converter. Refer to the Typical Performance Curves which apply to the desired mode of operation. (6) Recalibration can remove
these errors. (7) The specification also applies at f
mode rejection test is performed with a 100mV differential input.
to T
MIN
Enabled 1.6 mA
OUT
Enabled No Load 1 mA
, AVDD = DVDD = +5V, f
MAX
= 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REF
XIN
ADS1210U, P/ADS1211U, P, E
TMR of 16 37 60 mW
f
= 2.5MHz 17 mW
XIN
f
= 2.5MHz, TMR of 16 27 mW
XIN
Sleep Mode 11 mW
N = 2 • REFIN – AINP). If the input is single-ended (AINN or
IN
. (4) Applies after calibration. (5) After system calibration, these errors will be of the order
XIN
/i, where i is 2, 3, 4, etc. (8) Voltages at the analog inputs must remain within AGND to AVDD. (9) The common-
DATA
disabled,V
OUT
(as described in the text).
BIAS
BIAS
disabled,
ABSOLUTE MAXIMUM RATINGS
Analog Input: Current................................................ ±100mA, Momentary
AV
DD
AV
DD
DV
DD
AGND to DGND ................................................................................±0.3V
REF
Digital Input Voltage to DGND ..................................–0.3V to DV
Digital Output Voltage to DGND ............................... –0.3V to DV
Lead Temperature (soldering, 10s) .............................................. +300°C
Power Dissipation (Any package) .................................................. 500mW
Voltage ................................... AGND –0.3V to AV
to DVDD...........................................................................–0.3V to 6V
to AGND .........................................................................–0.3V to 6V
to DGND.........................................................................–0.3V to 6V
Voltage to AGND............................................ –0.3V to AVDD +0.3V
IN
±10mA, Continuous
DD
DD
DD
+0.3V
+0.3V
+0.3V
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information,
see the Package Option Addendum located at the end of
this data sheet.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
ADS1210, ADS1211
SBAS034B
www.ti.com
3
ADS1210 SIMPLIFIED BLOCK DIAGRAM
AGND AV
3
REF
DD
OUT
REF
IN
16 17 18 4 7 8
+2.5V
Reference
1
AINP
A
IN
2
N
PGA
Second-Order
∆Σ
Modulator
Modulator Control
ADS1210 PIN CONFIGURATION
TOP VIEW DIP/SOIC
A
IN
A
IN
AGND
V
BIAS
CS
DSYNC
X
X
OUT
DGND
1
P
2
N
3
4
ADS1210
5
6
7
IN
8
9
18
17
16
15
14
13
12
11
10
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
V
BIAS
+3.3V Bias
Generator
X
IN
Clock Generator
Third-Order
Digital Filter
65 1415
DSYNC CS DRDYMODE
ADS1210 PIN DEFINITIONS
PIN NO NAME DESCRIPTION
1A
2A
3 AGND Analog Ground.
4V
5 CS Chip Select Input.
6 DSYNC Control Input to Synchronize Serial Output Data.
7X
8X
9 DGND Digital Ground.
10 DV
11 SCLK Clock Input/Output for serial data transfer.
12 SDIO Serial Data Input (can also function as Serial Data
13 SDOUT Serial Data Output.
14 DRDY Data Ready.
15 MODE SCLK Control Input (Master = 1, Slave = 0).
16 AV
17 REF
18 REF
P Noninverting Input.
IN
N Inverting Input.
IN
BIAS
IN
OUT
DD
DD
OUT
IN
X
OUT
9
DGND
DV
10
DD
Micro Controller
Instruction Register
Command Register
Data Output Register
Offset Register
Full-Scale Register
11
SCLK
Serial Interface
12
SDIO
13
SDOUT
Bias Voltage Output, +3.3V nominal.
System Clock Input.
System Clock Output (for Crystal or Resonator).
Digital Supply, +5V nominal.
Output).
Analog Supply, +5V nominal.
Reference Output, +2.5V nominal.
Reference Input.
4
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ADS1210, ADS1211
SBAS034B
ADS1211 SIMPLIFIED BLOCK DIAGRAM
AGND AV
REF
DD
OUT
REF
IN
6 19 20 21 7 10 11
+2.5V
4
A
1P
IN
5
1N
A
IN
2
2P
A
IN
3
2N
A
IN
3P
A
IN
3N
A
IN
4P
A
IN
4N
A
IN
MUX
24
1
22
23
Reference
PGA
Second-Order
∆∑
Modulator
Modulator Control
ADS1211P AND ADS1211U PIN CONFIGURATION
TOP VIEW DIP/SOIC
A
3N
IN
A
2P
IN
A
2N
IN
A
1P
IN
A
1N
IN
AGND
V
BIAS
CS
DSYNC
X
X
OUT
DGND
1
2
3
4
5
6
ADS1211P
7
ADS1211U
8
9
10
IN
11
12
24
23
22
21
20
19
18
17
16
15
14
13
3P
A
IN
A
4N
IN
A
4P
IN
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
V
BIAS
+3.3V Bias
Generator
X
IN
Clock Generator
X
OUT
12
13
Micro Controller
Third-Order
Digital Filter
Instruction Register
Command Register
Data Output Register
Offset Register
Full-Scale Register
14
Serial Interface
15
16
98 1718
DSYNC CS DRDYMODE
ADS1211P AND ADS1211U PIN DEFINITIONS
PIN NO NAME DESCRIPTION
1AIN3N Inverting Input Channel 3.
2AIN2P Noninverting Input Channel 2.
3A
4A
5AIN1N Inverting Input Channel 1.
6 AGND Analog Ground.
7V
8 CS Chip Select Input.
9 DSYNC Control Input to Synchronize Serial Output Data.
10 X
11 X
12 DGND Digital Ground.
13 DV
14 SCLK Clock Input/Output for serial data transfer.
15 SDIO Serial Data Input (can also function as Serial Data
16 SDOUT Serial Data Output.
17 DRDY Data Ready.
18 MODE SCLK Control Input (Master = 1, Slave = 0).
19 AV
20 REF
21 REF
22 A
23 AIN4N Inverting Input Channel 4.
24 A
2N Inverting Input Channel 2.
IN
1P Noninverting Input Channel 1.
IN
BIAS
OUT
Bias Voltage Output, +3.3V nominal.
System Clock Input.
IN
System Clock Output (for Crystal or Resonator).
Digital Supply, +5V nominal.
DD
Output).
Analog Supply, +5V nominal.
DD
Reference Output: +2.5V nominal.
OUT
Reference Input.
IN
4P Noninverting Input Channel 4.
IN
3P Noninverting Input Channel 3.
IN
DGND
DV
DD
SCLK
SDIO
SDOUT
ADS1210, ADS1211
SBAS034B
www.ti.com
5
ADS1211E PIN CONFIGURATION
TOP VIEW SSOP
A
3N
IN
A
2P
IN
A
2N
IN
A
1P
IN
A
1N
IN
AGND
V
BIAS
NIC
NIC
CS
DSYNC
X
X
OUT
DGND
1
2
3
4
5
6
7
ADS1211E
8
9
10
11
12
IN
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
3P
A
IN
A
4N
IN
A
4P
IN
REF
IN
REF
OUT
AV
DD
MODE
NIC
NIC
DRDY
SDOUT
SDIO
SCLK
DV
DD
ADS1211E PIN DEFINITIONS
PIN NO NAME DESCRIPTION
1A
2A
3A
4A
5A
6 AGND Analog Ground.
7V
8 NIC Not Internally Connected.
9 NIC Not Internally Connected.
10 CS Chip Select Input.
11 DSYNC Control Input to Synchronize Serial Output Data.
12 X
13 X
14 DGND Digital Ground.
15 DV
16 SCLK Clock Input/Output for serial data transfer.
17 SDIO Serial Data Input (can also function as Serial Data
18 SDOUT Serial Data Output.
19 DRDY Data Ready.
20 NIC Not Internally Connected.
21 NIC Not Internally Connected.
22 MODE SCLK Control Input (Master = 1, Slave = 0).
23 AV
24 REF
25 REF
26 A
27 AIN4N Inverting Input Channel 4.
28 A
3N Inverting Input Channel 3.
IN
2P Noninverting Input Channel 2.
IN
2N Inverting Input Channel 2.
IN
1P Noninverting Input Channel 1.
IN
1N Inverting Input Channel 1.
IN
Bias Voltage Output, +3.3V nominal.
BIAS
System Clock Input.
IN
System Clock Output (for Crystal or Resonator).
OUT
Digital Supply, +5V nominal.
DD
Output).
Analog Supply, +5V nominal.
DD
Reference Output: +2.5V nominal.
OUT
Reference Input.
IN
4P Noninverting Input Channel 4.
IN
3P Noninverting Input Channel 3.
IN
6
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ADS1210, ADS1211
SBAS034B
TYPICAL PERFORMANCE CURVES
At TA = +25°C, AVDD = DV
2.5V reference, unless otherwise noted.
DD =
+5V, f
= 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of one, REF
XIN
disabled, V
OUT
disabled, and external
BIAS
EFFECTIVE RESOLUTION vs DATA RATE
24
22
20
18
16
14
Effective Resolution in Bits (rms)
12
1 10 100 1k
24
22
20
18
16
14
Effective Resolution in Bits (rms)
12
10 100 1k
Turbo 1
Turbo 2
EFFECTIVE RESOLUTION vs DATA RATE
Turbo 1
(1MHz Clock)
Turbo 16
Turbo 4
Data Rate (Hz)
(5MHz Clock)
Turbo 16
Turbo 2
Turbo 4
Data Rate (Hz)
Turbo 8
Turbo 8
EFFECTIVE RESOLUTION vs DATA RATE
24
22
20
18
16
14
Effective Resolution in Bits (rms)
12
1 10 100 1k
24
22
20
18
16
14
Effective Resolution in Bits (rms)
12
10 100 1k
Turbo 1
EFFECTIVE RESOLUTION vs DATA RATE
Turbo 1
(2.5MHz Clock)
Turbo 16
Turbo 2
Turbo 4
Data Rate (Hz)
(10MHz Clock)
Turbo 8
Turbo 2
Turbo 4
Data Rate (Hz)
Turbo 8
Turbo 16
24
22
20
18
16
14
12
Effective Resolution in Bits (rms)
10
EFFECTIVE RESOLUTION vs DATA RATE
PGA 1
PGA 2 PGA 4
PGA 16
PGA 8
10
ADS1210, ADS1211
SBAS034B
100 1k
Data Rate (Hz)
www.ti.com
RMS NOISE vs INPUT VOLTAGE LEVEL
2.5
2.0
1.5
RMS Noise (ppm)
1.0
0.5
–5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0
(60Hz Data Rate)
Analog Input Differential Voltage (V)
7
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, AVDD = DV
2.5V reference, unless otherwise noted.
DD =
+5V, f
= 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REF
XIN
disabled, V
OUT
disabled, and external
BIAS
POWER DISSIPATION vs TURBO MODE RATE
50.0
40.0
10MHz
30.0
Power Dissipation (mW)
20.0
85.0
80.0
5MHz
2.5MHz
1MHz
124816
(REF
Enabled)
OUT
Turbo Mode Rate
PSRR vs FREQUENCY
POWER DISSIPATION vs TURBO MODE RATE
40.0
30.0
10MHz
20.0
Power Dissipation (mW)
10.0
120.0
5MHz
2.5MHz
1MHz
124816
(External Reference; REF
Turbo Mode Rate
CMRR vs FREQUENCY
OUT
)
75.0
PSRR (dB)
70.0
65.0
0.1 1 10 100
Frequency (Hz)
115.0
CMRR (dB)
110.0
1k 10k 100k
LINEARITY vs TEMPERATURE
8
6
4
2
0
–2
Integral Nonlinearity (ppm)
–4
–6
–5 –4 –3 –2 –1012345
(60Hz Data Rate)
Analog Input Differential Voltage (V)
0.1 1 10
100 1k
Frequency (Hz)
–40°C
–5°C
+25°C
+55°C
+85°C
8
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ADS1210, ADS1211
SBAS034B
THEORY OF OPERATION
The ADS1210 and ADS1211 are precision, high dynamic
range, self-calibrating, 24-bit, delta-sigma A/D converters
capable of achieving very high resolution digital results.
Each contains a programmable gain amplifier (PGA); a
second-order delta-sigma modulator; a programmable digital filter; a microcontroller including the Instruction, Command and Calibration registers; a serial interface; a clock
generator circuit; and an internal 2.5V reference. The
ADS1211 includes a 4-channel input multiplexer.
In order to provide low system noise, common-mode rejection of 115dB and excellent power supply rejection, the
design topology is based on a fully differential switched
capacitor architecture. Turbo Mode, a unique feature of the
ADS1210/11, can be used to boost the sampling rate of the
input capacitor, which is normally 19.5kHz with a 10MHz
clock. By programming the Command Register, the sampling rate can be increased to 39kHz, 78kHz, 156kHz, or
312kHz. Each increase in sample rate results in an increase
in performance when maintaining the same output data rate.
The programmable gain amplifier (PGA) of the ADS1210/
11 can be set to a gain of 1, 2, 4, 8 or 16—substantially
increasing the dynamic range of the converter and simplifying the interface to the more common transducers (see Table
I). This gain is implemented by increasing the number of
samples taken by the input capacitor from 19.5kHz for a
gain of 1 to 312kHz for a gain of 16. Since the Turbo Mode
and PGA functions are both implemented by varying the
sampling frequency of the input capacitor, the combination
of PGA gain and Turbo Mode Rate is limited to 16 (see
Table II). For example, when using a Turbo Mode Rate of
8 (156kHz at 10MHz), the maximum PGA gain setting is 2.
ANALOG ANALOG INPUT
(1)
INPUT
FULL- EXAMPLE FULL- EXAMPLE
GAIN RANGE RANGE
SETTING (V) (V) (V) (V)
1 10 0 to 5 40 ±10
2 5 1.25 to 3.75 20 ±5
4 2.5 1.88 to 3.13 10 ±2.5
8 1.25 2.19 to 2.81 5 ±1.25
16 0.625 2.34 to 2.66 2.5 ±0.625
NOTE: (1) With a 2.5V reference, such as the internal reference. (2) This
example utilizes the circuit in Figure 12. Other input ranges are possible. (3)
The ADS1210/11 allows common-mode voltage as long as the absolute
input voltage on A
SCALE VOLTAGE SCALE VOLTAGE
P or AINN does not go below AGND or above AVDD.
IN
UTILIZING V
(3)
RANGE RANGE
BIAS
(1,2)
(3)
TABLE I. Full-Scale Range vs PGA Setting.
TURBO MODE RATE AVAILABLE PGA SETTINGS
1 1, 2, 4, 8, 16
2 1, 2, 4, 8
4 1, 2, 4
8 1, 2
16 1
The output data rate of the ADS1210/11 can be varied from
a few hertz to as much as 15,625kHz, trading off lower
resolution results for higher data rates. In addition, the data
rate determines the first null of the digital filter and sets the
–3dB point of the input bandwidth (see the Digital Filter
section). Changing the data rate of the ADS1210/11 does not
result in a change in the sampling rate of the input capacitor.
The data rate effectively sets the number of samples which
are used by the digital filter to obtain each conversion result.
A lower data rate results in higher resolution, lower input
bandwidth, and different notch frequencies than a higher
data rate. It does not result in any change in input impedance
or modulator frequency, or any appreciable change in power
consumption.
The ADS1210/11 also includes complete on-board calibration that can correct for internal offset and gain errors or
limited external system errors. Internal calibration can be
run when needed, or automatically and continuously in the
background. System calibration can be run as needed and the
appropriate input voltages must be provided to the ADS1210/
11. For this reason, there is no continuous System Calibration Mode. The calibration registers are fully readable and
writable. This feature allows for switching between various
configurations—different data rates, Turbo Mode Rates, and
gain settings—without re-calibrating.
The various settings, rates, modes, and registers of the
ADS1210/11 are read or written via a synchronous serial
interface. This interface can operate in either a self-clocked
mode (Master Mode) or an externally clocked mode (Slave
Mode). In the Master Mode, the serial clock (SCLK) frequency is one-half of the ADS1210/11 XIN clock frequency.
This is an important consideration for many systems and
may determine the maximum ADS1210/11 clock that can be
used.
The high resolution and flexibility of the ADS1210/11 allow
these converters to fill a wide variety of A/D conversion
tasks. In order to ensure that a particular configuration will
meet the design goals, there are several important items
which must be considered. These include (but are certainly
not limited to) the needed resolution, required linearity,
desired input bandwidth, power consumption goal, and sensor output voltage.
The remainder of this data sheet discusses the operation of
the ADS1210/11 in detail. In order to allow for easier
comparison of different configurations, “effective resolution” is used as the figure of merit for most tables and
graphs. For example, Table III shows a comparison between
data rate (and –3dB input bandwidth) versus PGA setting at
a Turbo Mode Rate of 1 and a clock rate of 10MHz. See the
Definition of Terms section for a definition of effective
resolution.
TABLE II. Available PGA Settings vs Turbo Mode Rate.
ADS1210, ADS1211
SBAS034B
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9
DATA -3DB
RATE FREQUENCY
(HZ) (HZ) G = 1 G = 2 G = 4 G = 8 G = 16
10 2.62 21.5 21.0 21.0 21.0 20.0
25 6.55 20.5 20.5 20.5 20.0 19.5
30 7.86 20.5 20.5 20.5 20.0 19.5
50 13.1 20.0 20.0 20.0 19.5 19.0
60 15.7 19.5 19.5 19.5 19.0 19.0
100 26.2 18.0 18.0 18.0 18.0 18.0
250 65.5 15.0 15.0 15.0 15.0 15.0
500 131 12.5 12.5 12.5 12.5 12.5
1000 262 10.0 10.5 10.0 10.0 10.0
EFFECTIVE RESOLUTION (BITS RMS)
TABLE III. Effective Resolution vs Data Rate and Gain
Setting. (Turbo Mode Rate of 1 and a 10MHz
clock.)
DEFINITION OF TERMS
An attempt has been made to be consistent with the terminology used in this data sheet. In that regard, the definition
of each term is given as follows:
Analog Input Differential Voltage—For an analog signal
that is fully differential, the voltage range can be compared
to that of an instrumentation amplifier. For example, if both
analog inputs of the ADS1210 are at 2.5V, then the differential voltage is 0V. If one is at 0V and the other at 5V, then
the differential voltage magnitude is 5V. But, this is the case
regardless of which input is at 0V and which is at 5V, while
the digital output result is quite different.
The analog input differential voltage is given by the following equation: AINP – AINN. Thus, a positive digital output is
produced whenever the analog input differential voltage is
positive, while a negative digital output is produced whenever the differential is negative.
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 2, the positive fullscale output is produced when the analog input differential
is 2.5V. The negative full-scale output is produced when the
differential is –2.5V. In each case, the actual input voltages
must remain within the AGND to AVDD range (see Table I).
Actual Analog Input Voltage—The voltage at any one
analog input relative to AGND.
Full-Scale Range (FSR)—As with most A/D converters,
the full-scale range of the ADS1210/11 is defined as the
“input” which produces the positive full-scale digital output
minus the “input” which produces the negative full-scale
digital output.
For example, when the converter is configured with a 2.5V
reference and is placed in a gain setting of 2, the full-scale
range is: [2.5V (positive full scale) minus –2.5V (negative
full scale)] = 5V.
Typical Analog Input Voltage Range—This term describes the actual voltage range of the analog inputs which
will cover the converter’s full-scale range, assuming that
each input has a common-mode voltage that is greater than
REFIN/PGA and smaller than (AVDD – REFIN/PGA).
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 2, the typical input
voltage range is 1.25V to 3.75V. However, an input range of
0V to 2.5V or 2.5V to 5V would also cover the converter’s
full-scale range.
Voltage Span—This is simply the magnitude of the typical
analog input voltage range. For example, when the converter
is configured with a 2.5V reference and placed in a gain
setting of 2, the input voltage span is 2.5V.
Least Significant Bit (LSB) Weight—This is the theoretical amount of voltage that the differential voltage at the
analog input would have to change in order to observe a
change in the output data of one least significant bit. It is
computed as follows:
LSB Weight =
Full−Scale Range
N
2
where N is the number of bits in the digital output.
Effective Resolution—The effective resolution of the
ADS1210/11 in a particular configuration can be expressed
in two different units: bits rms (referenced to output) and
microvolts rms (referenced to input). Computed directly
from the converter’s output data, each is a statistical calculation based on a given number of results. Knowing one, the
other can be computed as follows:
10V
ER in bits rms =
ER in Vrms =
20•log
PGA
ER in Vrms
6.02
10V
PGA
6.02• ER in bits rms +1.76
10
20
−1.76
The 10V figure in each calculation represents the full-scale
range of the ADS1210/11 in a gain setting of 1. This means
that both units are absolute expressions of resolution—the
performance in different configurations can be directly compared regardless of the units. Comparing the resolution of
different gain settings expressed in bits rms requires accounting for the PGA setting.
Main Controller—A generic term for the external
microcontroller, microprocessor, or digital signal processor
which is controlling the operation of the ADS1210/11 and
receiving the output data.
10
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ADS1210, ADS1211
SBAS034B
—The frequency of the crystal oscillator or CMOS
FILTER RESPONSE
Frequency (Hz)
–40
–60
–80
–100
–120
–140
–160
55 56 57 58 59 60 61 62 63 64 65
FILTER RESPONSE
Frequency (Hz)
0
–20
–40
–60
–80
–100
–120
–140
–160
0 50 100 150 200 250 300
Gain (dB) Gain (dB)
f
XIN
compatible input signal at the XIN input of the ADS1210/11.
f
—The frequency or speed at which the modulator of the
MOD
ADS1210/11 is running, given by the following equation:
f
•Turbo Mode
f
MOD
f
—The frequency or switching speed of the input
SAMP
XIN
=
512
sampling capacitor. The value is given by the following
equation:
f
•Turbo Mode • Gain Setting
XIN
=
512
—The frequency of the digital output data
f
DATA
, t
f
SAMP
DATA
produced by the ADS1210/11 or the inverse of this (the
period), respectively, f
f
f
DATA
=
XIN
512• Decimation Ratio +1
()
is also referred to as the data rate.
DATA
•Turbo Mode
,t
DATA
1
=
f
DATA
Conversion Cycle—The term “conversion cycle” usually
refers to a discrete A/D conversion operation, such as that
performed by a successive approximation converter. As
used here, a conversion cycle refers to the t
time period.
DATA
However, each digital output is actually based on the modulator results from the last three t
time periods.
DATA
DIGITAL FILTER
The digital filter of the ADS1210/11 computes the output
result based on the most recent results from the delta-sigma
modulator. The number of modulator results that are used
depend on the decimation ratio set in the Command Register. At the most basic level, the digital filter can be thought
of as simply averaging the modulator results and presenting
this average as the digital output.
While the decimation ratio determines the number of modulator results to use, the modulator runs faster at higher Turbo
Modes. These two items, together with the ADS1210/11
clock frequency, determine the output data rate:
0
–20
–40
–60
–80
Gain (dB)
–100
–120
–140
–160
NORMALIZED DIGITAL FILTER RESPONSE
0123456
Frequency (Hz)
FIGURE 1. Normalized Digital Filter Response.
0
–20
–40
–60
–80
–100
Gain (dB)
–120
–140
–160
0 50 100 150 200 250 300
–40
–60
–80
–100
Gain (dB)
–120
–140
–160
45 46 47 48 49 50 51 52 53 54 55
FILTER RESPONSE
Frequency (Hz)
FILTER RESPONSE
Frequency (Hz)
FIGURE 2. Digital Filter Response at a Data Rate of 50Hz.
•Turbo Mode
f
f
DATA
=
XIN
512• Decimation Ratio +1
()
Also, since the conversion result is essentially an average,
the data rate determines where the resulting notches are in
the digital filter. For example, if the output data rate is 1kHz,
then a 1kHz input frequency will average to zero during the
1ms conversion cycle. Likewise, a 2kHz input frequency
will average to zero, etc.
In this manner, the data rate can be used to set specific notch
frequencies in the digital filter response (see Figure 1 for the
normalized response of the digital filter). For example, if the
rejection of power line frequencies is desired, then the data
rate can simply be set to the power line frequency. Figures
2 and 3 show the digital filter response for a data rate of
50Hz and 60Hz, respectively.
ADS1210, ADS1211
SBAS034B
FIGURE 3. Digital Filter Response at a Data Rate of 60Hz.
If the effective resolution at a 50Hz or 60Hz data rate is not
adequate for the particular application, then power line frequencies could still be rejected by operating the ADS1210/11
at 25/30Hz, 16.7/20Hz, 12.5/15Hz, etc. If a higher data rate
is needed, then power line frequencies must either be rejected
before conversion (with an analog notch filter) or after
conversion (with a digital notch filter running on the main
controller).
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11
Filter Equation
The digital filter is described by the following transfer
function:
3
|H(f)|=
sin
N •sin
π•f •N
f
MOD
π•f
f
MOD
where N is the Decimation Ratio.
This filter has a (sin(x)/x)
3
response and is referred to a sinc
filter. For the ADS1210/11, this type of filter allows the data
rate to be changed over a very wide range (nearly four orders
of magnitude). However, the –3dB point of the filter is 0.262
times the data rate. And, as can be seen in Figures 1 and 2,
the rejection in the stopband (frequencies higher than the
first notch frequency) may only be –40dB.
These factors must be considered in the overall system
design. For example, with a 50Hz data rate, a significant
signal at 75Hz may alias back into the passband at 25Hz.
The analog front end can be designed to provide the needed
attenuation to prevent aliasing, or the system may simply
provide this inherently. Another possibility is increasing the
data rate and then post filtering with a digital filter on the
main controller.
Filter Settling
The number of modulator results used to compute each
conversion result is three times the Decimation Ratio. This
means that any step change (or any channel change for the
ADS1211) will require at least three conversions to fully
settle. However, if the change occurs asynchronously, then at
least four conversions are required to ensure complete settling. For example, on the ADS1211, the fourth conversion
result after a channel change will be valid (see Figure 4).
Significant Analog Input Change
ADS1211 Channel Change
Valid
Data
DRDY
or
Valid
Data
Data
not
Valid
Data
not
Valid
Data
not
Valid
Valid
Data
Valid
Data
the effective resolution of the output data at a given data rate,
but there is also an increase in power dissipation. For Turbo
Mode Rates 2 and 4, the increase is slight. For rates 8 and
16, the increase is more substantial. See the Typical Performance Curves for more information.
In a Turbo Mode Rate of 16, the ADS1210/11 can offer 20
bits of effective resolution at a 1kHz data rate. A comparison
of effective resolution versus Turbo Mode Rates and output
data rates is shown in Table IV while Table V shows the
corresponding noise level in µVrms.
3
DATA TURBO TURBO TURBO TURBO TURBO
RATE MODE MODE MODE MODE MODE
(HZ) RATE 1 RATE 2 RATE 4 RATE 8 RATE 16
10 21.5 22.0 22.5
20 21.0 22.0 22.0 22.5
40 20.0 21.5 22.0 22.5 23.0
50 20.0 21.5 21.5 22.0 23.0
60 19.5 21.0 21.5 22.0 23.0
100 18.0 20.0 21.0 21.5 22.5
1000 10.0 12.5 15.0 17.5 20.0
EFFECTIVE RESOLUTION (BITS RMS)
TABLE IV. Effective Resolution vs Data Rate and Turbo Mode
Rate. (Gain setting of 1 and 10MHz clock.)
NOISE LEVEL (µVrms)
DATA TURBO TURBO TURBO TURBO TURBO
RATE MODE MODE MODE MODE MODE
(Hz) RATE 1 RATE 2 RATE 4 RATE 8 RATE 16
10 2.9 1.7 1.3
20 4.3 2.1 1.7 1.3
40 6.9 3.0 2.3 1.6 1.0
50 8.1 3.2 2.4 1.8 1.0
60 10.5 3.9 2.6 1.9 1.0
100 26.9 6.9 3.5 2.7 1.4
1000 6909.7 1354.5 238.4 46.6 7.8
TABLE V. Noise Level vs Data Rate and Turbo Mode Rate.
(Gain setting of 1 and 10MHz clock.)
The Turbo Mode feature allows trade-offs to be made
between the ADS1210/11 XIN clock frequency, power dissipation, and effective resolution. If a 5MHz clock is available
but a 10MHz clock is needed to achieve the desired performance, a Turbo Mode Rate of 2X will result in the same
effective resolution. Table VI provides a comparison of
effective resolution at various clock frequencies, data rates,
and Turbo Mode Rates.
Serial
I/O
t
DATA
FIGURE 4. Asynchronous ADS1210/11 Analog Input Volt-
age Step or ADS1211 Channel Change to Fully
Settled Output Data.
TURBO MODE
The ADS1210/11 offers a unique Turbo Mode feature which
can be used to increase the modulator sampling rate by 2, 4,
8, or 16 times normal. With the increase of modulator
sampling frequency, there can be a substantial increase in
12
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DATA XIN CLOCK TURBO EFFECTIVE
RATE FREQUENCY MODE RESOLUTION
(Hz) (MHz) RATE (Bits rms)
60 10 1 19.5
60 5 2 19.5
60 2.5 4 19.5
60 1.25 8 19.5
60 0.625 16 19.5
100 10 1 18.0
100 5 2 18.0
100 2.5 4 18.0
100 1.25 8 18.0
100 0.625 16 18.0
TABLE VI. Effective Resolution vs Data Rate, Clock
Frequency, and Turbo Mode Rate. (Gain setting of 1.)
ADS1210, ADS1211
SBAS034B
The Turbo Mode Rate (TMR) is programmed via the Sampling Frequency bits of the Command Register. Due to the
increase in input capacitor sampling frequency, higher Turbo
Mode settings result in lower analog input impedance;
AIN Impedance (Ω) = (10MHz/f
)•4.3E6/(G•TMR)
XIN
where G is the gain setting. Because the modulator rate also
changes in direct relation to the Turbo Mode setting, higher
values result in a lower impedance for the REF
REFIN Impedance (Ω) = (10MHz/f
XIN
input:
IN
)•1E6/TMR
The Turbo Mode Rate can be set to 1, 2, 4, 8, or 16. Consult
the graphs shown in the Typical Performance Curves for full
details on the performance of the ADS1210/11 operating in
different Turbo Mode Rates. Keep in mind that higher Turbo
Mode Rates result in fewer available gain settings as shown
in Table II.
PROGRAMMABLE GAIN AMPLIFIER
The programmable gain amplifier gain setting is programmed
via the PGA Gain bits of the Command Register. Changes
in the gain setting (G) of the programmable gain amplifier
results in an increase in the input capacitor sampling frequency. Thus, higher gain settings result in a lower analog
input impedance:
AIN Impedance (Ω) = (10MHz/f
)•4.3E6/(G•TMR)
XIN
where TMR is the Turbo Mode Rate. Because the modulator
speed does not depend on the gain setting, the input impedance seen at REFIN does not change.
The PGA can be set to gains of 1, 2, 4, 8, or 16. These gain
settings with their resulting full-scale range and typical
voltage range are shown in Table I. Keep in mind that higher
Turbo Mode Rates result in fewer available gain settings as
shown in Table II.
SOFTWARE GAIN
The excellent performance, flexibility, and low cost of the
ADS1210/11 allow the converter to be considered for designs which would not normally need a 24-bit ADC. For
example, many designs utilize a 12-bit converter and a highgain INA or PGA for digitizing low amplitude signals. For
some of these cases, the ADS1210/11 by itself may be a
solution, even though the maximum gain is limited to 16.
To get around the gain limitation, the digital result can
simply be shifted up by “n” bits in the main controller—
resulting in a gain of “n” times G, where G is the gain
setting. While this type of manipulation of the output data
is obvious, it is easy to miss how much the gain can be
increased in this manner on a 24-bit converter.
For example, shifting the result up by three bits when the
ADS1210/11 is set to a gain of 16 results in an effective gain
of 128. At lower data rates, the converter can easily provide
more than 12 bits of resolution. Even higher gains are
possible. The limitation is a combination of the needed data
rate, desired noise performance, and desired linearity.
CALIBRATION
The ADS1210/11 offers several different types of calibration, and the particular calibration desired is programmed
via the Command Register. In the case of Background
Calibration, the calibration will repeat at regular intervals
indefinitely. For all others, the calibration is performed once
and then normal operation is resumed.
Each type of calibration is covered in detail in its respective
section. In general, calibration is recommended immediately
after power-on and whenever there is a “significant” change
in the operating environment. The amount of change which
should cause a re-calibration is dependent on the application, effective resolution, etc. Where high accuracy is important, re-calibration should be done on changes in temperature and power supply. In all cases, re-calibration should be
done when the gain, Turbo Mode, or data rate is changed.
After a calibration has been accomplished, the Offset Calibration Register and the Full-Scale Calibration Register
contain the results of the calibration. The data in these
registers are accurate to the effective resolution of the
ADS1210/11’s mode of operation during the calibration.
Thus, these values will show a variation (or noise) equivalent to a regular conversion result.
For those cases where this error must be reduced, it is
tempting to consider running the calibration at a slower data
rate and then increasing the converter’s data rate after the
calibration is complete. Unfortunately, this will not work as
expected. The reason is that the results calculated at the
slower data rate would not be valid for the higher data rate.
Instead, the calibration should be done repeatedly. After
each calibration, the results can be read and stored. After the
desired number of calibrations, the main controller can
compute an average and write this value into the calibration
registers. The resulting error in the calibration values will be
reduced by the square root of the number of calibrations
which were averaged.
The calibration registers can also be used to provide system
offset and gain corrections separate from those computed by
the ADS1210/11. For example, these might be burned into
E2PROM during final product testing. On power-on, the
main controller would load these values into the calibration
registers. A further possibility is a look-up table based on the
current temperature.
Note that the values in the calibration registers will vary from
configuration to configuration and from part to part. There is
no method of reliably computing what a particular calibration
register should be to correct for a given amount of system
error. It is possible to present the ADS1210/11 with a known
amount of error, perform a calibration, read the desired
calibration register, change the error value, perform another
calibration, read the new value and use these values to
interpolate an intermediate value.
ADS1210, ADS1211
SBAS034B
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13
Normal
Mode
Valid
Data
DRDY
Serial
I/O
t
DATA
Valid
Data
SC
(1)
NOTES: (1) SC = Self-Calibration instruction. (2) In Slave Mode, this function requires 4 cycles.
FIGURE 5. Self-Calibration Timing.
Offset
Calibration on
Internal Offset
Self-Calibration
Mode
Full-Scale
(2)
Calibration on
Internal Full-Scale
Analog
Input
Conversion
Normal
Mode
Valid
Data
Valid
Data
Self-Calibration
A self-calibration is performed after the bits 001 have been
written to the Command Register Operation Mode bits
(MD2 through MD0). This initiates the following sequence
at the start of the next conversion cycle (see Figure 5). The
DRDY signal will not go LOW but will remain HIGH and
will continue to remain HIGH throughout the calibration
sequence. The inputs to the sampling capacitor are disconnected from the converter’s analog inputs and are shorted
together. An offset calibration is performed over the next
three conversion periods (four in Slave Mode). Then, the
input to the sampling capacitor is connected across REFIN,
and a full-scale calibration is performed over the next three
conversions.
After this, the Operation Mode bits are reset to 000 (normal
mode) and the input capacitor is reconnected to the input.
Conversions proceed as usual over the next three cycles in
order to fill the digital filter. DRDY remains HIGH during
this time. On the start of the fourth cycle, DRDY goes LOW
indicating valid data and resumption of normal operation.
System Offset Calibration
A system offset calibration is performed after the bits 010
have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 6). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The offset calibration will be performed on the differential input voltage present at the
converter’s input over the next three conversion periods
(four in Slave Mode). When this is done, the Operation
Mode bits are reset to 000 (Normal Mode). A single conversion is done with DRDY HIGH. After this conversion, the
DRDY signal goes LOW indicating resumption of normal
operation.
Normal operation returns within a single conversion cycle
because it is assumed that the input voltage at the converter’s
input is not removed immediately after the offset calibration
is performed. In this case, the digital filter already contains
a valid result.
For full system calibration, offset calibration must be performed first and then full-scale calibration. In addition, the
offset calibration error will be the rms sum of the conversion
error and the noise on the system offset voltage. See the
System Calibration Limits section for information regarding
the limits on the magnitude of the system offset voltage.
System Full-Scale Calibration
A system full-scale calibration is performed after the bits
011 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 7). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The full-scale calibration will be performed on the differential input voltage (2 • REFIN/G)
present at the converter’s input over the next three conversion periods (four in Slave Mode). When this is done, the
Operation Mode bits are reset to 000 (Normal Mode). A
single conversion is done with DRDY HIGH. After this
conversion, the DRDY signal goes LOW indicating resumption of normal operation.
DRDY
Serial
I/O
Valid
Data
t
DATA
Normal
Mode
Valid
Data
(1)
SOC
NOTES: (1) SOC = System Offset Calibration instruction.
(2) In Slave Mode, this function requires 4 cycles.
System Offset
Calibration Mode
Offset
Calibration on
System Offset
Analog
Input
(2)
Conversion
FIGURE 6. System Offset Calibration Timing.
14
Normal
Mode
Possibly
Valid
Data
Possibly
Valid
Data
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DRDY
Serial
I/O
Normal
Mode
Valid
Valid
Data
Data
(1)
SFSC
t
DATA
NOTES: (1) SFSC = System Full-Scale Calibration instruction.
(2) In Slave Mode, this function requires 4 cycles.
System Full-Scale
Calibration Mode
Full-Scale
Calibration on
System Full-Scale
(2)
Analog
Input
Conversion
Normal
Mode
Possibly
Valid
Data
FIGURE 7. System Full-Scale Calibration Timing.
ADS1210, ADS1211
SBAS034B
Possibly
Valid
Data
Normal operation returns within a single conversion cycle
because it is assumed that the input voltage at the converter’s
input is not removed immediately after the full-scale calibration is performed. In this case, the digital filter already
contains a valid result.
For full system calibration, offset calibration must be performed first and then full-scale calibration. The calibration
error will be a sum of the rms noise on the conversion result
and the input signal noise. See the System Calibration Limits
section for information regarding the limits on the magnitude of the system full-scale voltage.
Pseudo System Calibration
The Pseudo System Calibration is performed after the bits
100 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 8). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The offset calibration will be performed
on the differential input voltage present at the converter’s
input over the next three conversion periods (four in Slave
Mode). Then, the input to the sampling capacitor is disconnected from the converter’s analog input and connected
across REF
. A gain calibration is performed over the next
IN
three conversions.
After this, the Operation Mode bits are reset to 000 (normal
mode) and the input capacitor is then reconnected to the
input. Conversions proceed as usual over the next three
cycles in order to fill the digital filter. DRDY remains
HIGH during this time. On the next cycle, the DRDY signal
goes LOW indicating valid data and resumption of normal
operation.
The system offset calibration range of the ADS1210/11
is limited and is listed in the Specifications Table. For
more information on how to use these specifications, see
the System Calibration Limits section. To calculate V
OS
use 2 • REFIN/ GAIN for VFS.
Background Calibration
The Background Calibration Mode is entered after the bits
101 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
continuous sequence (see Figure 9). At the start of the next
conversion cycle, the DRDY signal will not go LOW but
will remain HIGH. The inputs to the sampling capacitor are
disconnected from the converter’s analog input and shorted
together. An offset calibration is performed over the next
three conversion periods (in Slave Mode, the very first offset
calibration requires four periods and all subsequent offset
calibrations require three periods). Then, the input capacitor
is reconnected to the input. Conversions proceed as usual
over the next three cycles in order to fill the digital filter.
DRDY remains HIGH during this time. On the next cycle,
the DRDY signal goes LOW indicating valid data.
,
Normal
Mode
Offset
Calibration on
System Offset
DRDY
Serial
I/O
Valid
Data
t
DATA
Valid
Data
(1)
PSC
NOTES: (1) PSC = Pseudo System Calibration instruction. (2) In Slave Mode, this function requires 4 cycles.
FIGURE 8. Pseudo System Calibration Timing.
DRDY
Serial
I/O
Valid
Data
t
DATA
Normal
Background Calibration
Mode
Mode
Valid
Data
(1)
BC
Offset
Calibration on
Internal Offset
(2)
NOTES: (1) BC = Background Calibration instruction. (2) In Slave Mode, the very first offset
calibration will require 4 cycles. All subsequent offset calibrations will require 3 cycles.
(2)
Analog
Input
Conversion
Pseudo System
Calibration Mode
Full-Scale
Calibration on
Internal Full-Scale
Full-Scale
Calibration on
Internal Full-Scale
Analog
Input
Conversion
Analog
Conversion
Input
Normal
Mode
Valid
Data
Valid
Data
Cycle Repeats
with Offset
Calibration
FIGURE 9. Background Calibration Timing.
ADS1210, ADS1211
SBAS034B
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15
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