Page 1
查询BS62UV2006STCG10供应商
Ultra Low Power/Voltage CMOS SRAM
BSI
256K X 8 bit
BS62UV2006
FEATURES
• Wide Vcc operation voltage :
C-grade: 1.8V~3.6V
I-grade: 1.9V~3.6V
(Vcc_min.=1.65V at 25oC)
• Ultra low power consumption :
Vcc = 2.0V C-grade : 8mA (Max.) operating current
I- grade : 10mA (Max.) operating current
0.20uA (Typ.) CMOS standby current
Vcc = 3.0V C-grade : 11mA (Max.) operating current
I- grade : 13mA (Max.) operating current
0.30uA (Typ.) CMOS standby current
• High speed access time :
-85 85ns (Max.)
-10 100ns (Max.)
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.0V
• Easy expansion with CE2, CE1, and OE options
DESCRIPTION
The BS62UV2006 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.2uA at 2.0V /25
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62UV2006 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62UV2006 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP.
o
C and maximum access time of 85ns at 85oC.
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
C-grade:1.8~3.6V
I-grade:1.9~3.6V
Vcc=3.0V Vcc=3.0V
BS62UV2006DC DICE
BS62UV2006TC TSOP-32
BS62UV2006STC STSOP-32
+0O C to +70O C 1.8V ~3.6V 85/100
3.0uA
BS62UV2006SC
BS62UV2006DI DICE
BS62UV2006TI TSOP-32
BS62UV2006STI STSOP-32
-40O C to +85O C 1.9V ~ 3.6V 85/100
5.0uA
BS62UV2006SI
POWER DISSIPATION
STANDBY
CCSB1
( I
, Max )
Vcc=2.0V
2.0uA
3.0uA
Operating
( ICC, Max )
11mA
13mA
PKG TYPE
Vcc=2.0V
8mA
SOP-32
10mA
SOP-32
PIN CONFIGURATIONS
•
1
A11
2
A9
3
A8
4
A13
5
WE
6
CE2
VCC
A15
A17
A16
A14
A12
A7
A6
A5
A4
DQ0
DQ1
DQ2
GND
A17
A16
A14
A12
7
8
9
10
11
12
13
14
15
16
A7
A6
A5
A4
A3
A2
A1
A0
BS62UV2006TC
BS62UV2006STC
BS62UV2006TI
BS62UV2006STI
•
1
2
3
4
5
6
7
BS62UV2006SC
BS62UV2006SI
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
BLOCK DIAGRAM
A13
A17
A15
Address
A16
A14
A12
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
Vdd
Gnd
A7
Buffer
A6
A5
A4
WE
OE
OE
Input
20
8
8
Control
Decoder
Data
Input
Buffer
Data
Output
Buffer
Row
1024
8
8
A11
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS62UV2006
1
Memory Array
1024 x 2048
2048
Column I/O
Write Driver
Sense Amp
256
Column Decoder
16
Address Input Buffer
A8 A3 A2 A1 A10
A9
Revision 1.1
Jan. 2004
A0
Page 2
BSI
PIN DESCRIPTIONS
Name Function
BS62UV2006
A0-A17 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
DQ0-DQ7 Data Input/Output
These 18 address inputs select one of the 262,144 x 8-bit words in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
Ports
Vcc
Gnd
Power Supply
Ground
TRUTH TABLE
MODE WE CE1 CE2 OE I/O OPERATION Vcc CURRENT
Not selected
(Power Down)
Output Disabled H L H H High Z I
Read H L H L D
Write L L H X D
XHXX
XXLX
High Z I
OUT
IN
CCSB
, I
CCSB1
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL PARAMETER RATING UNITS
VTERM
TBIAS
T
STG
P
T
IOUT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
R0201-BS62UV2006
Terminal Voltage with
Respect to GND
Temperature Under Bias -40 to +85
Storage Temperature -60 to +150
Power Dissipation 1.0 W
DC Output Current 20 mA
-0.5 to
Vcc+0.5
OPERATING RANGE
RANGE
V
O
C
O
C
Commercial 0
Industrial -40
CAPACITANCE
SYMBOL PARAMETER CONDITIONS UNITMAX.
C
C
1. This parameter is guaranteed and not 100% tested.
IN
DQ
Input
Capacitance
Input/Output
Capacitance
2
AMBIENT
TEMPERATURE
O
O
(1)
(TA = 25oC, f = 1.0 MHz)
O
C to +70
C to +85
C 1.8V ~ 3.6V
O
C 1.9V ~ 3.6V
VIN=0V 6 pF
I/O
V
=0V 8 pF
Vcc
Revision 1.1
Jan. 2004
Page 3
BSI
BS62UV2006
DC ELECTRICAL CHARACTERISTICS ( TA = -40
PAR AMETE R
NAME
IL
V
IH
V
IL
I
Input Leakage Current Vcc = Max, V
ILO Output Leakage Current
VOL Output Low Voltage
VOH Output High Voltage
ICC
CCSB
I
Standby Current-TTL
(4)
CCSB1
I
Standby Current-CMOS
1. Typical characteristics are at TA = 25oC.
PAR AMET E R TEST CONDITIONS MIN. TYP.
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
Voltage
Operating Power Supply
Current
(2)
Vcc = Max, CE1 = V
or OE = V
Vcc = Max, IOL = 0.1mA
Vcc = Max, I
Vcc = Min, IOH = -0.1mA
Vcc = Min, I
Vcc = Max, CE1= V
DQ
= 0mA, F = Fmax
I
Vcc = Max, CE1 = V
CE2=V
DQ
= 0mA
I
Vcc = Max, CE1≧Vcc-0.2V or
CE2≦0.2V ;V
IN
V
≦0.2V
o
C to + 85oC )
(1)
MAX.
IN
= 0V to Vcc -- -- 1 uA
IH
IH
, V
or CE2=VIL
I/O
= 0V to Vcc
OL
= 2.0mA
OH
= -1.0mA
IL
, CE2=VIH
(3)
IH
IL
or
IN
≧ Vcc - 0.2V or
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
-0.3
1.4 --
2.0 --
-- -- 1 uA
-- -- 0.2
-- -- 0.4
Vcc-0.2 -- --
2.4 -- --
-- -- 10
-- -- 13
-- -- 0.1
-- -- 0.5
-- 0.20 3.0
-- 0.30 5.0
-- 0.6
(5)
-- 0.8
Vcc+0.3 V
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
DATA RETENTION CHARACTERISTICS ( TA = -40
SYMBOL PAR AMETE R TEST CONDITIONS MIN. TYP.
V
I
CCDR
t
CDR
1. Vcc = 1.0V, TA= + 25OC
= Read Cycle Time
2. t
RC
ccDR is 0.7uA at TA=70
3. I
LOW V
Vcc
CE1
. 4. IccsB1 is 2.0uA/3.0uA at Vcc=2.0V/3.0V and TA=70oC. 5. VIL = -1.5V for pulse width less than 30ns.
RC
o
C to + 85oC )
DR
t
R
Vcc for Data Retention
(3)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
o
C.
DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
CC
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
IN
V
≧ Vcc - 0.2V or VIN ≦ 0.2V
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,
IN
≧ Vcc - 0.2V or VIN ≦ 0.2V
V
See Retention Waveform
Data Retention Mode
≥
Vcc
VDR 1.0V
t CDR
≥
CE1 Vcc - 0.2V
1.0 -- -- V
-- 0.1 1.0 uA
0 -- -- ns
(2)
T
RC
Vcc
-- -- ns
t R
VIHVIH
(1)
MAX. UNITS
UNITS
V
V
V
mA
mA
uA
LOW V
DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
CC
Vcc
CE2
R0201-BS62UV2006
Data Retention Mode
Vcc
VDR ≧ 1.0V
t CDR
VIL
CE2 ≦ 0.2V
3
Vcc
t R
VIL
Revision 1.1
Jan. 2004
Page 4
BSI
BS62UV2006
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
Vcc / 0V
1V/ns
0.5Vcc
CL = 100pF+1TTL
= 30pF+1TTL
C
L
AC ELECTRICAL CHARACTERISTICS ( TA = -40
READ CYCLE
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
o
C to + 85oC)
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
E1LQV
t
E2HOV
t
GLQV
t
E1LQX
t
E2HOX
t
GLQX
t
E1HQZ
t
E2HQZ
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ2
t
OHZ
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Data Hold from Address Change
(CE1)
(CE2)
(CE1)
(CE2)
(CE1)
(CE2)
CYCLE TIME : 100ns
(Vcc = 1.9~3.6V)
MIN. TYP. MAX.
CYCLE TIME : 85ns
(Vcc = 1.9~3.6V)
MIN. TYP. MAX.
UNIT
100----85---- ns
-- -- 100 -- --
85
ns
-- -- 100 -- -- 85 ns
-- --
-- -- 85 ns
100
-- -- 45 -- -- 40 ns
15 -- -- 15 -- -- ns
15 -- -- 15 -- -- ns
15 -- -- 10 -- -- ns
-- -- 40 -- -- 35 ns
-- -- 40 -- -- 35 ns
-- -- 35 -- -- 30 ns
15 -- -- 15 -- -- ns
R0201-BS62UV2006
4
Revision 1.1
Jan. 2004
Page 5
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
ADDRESS
D
(1,2,4)
t AA
t OH
OUT
BS62UV2006
t RC
t OH
READ CYCLE2
CE1
CE2
D
OUT
READ CYCLE3
ADDRESS
OE
CE1
(1,3,4)
(1,4)
t CLZ
(5)
t ACS1
t ACS2
t CLZ1
(5)
t AA
t ACS1
t OLZ
t OE
t RC
(5)
t CHZ1, t CHZ2
t OH
(5)
t OHZ
(1,5)
t CHZ1
CE2
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = V
5. The parameter is guaranteed but not 100% tested.
R0201-BS62UV2006
IL .
t ACS2
(5)
t CLZ2
IL and CE2= VIH.
5
(2,5)
t CHZ2
Revision 1.1
Jan. 2004
Page 6
BSI
BS62UV2006
AC ELECTRICAL CHARACTERISTICS ( TA = -40
WRITE CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
E1LWH
t
AVWL
t
AVWH
t
WLWH
t
WHAX
t
E2LAX
t
WLQZ
t
DVWH
t
WHDX
t
GHQZ
t
WHOX
PARAMETER
NAME
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR1
t
WR2
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
DESCRIPTION
Write Cycle Time
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write recovery Time
Write recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
o
C to + 85oC )
CYCLE TIME : 100ns
(Vcc = 1.9~3.6V)
MIN. TYP. MAX.
100----85---- ns
100----85---- ns
0 -- -- 0 -- -- ns
100
-- -- 85 -- -- ns
50 -- -- 40 -- -- ns
(CE1,WE)
(CE2) 0 -- -- 0 -- -- ns
0 -- -- 0 -- -- ns
-- -- 40 -- -- 35 ns
40 -- -- 35 -- -- ns
0 -- -- 0 -- -- ns
-- -- 40 -- -- 35 ns
10 -- -- 10 -- -- ns
CYCLE TIME : 85ns
(Vcc = 1.9~3.6V)
MIN. TYP. MAX.
t WC
UNIT
ADDRESS
OE
CE1
CE2
WE
D
OUT
D
IN
R0201-BS62UV2006
t AS
(4,10)
t OHZ
(3)
t WR1
(11)
(5)
(5)
t AW
t CW
t CW
t WP
(11)
(2)
t WR2
(3)
t DH
t DW
6
Revision 1.1
Jan. 2004
Page 7
BSI
BS62UV2006
WRITE CYCLE2
ADDRESS
CE1
CE2
WE
D
OUT
D
IN
(1,6)
t AS
(5)
(5)
(4,10)
t WHZ
t AW
t WC
t CW
t CW
t WP
(11)
(11)
t WR2
(3)
(2)
t OW
(7) (8)
t DW
t DH
(8,9)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. T
WR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
7.
DOUT is the same phase of write data of this write cycle.
8. D
OUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. T
CW is measured from the later of CE1 going low or CE2 going high to the end of write.
R0201-BS62UV2006
IL ).
7
Revision 1.1
Jan. 2004
Page 8
BSI
BS62UV2006
ORDERING INFORMATION
BS62UV2006 X X Z Y Y
SPEED
85: 85ns
10: 100ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
o
C ~ +70oC
C: +0
o
I: -40
C ~ +85oC
PACKAGE
S: SOP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
D: DICE
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
STSOP - 32
R0201-BS62UV2006
8
Revision 1.1
Jan. 2004
Page 9
BSI
PACKAGE DIMENSIONS (continued)
BS62UV2006
TSOP - 32
SOP -32
WITH PLATING
c c1
BASE METAL
b
b1
SECTION A-A
R0201-BS62UV2006
9
Revision 1.1
Jan. 2004
Page 10
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