BSI BS62LV1600 User Manual

Very Low Power CMOS SRAM

R0201

-BS62LV1600

Revision

2.2

A4A3A2A1A0

CE1NCNC

DQ0

DQ1

VCC

VSS

DQ2

DQ3NCA20WEA19

A18

A17

A16

A15

BS62LV1600EI

44342414039383736353433323130292827262524

23A5 A6 A7 OE

A8 NC NC

NC NC A9

H F E D C B A 1 2 3 4 5 6 A9

WE NC NC NC

A7

NC A5 OE A3 A0 A6 A4 A1 A2

NC NC NC

NC

NC

NC

A8

Write Driver

Sense Amp

Address Input Buffer

A0

A10

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

A20A13

A17

A15

A18

A16

A14

A12A7A6A5A4

8

89

12

2M X 8 bit

Pb-Free and Green package materials are compliant to RoHS

BS62LV1600

n FEATURES

Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V
Ÿ Very low power consumption :

VCC = 3.0V Operation current : 46mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 1.5uA (Typ.) at 25 OC
VCC = 5.0V Operation current : 115mA (Max.) at 55ns
10mA (Max.) at 1MHz
Standby current : 6.0uA (Typ.) at 25OC

Ÿ High speed access time :

-55 55ns (Max.) at VCC : 3.0~5.5V

-70 70ns (Max.) at VCC : 2.7~5.5V

Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE1, CE2 and OE options
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation
Ÿ Data retention supply voltage as low as 1.5V

n DESCRIPTION

The BS62LV1600 is a high performance, very low power CMOS
Static Random Access Memory organized as 2048K by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 1.5uA at 3.0V/25OC and maximum access time of 55ns at

3.0V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2), and active LOW output
enable (OE) and three-state output drivers.
The BS62LV1600 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV1600 is available in JEDEC standard 44-pin TSOP II
and 48-ball BGA package.

n POWER CONSUMPTION

POWER DISSIPATION

PRODUCT

FAMILY

BS62LV1600EC
BS62LV1600FC
BS62LV1600EI TSOP II-44
BS62LV1600FI

OPERATING

TEMPERATURE

Commercial

+0OC to +70OC

Industrial

-40OC to +85OC

STANDBY

(I

, Max)

CCSB1

VCC=5.0V VCC=3.0V

1MHz 10MHz f

VCC=5.0V VCC=3.0V

50uA 8.0uA 9mA 48mA 113mA 1.5mA 19mA 45mA

100uA 16uA 10mA 50mA 115mA 2mA 20mA 46mA

Operating

(ICC, Max)

1MHz 10MHz

Max.

f

Max.

PKG TYPE

TSOP II-44
BGA-48-0912

BGA-48-0912

n PIN CONFIGURATIONS

1
2
3
4
5
6
7
8
9
10

BS62LV1600EC

11
12
13
14
15
16
17
18
19
20
21
22

NC

DQ0

VSS

DQ1

A17

CE1

DQ5

4

CE2

DQ7
DQ6
VSS
VCC
DQ5
DQ4

A10
A11
A12
A13
A14

CE2

DQ4

VCC

n BLOCK DIAGRAM

Address

Input

Buffer

8

8

CE1
CE2

WE

V

OE

CC

V

SS

Control

Decoder

Data
Input

Buffer

Data

Output

Buffer

Row

4096

Memory Array

4096 x 4096

Column I/O

Column Decoder

A8 A2A1

A9A11

A3

4096

512

A19

A14

A12

A16

A15

A13

A10

DQ2

VCC

DQ3

G

A20

A18

48-ball BGA top view

DQ6

A11

VSS

DQ7

A19

Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.

1

Jan. 2006

BS6

2L

V

1600

R0201

-BS62LV1600 Rev

ision 2.3

. With the

selected and the write enable is inactive, data will be present on the DQ pins and they

n PIN DESCRIPTIONS

Name Function

A0-A20 Address Input

CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input

WE Write Enable Input

OE Output Enable Input

DQ0-DQ7 Data Input/Output
Ports
VCC

VSS

n TRUTH TABLE

MODE

Not selected

(Power Down)

These 21 address inputs select one of the 2048K x 8-bit in the RAM

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read form or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
The write enable input is active LOW and controls read and write operations
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is

will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
There 8 bi-directional ports are used to read data from or write data into the RAM.

Power Supply

Ground

CE1

H X X X
X L X X

CE2

WE

OE

I/O OPERATION VCC CURRENT

High Z I

CCSB

, I

CCSB1

Output Disabled L H H H High Z ICC

Read L H H L D
Write L H L X DIN ICC

n ABSOLUTE MAXIMUM RATINGS

(1)

SYMBOL

V

TERM

T

BIAS

T

Storage Temperature -60 to +150

STG

PT Power Dissipation 1.0 W

I

DC Output Current 20 mA

OUT

PARAMETER RATING UNITS

Terminal Voltage with
Respect to GND

Temperature Under
Bias

(2)

-0.5

to 7.0

-40 to +125

1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

2. –2.0V in case of AC pulse width less than 30 ns.

ICC

OUT

n OPERATING RANGE

RANG

V

O

C

O

C

Commercial 0OC to + 70OC 2.4V ~ 5.5V

Industrial -40OC to + 85OC 2.4V ~ 5.5V

n CAPACITANCE

AMBIENT

TEMPERATURE

(1)

(TA = 25OC, f = 1.0MHz)

VCC

SYMBOL PAMAMETER CONDITIONS MAX. UNITS

CIN

CIO

Input
Capacitance

Input/Output
Capacitance

VIN = 0V 10 pF

V

= 0V 12 pF

I/O

1. This parameter is guaranteed and not 100% tested.

2

May. 2006

BS6

2L

V

1600

R0201

-BS62LV1600 Rev

ision 2.3

Data Retention Mode

V

CC

t

CDR

V

CC

n DC ELECTRICAL CHARACTERISTICS (TA =-40OC to +85OC)

PARAMETER

NAME

VCC Power Supply 2.4 -- 5.5 V

PARAMETER TEST CONDITIONS MIN. TYP.

(1)

MAX. UNITS

VIL Input Low Voltage -0.5

VIH Input High Voltage 2.2 -- V

IIL Input Leakage Current V

ILO Output Leakage Current

VOL Output Low Voltage V

VOH Output High Voltage V

(5)

I

CC

I

CC1

I

CCSB

I

CCSB1

1. Typical characteristics are at TA=25OC and not 100% tested.

2. Undershoot: -1.0V in case of pulse width less than 20 ns.

3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.

Operating Power Supply
Current

Operating Power Supply
Current

Standby Current – TTL

(6)

Standby Current – CMOS

= 0V to VCC -- -- 1 uA

IN

V

= 0V to V

I/O

,

CC

CE1= VIH or CE2= VIL, or OE = VIH

= Max, IOL = 2.0mA -- -- 0.4 V

CC

= Min, I

CC

CE1 = VIL and CE2 = VIH,
IDQ = 0mA, f = F

CE1 = VIL and CE2 = VIH,
IDQ = 0mA, f = 1MHz

CE1 = VIH, or CE2 = VIL,
IDQ = 0mA

CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V

= -1.0mA 2.4 -- -- V

OH

4. F

MAX

5. I

CC(MAX.)

6. I

CCSB1(MAX.)

VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V

=1/t

RC.

is 45mA/113mA at VCC=3.0V/5.0V and TA=70OC.

is 8.0uA/50uA at VCC=3.0V/5.0V and TA=70OC.

MAX

(4)

n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.

(2)

-- 0.8 V

(3)

CC

+0.3

V

-- -- 1 uA

-- --

-- --

-- --

--

1.5 16

6.0 100

(1)

46

115

2

10

1.0

2.0

mA

mA

mA

uA

MAX. UNITS

VDR V

(3)

I

Data Retention Current

CCDR

t

CDR

for Data Retention

CC

Chip Deselect to Data
Retention Time

CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V

CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V

See Retention Waveform

tR Operation Recovery Time

1. VCC=1.5V, TA=25OC and not 100% tested.

2. tRC = Read Cycle Time.

3. I

is 4.0uA at TA=70OC.

CCRD(Max.)

n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)

V

CC

VDR≧1.5V

CE1

V

IH

CE1≧VCC - 0.2V

3

1.5 -- -- V

-- 0.7 8.0 uA

0 -- -- ns

(2)

t

-- -- ns

RC

t

R

V

IH

May. 2006

BS6

2L

V

1600

R0201

-BS62LV1600 Rev

ision 2.3

Data Retention Mode

V

CC

V

CC

V

DR

1.5V

(1)

1

TTL

→ ←

CC

GND

→ ←

10% 10%

n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)

V

CC

t

CDR

≧

CE2

V

IL

CE2≦0.2V

n AC TEST CONDITIONS

(Test Load and Input/Output Reference)

n KEY TO SWITCHING WAVEFORMS

Input Pulse Levels Vcc / 0V

WAVEFORM INPUTS OUTPUTS

t

R

V

IL

Input Rise and Fall Times 1V/ns
Input and Output Timing

Reference Level

t

, t

CLZ

Output Load

OLZ

Others CL = 30pF+1TTL

0.5Vcc

, t

, t

, t

CHZ

CL = 5pF+1TTL

OHZ

WHZ

Output

C

L

V

1. Including jig and scope capacitance.

ALL INPUT PULSES

90%

90%

Rise Time :
1V/ns

Fall Time :
1V/ns

n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)

READ CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVQX

t

E1LQV

t

E2HQV

t

GLQV

t

E1LQX

t

E2HQX

t

GLQX

t

E1HQZ

t

E2LQZ

t

GHQZ

t

AVQX

PARANETER

NAME

DESCRIPTION

tRC Read Cycle Time 55 -- -- 70 -- -- ns
tAA Address Access Time -- -- 55 -- -- 70 ns

t
t

ACS1

ACS2

Chip Select Access Time (CE1)

Chip Select Access Time (CE2)

tOE Output Enable to Output Valid -- -- 25 -- -- 30 ns

t
t

t

t
t

t

CLZ1

CLZ2

OLZ

CHZ1

CHZ2

OHZ

Chip Select to Output Low Z (CE1)

Chip Select to Output Low Z (CE2)

Output Enable to Output Low Z 10 -- -- 10 -- -- ns

Chip Select to Output High Z (CE1)

Chip Select to Output High Z (CE2)

Output Enable to Output High Z -- -- 25 -- -- 30 ns

tOH Data Hold from Address Change 10 -- -- 10 -- -- ns

MUST BE
STEADY

MAY CHANGE
FROM “H” TO “L”

MAY CHANGE
FROM “L” TO “H”

DON’T CARE
ANY CHANGE
PERMITTED

DOES NOT
APPLY

CYCLE TIME : 55ns

(VCC =3.0~5.5V)

MIN. TYP. MAX.

CYCLE TIME : 70ns

(VCC = 2.7~5.5V)

MIN. TYP. MAX.

MUST BE
STEADY

WILL BE CHANGE
FROM “H” TO “L”

WILL BE CHANGE
FROM “L” TO “H”

CHANGE :
STATE UNKNOW

CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE

UNITS

-- -- 55 -- -- 70 ns

-- -- 55 -- -- 70 ns

10 -- -- 10 -- -- ns
10 -- -- 10 -- -- ns

-- -- 30 -- -- 35 ns

-- -- 30 -- -- 35 ns

4

May. 2006

BS6

2L

V

1600

R0201

-BS62LV1600 Rev

ision 2.3

OH

AA

(5)

OUT

CE2 CE1

ACS2

ACS1

(5)

OH

RC

OE

(5)

(1,5)

OE

(5)

ACS1

CHZ1

(1,5)

(5)

OLZ

AA

n SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE 1

(1,2,4)

t

ADDRESS

t

t

OH

RC

D

OUT

READ CYCLE 2

(1,3,4)

t

D

t

t

CLZ

READ CYCLE 3

ADDRESS

(1, 4)

t

t

t

CE1

CE2

t

CLZ1

D

OUT

t

CLZ2

t

t

ACS2

t

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE1 = VIL and CE2= VIH.

3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.

4. OE = VIL.

5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.

t

CHZ1

t

t

CHZ2

, t

t

OHZ

t

CHZ2

t

5

May. 2006

BS6

2L

V

1600

R0201

-BS62LV1600 Rev

ision 2.3

(3)

(11)

(11)

(2)

(4,10)

AS

(3)

DH

tDW

OE

(5) (5)

n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)

WRITE CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVWL

t

AVWH

t

E1LWH

t

WLWH

t

WHAX

t

E2LAX

t

WLQZ

t

DVWH

t

WHDX

t

GHQZ

t

WHQX

PARANETER

NAME

DESCRIPTION

tWC Write Cycle Time 55 -- -- 70 -- -- ns
tAS Address Set up Time 0 -- -- 0 -- -- ns

tAW Address Valid to End of Write 40 -- -- 50 -- -- ns

tCW Chip Select to End of Write 40 -- -- 50 -- -- ns

tWP Write Pulse Width 30 -- -- 35 -- -- ns

t

t

t

WR1

WR2

WHZ

Write Recovery Time (CE1, WE)

Write Recovery Time (CE2)

Write to Output High Z -- -- 25 -- -- 30 ns
tDW Data to Write Time Overlap 25 -- -- 30 -- -- ns
tDH Data Hold from Write Time 0 -- -- 0 -- -- ns
t

Output Disable to Output in High Z -- -- 25 -- -- 30 ns

OHZ

tOW End of Write to Output Active 5 -- -- 5 -- -- ns

n SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE 1

(1)

t

WC

CYCLE TIME : 55ns

(VCC = 3.0~5.5V)

MIN. TYP. MAX.

0 -- -- 0 -- -- ns
0 -- -- 0 -- -- ns

CYCLE TIME : 70ns

(VCC = 2.7~5.5V)

MIN. TYP. MAX.

UNITS

ADDRESS

CE1

CE2

WE

D

OUT

D

IN

t

WR1

t

CW

t

CW

t

AW

t

t

t

OHZ

WP

t

WR2

t

6

May. 2006

BS6

2L

V

1600

R0201

-BS62LV1600 Rev

ision 2.3

t

WC

(11)

(11)

(2)

(4,10)

AS

(3)

DH

tDW

OUT

(5) (5)

OW

(7) (8) (8,9)

WRITE CYCLE 2

(1,6)

ADDRESS

CE1

t

CW

CE2

WE

D

t

CW

t

AW

t

WP

t

t

WHZ

D

IN

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and
WE low. All signals must be active to initiate a write and any one signal can terminate a
write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.

3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of
write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.

5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = VIL).

7. D

is the same phase of write data of this write cycle.

OUT

8. D

is the read data of next address.

OUT

9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.

11. tCW is measured from the later of CE1 going low or CE2 going high to the end of write.

t

WR2

t

t

7

May. 2006

BS6

2L

V

1600

R0201

-BS62LV1600 Rev

ision 2.3

PACKAGE

F:

BGA-48-0912

GRADE

SPEED

70: 70ns

PKG MATERIAL

TSOP

II-44

n ORDERING INFORMATION

BS62LV1600 X X Z Y Y

55: 55ns

-: Normal
G: Green, RoHS Compliant
P: Pb free, RoHS Compliant

C: +0oC ~ +70oC
I: -40oC ~ +85oC

E: TSOP II-44

Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.

n PACKAGE DIMENSIONS

8

May. 2006

BS6

2L

V

1600

R0201

-BS62LV1600 Rev

ision 2.3

D

48

E1 D1 e

D

D1

e E1

2.625

n PACKAGE DIMENSIONS (continued)

1.4 Max.

SIDE VIEW

0.25±0.05

NOTES:

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

0.1

3.375

VIEW A

48 mini-BGA (9mm x 12mm)

N E

12.0 9.0

E±0.1

3.75

5.25

SOLDER BALL 0.35 ±0.05

0.75

9

May. 2006

BS6

2L

V

1600

R0201

-BS62LV1600 Rev

ision 2.3

n Revision History

Revision No. History Draft Date Remark

2.2 Add Icc1 characteristic parameter Jan. 13, 2006

Improve Iccsb1 spec.
I-grade from 220uA to 100uA at 5.0V
20uA to 16uA at 3.0V
C-grade from 110uA to 50uA at 5.0V
10uA to 8.0uA at 3.0V

2.3 Change I-grade operation temperature range May. 25, 2006

- from –25OC to –40OC

10

May. 2006