Datasheet BS616UV2011TC, BS616UV2011EI, BS616UV2011EC, BS616UV2011DI, BS616UV2011DC Datasheet (BSI)
...
Revision 2.4
April 2002
1
Ultra Low Power/Voltage CMOS SRAM
128K x 16 or 256K x 8 bit switchable
The BS616UV2021 is a high performance, Ultra low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits or
262,144 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.08uA and maximum access time of 70/100ns in 2.0V operation.
Easy memory expansion is provided by active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616UV2021 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV2021 is available in DICE form and 48-pin BGA type.
POWER DISSIPATION
SPEED
( ns )
STANDBY
(I
CCSB1
, Max )
Operating
(I CC, Max )
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc=
2.0V
Vcc=
2.0V
Vcc=
3.0V
Vcc=
2.0V
Vcc=
3.0V
PKG TYPE
BS616UV2021DC DICE
BS616UV2021AC
+0
O
C to +70OC1.8 20mA
BGA-48-0608
V ~ 3.6V 70 / 100 0.5uA 0.7uA 15mA
BS616UV2021DI DICE
BS616UV2021AI
-40
O
C to +85OC1.8 25mA
BGA-48-0608
V ~ 3.6V 70 / 100 1uA 1.5uA 20mA
• Ultra low operation voltage : 1.8 ~ 3.6V
• Ultra low power consumption :
Vcc = 2.0V C-grade: 15mA (Max.) operating current
I-grade: 20mA (Max.) operating current
0.08uA (Typ.) CMOS standby current
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade: 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 2.0V
-10 100ns (Max.) at Vcc = 2.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
DESCRIPTION
FEATURES
BLOCK DIAGRAM
PRODUCT FAMILY
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
BS616UV2021
Row
Decoder
Memory Array
1024 x 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A1 A2 A3
Data
Input
Buffer
Control
Vss
Vdd
OE
WE
D0
A8
A12
16(8)
16(8)
16(8)
16(8)
CE1
D15
A11
A7
A13
14(16)
128(256)
2048
1024
20
A10
A9
A0
A6
A4
A16
A14
Address
Input
Buffer
A5
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
A15
CIO
CE2
(SAE)
PIN CONFIGURATION
R0201-BS616UV2021
BSI
Revision 2.4
April 2002
2
PIN DESCRIPTIONS
BSI
BS616UV2021
R0201-BS616UV2021
Name Function
A0-A16 Address Input
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
SAE Address Input
This address input incorporates with the above 17 address input select one of the
262,144 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.
CIO x8/x16 select input
This input selects the organization of the SRAM. 131,072 x 16-bit words configuration
is selected if CIO is HIGH. 262,144 x 8-bit bytes configuration is selected if CIO is
LOW.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read
from or write to the device. If either chip enable is not active, the device is deselected
and is in a standby power mode. The DQ pins will be in the high impedance state
when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins. The chip is deselected when
both LB and UB pins are HIGH.
D0 - D15 Data Input/Output Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
Revision 2.4
April 2002
3
MODE CE1 CE2 OE WE CIO LB UB SAE D0~7 D8~15 VCC Current
H X X X
Fully Standby
X L
X X X
X X
X High-Z High-Z I
CCSB
, I
CCSB1
Output Disable L H H H X X X X High-Z High-Z I
CC
L H Dout High-Z
H L High-Z Dout
Read from SRAM
( WORD mode )
L H L H H
L L
X
Dout Dout
I
CC
L H Din X
H L X Din
Write to SRAM
( WORD mode )
L H X L H
L L
X
Din Din
I
CC
Read from SRAM
( BYTE Mode )
L H L H L X X A-1 Dout High-Z I
CC
Write to SRAM
( BYTE Mode )
L H X L L X X A-1 Din X I
CC
TRUTH TABLE
BSI
BS616UV2021
SYMBOL PAR AME TER CONDITIONS MAX. UNIT
C
IN
Input
Capacitance
VIN=0V 6 pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V 8 pF
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial 0OC to +70OC1.8V ~ 3.6V
Industrial -40OC to +85OC1.8V ~ 3.6V
ABSOLUTE MAXIMUM RATINGS
(1)
OPERATING RANGE
CAPACITANCE
(1)
(TA = 25oC, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not tested.
SYMBOL PARAME TER RATING UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
V
T
BIAS
Temperature Under Bias -40 to +125
O
C
T
STG
Storage Temperature -60 to +150
O
C
P
T
Power Dissipation 1.0 W
I
OUT
DC Output Current 20 mA
R0201-BS616UV2021
Revision 2.4
April 2002
4
PARAMETER
NAME
PARAMETER TEST CONDITIONS MIN. TYP.
(1)
MAX. UNITS
Vcc=2V
0.6
V
IL
Guaranteed Input Low
Voltage
(2)
Vcc=3V
-0.5 --
0.8
V
Vcc=2V
1.4
V
IH
Guaranteed Input High
Voltage
(2)
Vcc=3V
2.0
--
Vcc+0.2
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc -- -- 1 uA
I
OL
Output Leakage Current
Vcc = Max, CE1 = V
IH
or CE2=VILor OE = V
IH
,
V
I/O
= 0V to Vcc
-- -- 1 uA
Vcc=2V
V
OL
Output Low Voltage
Vcc = Max, IOL= 2mA
Vcc=3V
-- -- 0.4 V
Vcc=2V
1.6
V
OH
Output High Voltage
Vcc = Min, IOH= -1mA
Vcc=3V
2.4
-- -- V
Vcc=2V
-- -- 15
I
CC
Operating Power Supply
Current
Vcc = Max, CE1= V
IL
IDQ= 0mA, F = Fmax
(3)
, CE2=V
IH
Vcc=3V
-- -- 20
mA
Vcc=2V
-- -- 0.5
I
CCSB
Standby Current-TTL
Vcc = Max, CE1 = V
IH
IDQ= 0mA
or CE2=V
IL
Vcc=3V
-- -- 1
mA
Vcc=2V
-- 0.08 0.5
I
CCSB1
Standby Current-CMOS
Vcc = Max, CE1
CE2Љ0.2V,
Њ
Other inputsЊVcc - 0.2V or
Vcc=3V
Vcc-0.2V or
V
IN
Љ
0.2V
-- 0.1 0.7
uA
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
DC ELECTRICAL CHARACTERISTICS (TA = 0
o
C to +70oC)
BSI
BS616UV2021
R0201-BS616UV2021
Revision 2.4
April 2002
5
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.
(1)
MAX. UNITS
V
DR
Vcc for Data Retention
CE1
Њ
Vcc - 0.2V or CE2 Љ0.2V or
V
IN
Њ
Vcc - 0.2V or V
IN
Љ
0.2V
1.5 -- --
V
I
CCDR
Data Retention Current
CE1
Њ
Vcc - 0.2V or CE2 Љ0.2V
V
IN
Њ
Vcc - 0.2V or V
IN
Љ
0.2V
-- 0.05 0.5 uA
t
CDR
Chip Deselect to Data
Retention Time
0----
ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
-- --
ns
DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70
o
C )
1. Vcc = 1.5V, TA= + 25OC
2. t
RC
= Read Cycle Time
BSI
BS616UV2021
LOW V
CC
DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
CE1
Data Retention Mode
Vcc
t CDR
Vcc
t R
VIHVIH
Vcc
VDR Њ 1.5V
CE1 Њ Vcc - 0.2V
LOW V
CC
DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
CE2
Data Retention Mode
Vcc
t CDR
Vcc
t R
VIL
VIL
Vcc
VDR Њ 1.5V
CE2 Љ 0.2V
R0201-BS616UV2021
Revision 2.4
April 2002
6
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC ELECTRICAL CHARACTERISTICS (TA = 0
o
C to +70oC, Vcc =2.0V )
READ CYCLE
AC TEST CONDITIONS
AC TEST LOADS AND WAVEFORMS
BSI
BS616UV2021
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
R0201-BS616UV2021
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS616UV2021-70
MIN. TYP. MAX.
BS616UV2021-10
MIN. TYP. MAX.
UNIT
t
AVAX
Read Cycle Time
t
RC
70 -- -- 100 -- -- ns
t
AVQV
t
AA
Address Access Time
-- -- 70 -- -- 100 ns
t
E1LQV
t
ACS1
Chip Select Access Time
(CE1)
-- -- 70 -- -- 100 ns
t
E2LQV
t
ACS2
Chip Select Access Time
(CE2)
-- -- 70 -- -- 100 ns
t
BA
t
BA
Data Byte Control Access Time
(LB,U ) -B - -- 35 -- -- 50 ns
t
GLQV
t
OE
Output Enable to Output Valid
-- -- 35 -- -- 50 ns
t
ELQX
t
CLZ
Chip Select to Output Low Z
(CE1, 2) 10CE -- -- 15 -- -- ns
t
BE
t
BE
Data Byte Control to Output Low Z
(LB,U ) 10B ----15---- ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
10 -- -- 15 -- -- ns
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z
(CE1,CE2)
0--350--40ns
t
BDO
t
BDO
Data Byte Control to Output High Z
(LB, UB)
0--350--40ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0--300--35ns
t
AXOX
t
OH
Output Disable to Address Change
10 -- -- 15 -- -- ns
Ω800
THEVENIN EQUIVALENT
ALL INPUT PULSES
→
10%
←
90%
Vcc
GND
→
←
5ns
90%
10%
1.2V
OUTPUT
FIGURE 2
2V
OUTPUT
INCLUDING
JIG AND
SCOPE
Ω
1333
Ω
2000
5PF
FIGURE 1B
2V
OUTPUT
INCLUDING
JIG AND
SCOPE
Ω
1333
Ω
100PF
FIGURE 1A
2000
1. tBA is 35ns/50ns (@speed=70ns/100ns) with address toggle .
t
BA is 70ns/100ns (@speed=70ns/100ns) without address toggle .
NOTE :
(1)
Revision 2.4
April 2002
7
SWITCHING WAVEFORMS (READ CYCLE)
BSI
BS616UV2021
R0201-BS616UV2021
READ CYCLE3
(1,4)
READ CYCLE2
(1,3,4)
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
IL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = V
IL .
5. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
±
READ CYCLE1
(1,2,4)
t RC
t OH
t AA
D
OUT
ADDRESS
t OH
t CLZ
t CHZ
(5)
D
OUT
CE1
(5)
t ACS1
CE2
t OH
t RC
t OE
D
OUT
LB,UB
CE1
OE
ADDRESS
t CLZ
(5)
t ACS1
t CHZ
(1,5)
t OHZ
(5)
t OLZ
t AA
t BDO
t BA
t BE
CE2
t ACS2
t ACS2
Revision 2.4
April 2002
8
AC ELECTRICAL CHARACTERISTICS (TA = 0
o
C to +70oC, Vcc =2.0V )
WRITE CYCLE
SWITCHING WAVEFORMS (WRITE CYCLE)
BSI
BS616UV2021
R0201-BS616UV2021
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS616UV2021-70
MIN. TYP. MAX.
BS616UV2021-10
MIN. TYP. MAX.
UNIT
t
AVAX
t
WC
Write Cycle Time
70 -- -- 100 -- -- ns
t
E1LWH
t
CW
Chip Select to End of Write
70 -- -- 100 -- -- ns
t
A
VWL
t
AS
Address Setup Time
0----0---- ns
t
AVWH
t
AW
Address Valid to End of Write
70 -- -- 100 -- -- ns
t
WLWH
t
WP
Write Pulse Width
35 -- -- 50 -- -- ns
t
WHAX
t
WR
Write recovery Time (CE2,CE1,WE)
0----0---- ns
t
BW
t
BW
Date Byte Control to End of Write
(LB,U ) 3B 0 -- -- 40 -- -- ns
t
WLQZ
t
WHZ
Write to Output in High Z
0--300--40ns
t
DVWH
t
DW
Data to Write Time Overlap
30 -- -- 40 -- -- ns
t
WHDX
t
DH
Data Hold from Write Time
0----0---- ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0--300--40ns
t
WHOX
t
OW
End of Write to Output Active
5----10---- ns
t WR
WRITE CYCLE1
(1)
t WC
(3)
t CW
(11)
t BW
(2)
t WP
t AW
t OHZ
(4,10)
t AS
(3)
t DH
t DW
D
IN
D
OUT
WE
CE1
OE
ADDRESS
(5)
CE2
(5)
(5)
LB,UB
1. tBW is 30ns/40ns (@speed=70ns/100ns) with address toggle. ; tBW is 70ns/100ns (@speed=70ns/100ns) without address toggle .
NOTE :
(1)
Revision 2.4
April 2002
9
BSI
BS616UV2021
R0201-BS616UV2021
WRITE CYCLE2
(1,6)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low.
All signals must be active to initiate a write and any one signal can terminate
a write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. T
WR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
IL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. T
CW is measured from the later of CE2 going high or CE1 going low to the end of write.
±
t WC
t CW
(11)
(2)
t WP
t AW
t WHZ
(4,10)
t AS
t WR
(3)
t DH
t DW
D
IN
D
OUT
WE
CE1
ADDRESS
t DH
(7) (8)
(8,9)
CE2
LB,UB
t BW
(5)
(5)
Revision 2.4
April 2002
10
BS616UV2021
BSI
R0201-BS616UV2021
PACKAGE DIMENSIONS
D1
VIEW A
1.4 Max.
e
E1
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
8.0 6.0
EN
48 3.755.25
E1D1
NOTES:
48 mini-BGA (6 x 8mm)
PACKAGE
A :BGA - 48 PIN(6x8mm)
D :DICE
ORDERING INFORMATION
BS616UV2021 X X -- Y Y
GRADE
C: +0oC ~ +70oC
I: -40
o
C ~ +85oC
SPEED
70: 70ns
10: 100ns
Revision 2.4
April 2002
11
BSI
R0201-BS616UV2021
REVISION HISTORY
Revision Description Date Note
2.2 2001 Data Sheet release Apr. 15, 2001
2.3 Modify Standby Current (Typ.
and Max.)
Jun. 29, 2001
2.4 Modify some AC parameters April,15,2002
BS616UV2021
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