BSI BS616LV8016 User Manual

Very Low Power CMOS SRAM

R0201

-BS616LV8016

Revision

2.3

H F E D C B A 1 2 3 4 5 6 A9

NC

WE

A7

A5 OE A3 A0 A6 A4 A1 A2

UB

DQ10

NC A8

Write Driver

Sense Amp

Address Input Buffer

A0

DQ0

. . . . .

.

DQ15

16

16

16

16

10

. . . . .

.

512K X 16 bit

Pb-Free and Green package materials are compliant to RoHS

BS616LV8016

n FEATURES

Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V
Ÿ Very low power consumption :

VCC = 3.0V Operation current : 31mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.8uA (Typ.) at 25 OC
VCC = 5.0V Operation current : 76mA (Max.) at 55ns
10mA (Max.) at 1MHz
Standby current : 3.5uA (Typ.) at 25OC

Ÿ High speed access time :

-55 55ns(Max.) at VCC=3.0~5.5V

-70 70ns(Max.) at VCC=2.7~5.5V

Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE2, CE1 and OE options
Ÿ I/O Configuration x8/x16 selectable by LB and UB pin.
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation, no clock, no refresh
Ÿ Data retention supply voltage as low as 1.5V

n POWER CONSUMPTION

PRODUCT

FAMILY

BS616LV8016DC
BS616LV8016FC

OPERATING

TEMPERATURE

Commercial

+0OC to +70OC

STANDBY

(I

, Max)

CCSB1

VCC=5.0V VCC=3.0V

25uA 4.0uA 9mA 39mA 75mA 1.5mA 19mA 30mA

n DESCRIPTION

The BS616LV8016 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 by 16 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.8uA at 3.0V/25OC and maximum access time of 55ns at

3.0V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE1), active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BS616LV8016 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS616LV8016 is available in DICE form and 48-ball BGA
package.

POWER DISSIPATION

1MHz 10MHz f

Operating

VCC=5.0V VCC=3.0V

(ICC, Max)

1MHz 10MHz

Max.

f

Max.

PKG TYPE

DICE
BGA-48-0912

BS616LV8016FI

Industrial

-40OC to +85OC

50uA 8.0uA 10mA 40mA 76mA 2mA 20mA 31mA BGA-48-0912

n PIN CONFIGURATIONS

n BLOCK DIAGRAM

LB

CE2

CE1

DQ8

DQ0

DQ9

DQ1

DQ2

VSS

DQ11

A17

DQ3

VCC

VCC

DQ12

VSS

A16

DQ4

VSS

DQ14

G

DQ15

A18

DQ13

A14

A12

A15

A13

A10

DQ5

A11

DQ6

DQ7

48-ball BGA top view

A13
A12
A11
A10

CE2
CE1

WE

V

Address
A9
A8
A7
A6
A5
A4

OE
UB

LB

CC

V

SS

Input

Buffer

Control

Decoder

Data
Input

Buffer

Data

Output

Buffer

Row

1024

A14

Memory Array

Column Decoder

A16

A15

1024 x 8192

Column I/O

512

A18

A17

8192

9

A1A2

A3

Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.

1

May. 2006

BS6

16L

V

8016

Revision

2.3

. With the

selected and the write enable is inactive, data will be present on the DQ pins and they

n PIN DESCRIPTIONS

Name Function

A0-A18 Address Input

CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input

WE Write Enable Input

OE Output Enable Input

LB and UB Data Byte Control Input

DQ0-DQ15 Data Input/Output
Ports
VCC

VSS

n TRUTH TABLE

MODE

Chip De-selected

(Power Down)

Output Disabled

CE1

H X X X X X High Z High Z I
X L X X X X High Z High Z I
X X X X H H High Z High Z I

L H H H L X High Z High Z ICC
L H H H X L High Z High Z ICC

CE2

These 19 address inputs select one of the 524,288 x 16 bit in the RAM

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read form or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
The write enable input is active LOW and controls read and write operations
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is

will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.

16 bi-directional ports are used to read data from or write data into the RAM.

Power Supply

Ground

WE

OE

LB UB

DQ0~DQ7 DQ8~DQ15 VCC CURRENT

CCSB

CCSB

CCSB

, I
, I
, I

CCSB1

CCSB1

CCSB1

Read L H H L

Write L H L X

NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)

R0201-BS616LV8016

2

L L D

H L High Z D

L H D
L L DIN DIN ICC

H L X DIN ICC

L H DIN X ICC

D

OUT

High Z ICC

OUT

ICC

OUT

ICC

OUT

May. 2006

BS6

16L

V

8016

Revision

2.3

n ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

TERM

T

BIAS

T

Storage Temperature -60 to +150

STG

PARAMETER RATING UNITS

Terminal Voltage with
Respect to GND

Temperature Under
Bias

(1)

(2)

-0.5

to 7.0

-40 to +125

n OPERATING RANGE

V

O

C

O

C

PT Power Dissipation 1.0 W

n CAPACITANCE

I

DC Output Current 20 mA

OUT

SYMBOL PAMAMETER CONDITIONS MAX. UNITS

1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

2. –2.0V in case of AC pulse width less than 30 ns.

1. This parameter is guaranteed and not 100% tested.

n DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)

PARAMETER

NAME

PARAMETER TEST CONDITIONS MIN. TYP.

RANG

AMBIENT

TEMPERATURE

VCC

Commercial 0OC to + 70OC 2.4V ~ 5.5V

Industrial -40OC to + 85OC 2.4V ~ 5.5V

(1)

(TA = 25OC, f = 1.0MHz)

CIN

CIO

Input
Capacitance

Input/Output
Capacitance

VIN = 0V 6 pF

V

= 0V 8 pF

I/O

(1)

MAX. UNITS

VCC Power Supply 2.4 -- 5.5 V

VIL Input Low Voltage -0.5

VIH Input High Voltage 2.2 -- V

IIL Input Leakage Current

ILO Output Leakage Current

VOL Output Low Voltage V

VOH Output High Voltage V

(5)

I

CC

I

CC1

I

CCSB

I

CCSB1

1. Typical characteristics are at TA=25OC and not 100% tested.

2. Undershoot: -1.0V in case of pulse width less than 20 ns.

3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.

4. F

=1/t

MAX

5. I

CC (MAX.)

6. I

CCSB1(MAX.)

Operating Power Supply
Current

Operating Power Supply
Current

Standby Current – TTL

(6)

Standby Current – CMOS

RC.

is 30mA/75mA at VCC=3.0V/5.0V and TA=70OC.

is 4.0uA/25uA at VCC=3.0V/5.0V and TA=70OC.

VIN = 0V to VCC,
CE1 = VIH or CE2 = VIL
V

= 0V to V

I/O

,

CC

CE1 = VIH or CE2 = VIL or OE = VIH

= Max, IOL = 2.0mA -- -- 0.4 V

CC

= Min, I

CC

CE1 = VIL and CE2 = VIH,
IDQ = 0mA, f = F

CE1 = VIL and CE2 = VIH,
IDQ = 0mA, f = 1MHz

CE1 = VIH, or CE2 = VIL,
IDQ = 0mA

CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V

= -1.0mA 2.4 -- -- V

OH

VCC=3.0V

(4)

MAX

VCC=5.0V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V

(2)

-- 0.8 V

CC

-- -- 1 uA

-- -- 1 uA

-- --

-- --

-- --

--

0.8 8.0

3.5 50

1.0

2.0

+0.3

31
76

2

10

(3)

V

mA

mA

mA

uA

R0201-BS616LV8016

3

May. 2006

BS6

16L

V

8016

Revision

2.3

Data Retention Mode

V

CC

V

CC

Data Retention Mode

V

CC

t

CDR

V

CC

(1)

1

TTL

→ ←

CC

GND

90%

→ ←

n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.

(1)

MAX. UNITS

VDR V

(3)

I

Data Retention Current

CCDR

t

CDR

for Data Retention

CC

Chip Deselect to Data
Retention Time

CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V

See Retention Waveform

tR Operation Recovery Time

1. VCC=1.5V, TA=25OC and not 100% tested.

2. tRC = Read Cycle Time.

3. I

is 2.0uA at TA=70OC.

CCDR(Max.)

n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)

V

CC

VDR≧1.5V

CE1

V

IH

CE1≧VCC - 0.2V

n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)

V

CC

t

CDR

VDR≧1.5V

CE2

V

IL

CE2≦0.2V

n AC TEST CONDITIONS

(Test Load and Input/Output Reference)

n KEY TO SWITCHING WAVEFORMS

Input Pulse Levels Vcc / 0V

WAVEFORM INPUTS OUTPUTS

1.5 -- -- V

-- 0.4 4.0 uA

0 -- -- ns

(2)

t

-- -- ns

RC

t

R

V

IH

t

R

V

IL

Output

R0201-BS616LV8016

Input Rise and Fall Times 1V/ns
Input and Output Timing

Reference Level

t

, t

CLZ

Output Load

OLZ

Others CL = 30pF+1TTL

, t

, t

, t

CHZ

OHZ

0.5Vcc

CL = 5pF+1TTL

WHZ

ALL INPUT PULSES

V

10%

C

L

Rise Time:
1V/ns

1. Including jig and scope capacitance.

90%

10%

Fall Time:
1V/ns

4

MUST BE
STEADY

MAY CHANGE
FROM “H” TO “L”

MAY CHANGE
FROM “L” TO “H”

DON’T CARE
ANY CHANGE
PERMITTED

DOES NOT
APPLY

MUST BE
STEADY

WILL BE CHANGE
FROM “H” TO “L”

WILL BE CHANGE
FROM “L” TO “H”

CHANGE :
STATE UNKNOW

CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE

May. 2006

BS6

16L

V

8016

Revision

2.3

OH

AA

n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)

READ CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVQX

t

ELQV

t

ELQV

t

BLQV

t

GLQV

t

ELQX

t

ELQX

t

BLQX

t

GLQX

t

EHQZ

t

EHQZ

t

BHQZ

t

GHQZ

t

AVQX

PARANETER

NAME

DESCRIPTION

tRC Read Cycle Time 55 -- -- 70 -- -- ns
tAA Address Access Time -- -- 55 -- -- 70 ns
t
t

ACS1

ACS2

tBA

Chip Select Access Time (CE1)
Chip Select Access Time (CE2)
Data Byte Control Access Time (LB, UB)

tOE Output Enable to Output Valid -- -- 30 -- -- 35 ns
t
t

CLZ1

CLZ2

tBE

t
t
t

t

t

OLZ

CHZ1

CHZ2

BDO

OHZ

Chip Select to Output Low Z (CE1)
Chip Select to Output Low Z (CE2)
Data Byte Control to Output Low Z (LB, UB)

Output Enable to Output Low Z 5 -- -- 5 -- -- ns

Chip Select to Output High Z (CE1)
Chip Select to Output High Z (CE2)
Data Byte Control to Output High Z (LB, UB)

Output Enable to Output High Z -- -- 25 -- -- 30 ns

tOH Data Hold from Address Change 10 -- -- 10 -- -- ns

n SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE 1

(1,2,4)

t

ADDRESS

t

t

OH

RC

D

OUT

CYCLE TIME : 55ns

(VCC=3.0~5.5V)

MIN. TYP. MAX. MIN. TYP. MAX.

-- -- 55 -- -- 70 ns

-- -- 55 -- -- 70 ns

-- -- 55 -- -- 70 ns

10 -- -- 10 -- -- ns
10 -- -- 10 -- -- ns
10 -- -- 10 -- -- ns

-- -- 30 -- -- 35 ns

-- -- 30 -- -- 35 ns

-- -- 30 -- -- 35 ns

CYCLE TIME : 70ns

(VCC=2.7~5.5V)

UNITS

t

R0201-BS616LV8016

5

May. 2006

BS6

16L

V

8016

Revision

2.3

(5)

OUT

CE2 CE1

ACS2

ACS1

(5)

OH

RC

OE

OE

(5)

t

ACS1

CHZ

(1,5)

(5)

OLZ

AA

BA

(5)

(2,5)

READ CYCLE 2

(1,3,4)

t

D

t

t

CLZ

READ CYCLE 3

ADDRESS

(1, 4)

t

t

CE1

t

t

t

CLZ1

CE2

LB, UB

t

CLZ2

t

ACS2

t

t

BE

D

OUT

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE1 = VIL and CE2= VIH.

3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.

4. OE = VIL.

5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.

t

t

CHZ2

t

t

CHZ

t

BDO

t

OHZ

R0201-BS616LV8016

6

May. 2006

BS6

16L

V

8016

Revision

2.3

(3)

(11)

(2)

(4,10)

AS

(3)

DH

tDW

OE

(5)

(11)

(5)

n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)

WRITE CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVWL

t

AVWH

t

ELWH

t

BLWH

t

WLWH

t

WHAX

t

WHAX

t

WLQZ

t

DVWH

t

WHDX

t

GHQZ

t

WHQX

PARANETER

NAME

DESCRIPTION

tWC Write Cycle Time 55 -- -- 70 -- -- ns

tAS Address Set up Time 0 -- -- 0 -- -- ns
tAW Address Valid to End of Write 55 -- -- 70 -- -- ns
tCW Chip Select to End of Write 55 -- -- 70 -- -- ns
tBW

Data Byte Control to End of Write (LB, UB)

tWP Write Pulse Width 30 -- -- 35 -- -- ns
t
t
t

WR1

WR2

WHZ

Write Recovery Time (CE1, WE)

Write Recovery Time (CE2)

Write to Output High Z -- -- 25 -- -- 30 ns
tDW Data to Write Time Overlap 25 -- -- 30 -- -- ns
tDH Data Hold from Write Time 0 -- -- 0 -- -- ns
t

Output Disable to Output in High Z -- -- 25 -- -- 30 ns

OHZ

tOW End of Write to Output Active 5 -- -- 5 -- -- ns

n SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE 1

(1)

t

WC

CYCLE TIME : 55ns

(VCC=3.0~5.5V)

MIN. TYP. MAX. MIN. TYP. MAX.

25 -- -- 30 -- -- ns

0 -- -- 0 -- -- ns
0 -- -- 0 -- -- ns

CYCLE TIME : 70ns

(VCC=2.7~5.5V)

UNITS

ADDRESS

CE1

CE2

LB, UB

WE

D

OUT

t

t

OHZ

t

t

WR1

WR2

t

CW

t

CW

t

BW

t

AW

t

WP

t

D

IN

R0201-BS616LV8016

7

May. 2006

BS6

16L

V

8016

Revision

2.3

t

WC

(11)

(2)

(4,10)

AS

(3)

DH

tDW

OUT

(5)

OW

(7) (8) (8,9)

(12)

(11)

WRITE CYCLE 2

(1,6)

ADDRESS

CE1

t

CW

CE2

LB, UB

t

CW

t

BW

t

t

WHZ

AW

t

WP

WE

t

D

D

IN

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and
WE low. All signals must be active to initiate a write and any one signal can terminate a
write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.

3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of
write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.

5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = VIL).

7. D

is the same phase of write data of this write cycle.

OUT

8. D

is the read data of next address.

OUT

9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.

11. tCW is measured from the later of CE1 going low or CE2 going high to the end of write.

12. The change of Read/Write cycle must accompany with CE or address toggled.

t

WR

t

t

R0201-BS616LV8016

8

May. 2006

BS6

16L

V

8016

Revision

2.3

D

48

E1 D1 e

D1

1.2

e E1

SOLDER BALL

0.35

±0.05

2.625

PACKAGE

F: BGA-48-0912

GRADE

I: -40oC ~ +85

C

SPEED

70: 70ns

PKG MATERIAL

P: Pb free

, RoHS Compliant

n ORDERING INFORMATION

BS616LV8016 X X Z Y Y

55: 55ns

-: Normal
G: Green, RoHS Compliant

C: +0oC ~ +70oC

D: DICE

o

Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.

n PACKAGE DIMENSIONS

Max.

3.375

VIEW A

SIDE VIEW

D 0.1

0.25±0.05

E±0.1

NOTES:

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

N E

12.0 9.0

5.25

3.75

0.75

R0201-BS616LV8016

48 mini-BGA (9mm x 12mm)

9

May. 2006

BS6

16L

V

8016

Revision

2.3

n Revision History

Revision No. History Draft Date Remark

2.2 Add Icc1 characteristic parameter Jan. 13, 2006

Improve Iccsb1 spec.
I-grade from 110uA to 50uA at 5.0V
10uA to 8.0uA at 3.0V
C-grade from 55uA to 25uA at 5.0V

5.0uA to 4.0uA at 3.0V

2.3 Change I-grade operation temperature range May. 25, 2006

- from –25OC to –40OC

R0201-BS616LV8016

10

May. 2006