BSI BS616LV4017 User Manual

查询BD616LV4017AC-55供应商

Very Low Power/Voltage CMOS SRAM

BSI

256K X 16 bit

 FEATURES

• Wide Vcc operation voltage : 2.4~5.5V

• Very low power consumption :
Vcc = 3.0V C-grade: 26mA (@55ns) operating current

I-grade: 27mA (@55ns) operating current

C-grade: 21mA (@70ns) operating current

I-grade: 22mA (@70ns) operating current

0.45uA (Typ.) CMOS standby current

Vcc = 5.0V C-grade: 63mA (@55ns) operating current

I-grade: 65mA (@55ns) operating current

C-grade: 53mA (@70ns) operating current

I-grade: 55mA (@70ns) operating current

2.0uA (Typ.) CMOS standby current

• High speed access time :

-55 55ns

-70 70ns

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

 PRODUCT FAMILY

PRODUCT FAMILY

BS616LV4017DC

BS616LV4017EC

BS616LV4017AC
BS616LV4017DI

BS616LV4017EI
BS616LV4017AI

OPERATING

TEMPERATURE

+0O C to +70O C

2.4V ~ 5.5V 55 /70

-40O C to +85O C 2.4V ~ 5.5V 55 /70

 PIN CONFIGURATIONS

GND

1

A4

2

A3

3

A2

4

A1

5

A0

6

CE

7

DQ0

8

DQ1

9

DQ2

10

DQ3
VCC

DQ4
DQ5
DQ6
DQ7

WE
A17
A16
A15
A14
A13

BS616LV4017EC

11
12

BS616LV4017EI

13
14
15
16
17
18
19
20
21
22

44

A5

43

A6

42

A7

41

OE

40

UB

39

LB

38

DQ15

37

DQ14

36

DQ13

35

DQ12

34

GND

33

VCC

32

DQ11

31

DQ10

30

DQ9

29

DQ8

28

NC

27

A8

26

A9

25

A10

24

A11

23

A12

Vcc

RANGE

BS616LV4017

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE and OE options

• I/O Configuration x8/x16 selectable by LB and UB pin

 DESCRIPTION

The BS616LV4017 is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of

0.45uA at 3.0V/25oC and maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable (CE)
,active LOW output enable(OE) and three-state output drivers.
The BS616LV4017 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV4017 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package and 48-ball BGA package.

SPEED

(

ns )

55ns :3.0~5.5V
70ns :2.7~5.5V

 BLOCK DIAGRAM

POWER DISSIPATION

STANDBY

CCSB1

( I

, Max ) ( ICC, Max )

3.0V

5uA

10uA

A4
A3
A2

A1

A0

.
.
.
.

.
.
.
.

Vcc=

30uA

60uA

Address

Input

Buffer

16

16

Vcc= 5.0V

A17

A16

A15
A14
A13
A12

DQ0

DQ15

Operating

Vcc =

3.0V

70ns 70ns

21mA

22mA 55mA

22

Row

Decoder

Data

Input

Buffer

Data

Output

Buffer

16

Vcc =

53mA

2048

16

5.0V

Memory Array

2048 x 2048

Write Driver

Column Decoder

PKG TYPE

DICE

TSOP2-44
BGA-48-0608
DICE
TSOP2-44
BGA-48-0608

2048

Column I/O

Sense Amp

128

CE

Vcc

Gnd

WE

OE
UB

LB

Control

Address Input Buffer

A10

A11

Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.

R0201-BS616LV4017

1

14

A9 A8 A7

A5

A6

Revision 2.1
Jan. 2004

BSI

 PIN DESCRIPTIONS

Name Function

BS616LV4017

A0-A17 Address Input

CE Chip Enable Input

WE Write Enable Input

OE Output Enable Input

LB and UB Data Byte Control Input

DQ0 - DQ15 Data Input/Output

These 18 address inputs select one of the 262,144 x 16-bit words in the RAM.

CE is active LOW. Chip enables must be active when data read from or write to the

device. if chip enable is not active, the device is deselected and is in a standby power

mode. The DQ pins will be in the high impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

Lower byte and upper byte data input/output control pins.

These 16 bi-directional ports are used to read data from or write data into the RAM.

Ports

Vcc

Gnd

Power Supply

Ground

 TRUTH TABLE

MODE CE WE OE LB UB D0~D7 D8~D15 Vcc CURRENT

Not selected

(Power Down) X

Output Disabled

Read L H L

Write L L X

H

L

X X X X High Z High Z I

X X H H High Z High Z I

XX

L

H H X X High Z High Z I

H

H

L L Dout Dout I

H L High Z Dout I

L H Dout High Z I

LL Din Din I

HL X Din I

LH Din X I

High Z

High Z

CCSB

CCSB

, I

CCSB1

, I

CCSB1

I

CC

CC

CC

CC

CC

CC

CC

CC

R0201-BS616LV4017

2

Revision 2.1
Jan. 2004

BSI

BS616LV4017

 ABSOLUTE MAXIMUM RATINGS

(1)

 OPERATING RANGE

SYMBOL PAR AME TER RATING UNITS

TERM

V

BIAS

T

STG

T

PT

OUT

I

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.

Terminal Voltage with
Respect to GND

Temperature Under Bias -40 to +85

Storage Temperature

Power Dissipation

DC Output Current 20 mA

-0.5 to

Vcc+0.5

-60 to +150

1.0 W

V

O

C

O

C

 CAPACITANCE

1. This parameter is guaranteed and not 100% tested.

 DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85

PARAMETER

NAME

IL

V

IH

V

IL

I

LO

I

OL

V

OH

V

(5)

CC

I

PARAMETER TEST CONDITIONS MIN. TYP.

Guaranteed Input Low
Voltage

Guaranteed Input High
Voltage

Input Leakage Current Vcc = Max, V

Output Leakage Current

Output Low Voltage

Output High Voltage

Supply Current

(2)

(2)

Operating Power

IN

= 0V to Vcc -- -- 1 uA

Vcc = Max, CE = V

= 0V to Vcc

V

I/O

, or OE = VIH,

IH

Vcc = Max, IOL= 2.0mA

Vcc = Min, I

CE=V

IL

F=Fmax

= -1.0mA

OH

,IDQ= 0mA,

(3)

70ns

70ns

RANGE

Commercial 0O C to +70O C 2.4V ~ 5.5V

Industrial -40O C to +85O C 2.4V ~ 5.5V

SYMBOL PARAMETER CONDITIONS MAX. UNIT

IN

C

DQ

C

o

C )

Vcc=3.0V

Vcc=5.0V

Vcc=3.0V

Vcc=5.0V

AMBIENT

TEMPERATURE

(1)

Input
Capacitance
Input/Output
Capacitance

-0.5

2.0

2.2

Vcc

(TA = 25oC, f = 1.0 MHz)

VIN=0V 6 pF

I/O

V

=0V 8 pF

(1)

MAX.

--

0.8

0.8

--

Vcc+0.3

UNITS

-- -- 1 uA

Vcc=3.0V

Vcc=5.0V

Vcc=3.0V

Vcc=5.0V

Vcc=3.0V

Vcc=5.0V

--

2.4

2.4

--

--

--

--

0.4

0.4

--

22

55

V

V

V

V

mA

CCSB

I

CCSB1

I

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/t

4. IccSB1_MAX. is 5uA/30uA at Vcc=3.0V/5.0V and TA=70oC.

5. Icc_MAX. is 27mA(@3.0V)/65mA(@5.0V) under 55ns operation.

R0201-BS616LV4017

Standby Current-TTL

(4)

Standby Current-CMOS

.

RC

IH

CE = V

, IDQ= 0mA

CE ≧Vcc-0.2V,

IN

Vcc - 0.2V or V

V

≧

≦

IN

3

Vcc=3.0V 0.5

--

Vcc=5.0V

0.2V

Vcc=3.0V

Vcc=5.0V

--

--

0.45

2.0 60

mA

1.0

10

uA

Revision 2.1
Jan. 2004

BSI

BS616LV4017

 DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85

o

C )

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.

V

DR

I

CCDR

t

CDR

t

R

1. Vcc = 1.5V, TA= + 25OC

2. tRC= Read Cycle Time

3. IccDR_MAX. is 0.8uA at TA=70OC.

Vcc for Data Retention

(3)

Data Retention Current

Chip Deselect to Data
Retention Time

Operation Recovery Time

CE ≧Vcc - 0.2V

IN

V

Vcc - 0.2V or V

≧

CE ≧Vcc - 0.2V

IN

V

Vcc - 0.2V or V

≧

See Retention Waveform

IN

IN

0.2V

≦

0.2V

≦

1.5 -- -- V

T

RC

 LOW VCCDATA RETENTION WAVEFORM ( CE Controlled )

Data Retention Mode

≥

Vcc

CE

Vcc

t CDR

VDR 1.5V

≥

CE Vcc - 0.2V

(1)

MAX. UNITS

-- 0.3 1.3 uA

0---- ns

(2)

-- -- ns

Vcc

t R

VIHVIH

R0201-BS616LV4017

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Revision 2.1
Jan. 2004

BSI

BS616LV4017

AC TEST CONDITIONS

(Test Load and Input/Output Reference)

Input Pulse Levels

Input Rise and Fall Times

Input and Output
Timing Reference Level

Output Load

Vcc / 0V

1V/ns

0.5Vcc

CL = 30pF+1TTL
C

= 100pF+1TTL

L

 AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85

 KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

o

C )

MUST BE
STEADY

MAY CHANGE
FROM H TO L

MAY CHANGE
FROM L TO H

,

DON T CARE:
ANY CHANGE
PERMITTED

DOES NOT
APPLY

MUST BE
STEADY

WILL BE
CHANGE
FROM H TO L

WILL BE
CHANGE
FROM L TO H

CHANGE :
STATE
UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE

READ CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVQV

t

ELQV

t

BA

t

GLQV

t

E1LQX

t

BE

t

GLQX

t

EHQZ

t

BDO

t

GHQZ

t

AXOX

PARAMETER

NAME

t

RC

t

AA

t

ACS

(1)

t

BA

t

OE

t

CLZ

t

BE

t

OLZ

t

CHZ

t

BDO

t

OHZ

t

OH

DESCRIPTION

Read Cycle Time

Address Access Time

Chip Select Access Time

Data Byte Control Access Time

Output Enable to Output Valid

Chip Select to Output Low Z

Data Byte Control to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Data Byte Control to Output High Z

Output Disable to Output in High Z

Data Hold from Address Change

(LB,UB)----35----30ns

(LB,UB) 5 -- -- 5 -- -- ns

(LB,UB) -- -- 35 -- -- 30 ns

CYCLE TIME : 70ns

(Vcc = 2.7~5.5V)

MIN. TYP. MAX.

70 -- -- 55 -- -- ns

-- -- 70 -- -- 55 ns

-- -- 70 -- -- 55 ns

-- -- 35 -- -- 30 ns

10 -- -- 10 -- -- ns

5----5---- ns

-- -- 35 -- -- 30 ns

-- -- 30 -- -- 25 ns

10 -- -- 10 -- -- ns

NOTE :

1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle. ; tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle.

CYCLE TIME : 55ns

(Vcc = 3.0~5.5V)

MIN. TYP. MAX.

UNIT

R0201-BS616LV4017

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Revision 2.1
Jan. 2004

BSI

 SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

ADDRESS

D

(1,2,4)

t AA

t OH

OUT

BS616LV4017

t RC

t OH

READ CYCLE2

CE

LB,UB

D

OUT

READ CYCLE3

ADDRESS

OE

CE

LB,UB

(1,3,4)

(1,4)

t CLZ

(5)

t ACS

t CLZ

t BA

(5)

t BE

t BDO

t CHZ

t RC

t AA

t OE

t OH

t OLZ

(5)

t ACS

(5)

t OHZ

t CHZ

(1,5)

t BA

t BE

t BDO

D

OUT

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE = V

3. Address valid prior to or coincident with CE transition low.

4. OE = VIL .

5. The parameter is guaranteed but not 100% tested.

R0201-BS616LV4017

IL.

6

Revision 2.1
Jan. 2004

BSI

BS616LV4017

 AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85

o

C )

WRITE CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

E1LWH

t

AVWL

t

AVWH

t

WLWH

t

WHAX

t

BW

t

WLQZ

t

DVWH

t

WHDX

t

GHQZ

t

WHOX

NOTE :

1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle.

PARAMETER

NAME

t

WC

t

CW

t

AS

t

AW

t

WP

t

WR

(1)

t

BW

t

WHZ

t

DW

t

DH

t

OHZ

t

OW

DESCRIPTION

Write Cycle Time

Chip Select to End of Write

Address Setup Time

Address Valid to End of Write

Write Pulse Width

Write recovery Time

Date Byte Control to End of Write

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End of Write to Output Active

(CE,WE)

(LB,UB) 30 -- -- 25 -- -- ns

CYCLE TIME : 70ns

(Vcc = 2.7~5.5V)

MIN. TYP. MAX.

70 -- -- 55 -- -- ns

70

-- -- 55 -- -- ns

0 -- -- 0 -- -- ns

70 -- -- 55 -- -- ns

35 -- -- 30 -- -- ns

0 -- -- 0 -- -- ns

-- -- 30 -- -- 25 ns

30 -- -- 25 -- -- ns

0 -- -- 0 -- -- ns

-- -- 30 -- -- 25 ns

5 -- -- 5 -- -- ns

CYCLE TIME : 55ns

(Vcc = 3.0~5.5V)

MIN. TYP. MAX.

 SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

(1)

t WC

UNIT

ADDRESS

OE

CE

LB,UB

WE

D

D

R0201-BS616LV4017

IN

OUT

t AS

(4,11)

t OHZ

(3)

t WR

(10)

(5)

t CW

t BW

t AW

t WP

(2)

(3)

t DH

t DW

7

Revision 2.1
Jan. 2004

BSI

BS616LV4017

WRITE CYCLE2

ADDRESS

CE

LB,UB

WE

D

OUT

D

IN

(1,6)

t AS

(5)

(4,11)

t WHZ

t AW

t WC

t CW

t WP

t BW

(10)

t WR

(3)

(2)

t OW

(7) (8)

t DW

t DH

(8,9)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.

WR is measured from the earlier of CE or WE going high at the end of write cycle.

3. T

4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

OUT is the same phase of write data of this write cycle.

7. D

8. D

OUT is the read data of next address.

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.

10. TCW is measured from the later of CE going low to the end of write.

11. The parameter is guaranteed but not 100% tested.

R0201-BS616LV4017

IL ).

8

Revision 2.1
Jan. 2004

BSI

BS616LV4017

 ORDERING INFORMATION

BS616LV4017 X X Z Y Y

SPEED

55: 55ns
70: 70ns

PKG MATERIAL

-: Normal
G: Green
P: Pb free

GRADE

C: +0oC ~ +70oC

I: -40oC ~ +85oC

PACKAGE

E: TSOP2-44
A: BGA-48-0608
D: DICE

Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.

 PACKAGE DIMENSIONS

TSOP2-44

R0201-BS616LV4017

9

Revision 2.1
Jan. 2004

BSI

 PACKAGE DIMENSIONS (continued)

BS616LV4017

0.05

±

0.25

NOTES:

1: CONTROLLING DIMENSIONS ARE IN MI LLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

1.4 Max.

e

VIEW A

SIDE VIEW

D0.1

D1

48 mini-BGA (6 x 8mm)

N ED

48 8. 0 6.0

E1

±

E0.1

E1D1

3.755.25

SOLDER BALL 0.3 5±0.05

R0201-BS616LV4017

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Revision 2.1
Jan. 2004