Page 1
Very Low Power/Voltage CMOS SRAM
BSI
FEATURES
• Vcc operation voltage range : 2.7V ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 23mA (@55ns) operating current
I -grade: 25mA (@55ns) operating current
C-grade: 15mA (@70ns) operating current
I -grade: 16mA (@70ns) operating current
0.3uA(Typ.)CMOS standby current
• High speed access time :
-55 55ns
-70 70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
PRODUCT FAMILY
PRODUCT
FAMILY
BS616LV2019DC DICE
BS616LV2019TC TSOP1-48
BS616LV2019AC
BS616LV2019DI DICE
BS616LV2019TI TSOP1-48
BS616LV2019AI
128K X 16 bit
OPERATING
TEMPERATURE
+0O C to +70O C
-40O C to +85O C
DESCRIPTION
Vcc
RANGE
2.7V ~3.6V 55/70
2.7V ~ 3.6V
SPEED
( ns )
55ns: 2.7~3.6V
70ns: 2.7~3.6V
55/70
BS616LV2019
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV2019 is a high performance , very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.3uA at 3.0V /25oC and maximum access time of 55ns at 2.7V/ 85oC.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The BS616LV2019 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2019 is available in DICE form , JEDEC standard 48-pin
TSOP Type I package and 48-ball BGA package.
POWER DISSIPATION
STANDBY
CCSB1
( I
, Max )
Vcc=3.0V Vcc=3.0V
3.0uA
5.0uA
Operating
55ns
23mA
25mA
( ICC, Max )
PKG TYPE
70ns
15mA
BGA-48-0608
16mA
BGA-48-0608
PIN CONFIGURATIONS
1
A15
A14
A13
A12
A11
A10
A9
A8
NC
9
NC
10
/WE
CE2
NC
13
/UB
/LB
NC
16
NC
17
A7
A6
A5
A4
A3
A2
A1
24 25
A
B
C
D
E
F
G
H
BS616LV2019TC
BS616LV2019TI
123456
LB
D8
UBOEA3
D10 A5
D9
VSS
VCC
D14
D15
N.C.
N.C.
D11
D12
N.C.
D13
A14
A12
N.C.
A8 A9
48-ball BGA top view
A0
A1 A2
A4
A6
A7
A16
A15WED5
A13
A10
CE
A11
48
47
46
37
27
N.C.
D0
D2
D1
VCC
D3
VSS
D4
D6
D7
N.C.
BLOCK DIAGRAM
A16
NC
VSS
IO15
IO7
IO14
IO6
IO13
IO5
IO12
IO4
VCC
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
/OE
VSS
/CE
A0
A13
A15
A16
A14
A12
A7
A6
A5
A4
DQ0
DQ15
CE2,CE
Vcc
Gnd
A8
Address
20
Input
Buffer
Data
16
Input
.
.
.
.
.
.
.
.
WE
OE
UB
LB
Control
Buffer
16
Data
Output
Buffer
Row
Decoder
1024
16
16
A11
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV2019
1
Memory Array
1024 x 2048
2048
Column I/O
Write Driver
Sense Amp
128
Column Decoder
14
Address Input Buffer
A9
A3 A2 A1
Revision 1.2
May 2004
A10
A0
Page 2
BSI
PIN DESCRIPTIONS
Name Function
BS616LV2019
A0-A16 Address Input
CE Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
Ports
Vcc
Gnd
TRUTH TABLE
MODE CE CE2
Not selected
(Power Down)
Output Disabled
Read L H H L
Write L H L X
1. 48B BGA ignore CE2 condition.
H
X
X
L
(1)
X X X X X High Z High Z I
L X X X X High Z High Z I
X
H H H X X High Z High Z I
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected. (48B BGA ignore CE2 pin)
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
WE OE LB UB D0~D7 D8~D15 Vcc CURRENT
, I
CCSB
CCSB1
, I
CCSB
CCSB1
XX
H
H
L L Dout Dout I
H L High Z Dout I
L H Dout High Z I
LL Din Din I
HL X Din I
LH Din X I
High Z
High Z
I
CCSB
, I
CCSB1
CC
CC
CC
CC
CC
CC
CC
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Revision 1.2
May 2004
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BSI
ABSOLUTE MAXIMUM RATINGS
SYMBOL PARAMETER RATING UNITS
TERM
V
cc
V
BIAS
T
STG
T
T
P
OUT
I
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
Terminal Voltage with
Respect to GND
Power Supply
Temperature Under Bias -40 to +85
Storage Temperature -60 to +150
Power Dissipation 1.0 W
DC Output Current 20 mA
(1)
-0.5 to
Vcc+0.5
-0.5 to
Vcc+0.5
V
V
O
C
O
C
OPERATING RANGE
RANGE
Commercial 0O C to +70O C2.7V ~ 3.6V
Industrial -40O C to +85O C2.7V ~ 3.6V
TEMPERATURE
CAPACITANCE
SYMBOL PARAMETER CONDITIONS MAX. UNIT
C
C
IN
DQ
Input
Capacitance
Input/Output
Capacitance
BS616LV2019
AMBIENT
(1)
(TA = 25oC, f = 1.0 MHz)
VIN=0V 6 pF
I/O
V
=0V 8 pF
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
1. This parameter is guaranteed and not 100% tested.
maximum rating conditions for extended periods may affect
reliability.
(3)
(4)
0.2V
o
(4)
0.2V,
≦
C )
(1)
Vcc =3.0V -0.3 -- 0.8 V
Vcc =3.0V 2.0 -- V
-- -- 1 uA
= VIL or OE = VIH,
Vcc =3.0V -- -- 0.4 V
Vcc =3.0V 2.4 -- -- V
3.0 V
70ns 16
55ns
Vcc =3.0V -- -- 0.5 mA
Vcc =3.0V -- 0.3 5.0 uA
-- -- 1 uA
-- --
DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85
PAR AM ET ER
NAME
IL
V
IH
V
IL
I
ILO Output Leakage Current
VOL Output Low Voltage Vcc = Max, IOL = 2.0mA
VOH Output High Voltage Vcc = Min, IOH = -1.0mA
(6)
CC
I
CCSB
I
Standby Current-TTL
(5)
CCSB1
I
Standby Current-CMOS
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
6. Icc_Max. is 23mA(@55ns) / 15mA(@70ns) at Vcc=3.0V/ 0~70oC.
RC
PAR AME TE R TEST CONDITIONS MIN. TYP.
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
Voltage
(2)
Input Leakage Current Vcc = Max, V
Vcc = Max,CE = V
I/O
V
= 0V to Vcc
Operating Power Supply
Current
CE = V
DQ
= 0mA, F = Fmax
I
CE=V
DQ
I
= 0mA
CE≧Vcc-0.2V or CE2
Vcc-0. 2V or V
V
≧
IN
. 4. 48B BGA ignore CE2 condition. 5.IccsB1_Max. is 3.0uA at Vcc=3.0V and TA=70oC.
IL
, CE2
IH
or CE2
IN
= 0V to Vcc
IH
or CE2
(4)
= VIH
(4)
=VIL
≦
IN
Vcc
MAX.
+0.3
cc
25
UNITS
V
mA
DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85
o
C )
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.
o
C.
(3)
,
(3)
,
V
I
CCDR
t
CDR
t
1. Vcc = 1.5V, TA= + 25OC 2.tRC= Read Cycle Time
Vcc for Data Retention
DR
(4)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
R
3. 48B BGA ignore CE2 condition. 4. Icc
CE ≧ Vcc - 0.2V or CE2 ≦ 0.2V
IN
V
≧ Vcc - 0.2V or VIN ≦ 0.2V
CE ≧ Vcc - 0.2V or CE2 ≦ 0.2V
IN
V
≧ Vcc - 0.2V or VIN ≦ 0.2V
See Retention Waveform
DR is 0.7uA at TA=70
R0201-BS616LV2019
3
(1)
MAX. UNITS
1.5 -- -- V
-- 0.1 1.0 uA
0 -- -- ns
(2)
T
RC
-- -- ns
Revision 1.2
May 2004
Page 4
BSI
LOW VCCDATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
≥
Vcc
CE
Vcc
t CDR
VDR 1.5V
≥
CE Vcc - 0.2V
BS616LV2019
Vcc
t R
VIHVIH
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
Vcc / 0V
1V/ns
0.5Vcc
CL = 100pF+1TTL
= 30pF+1TTL
C
L
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
E1LQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
(48B BGA ignore CE2 condition)
PARAMETER
NAME
t
RC
t
AA
t
ACS1 , 2
(1)
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
DESCRIPTION
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
o
C )
CYCLE TIME : 55ns
(Vcc = 2.7~3.6V)
MIN. TYP. MAX.
CYCLE TIME : 70ns
MIN. TYP. MAX.
55 -- -- 70 -- -- ns
-- -- 55 -- -- 70 ns
(CE,CE2)
-- -- 55 -- -- 70 ns
(LB,UB)----30----35 ns
-- -- 30 -- -- 35 ns
(CE,CE2)
10 -- -- 10 -- -- ns
(LB,UB)10----10---- ns
5----5---- ns
(CE,CE2)
-- -- 30 -- -- 35 ns
(LB,UB) -- -- 30 -- -- 35 ns
-- -- 25 -- -- 30 ns
10 -- -- 10 -- -- ns
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
(Vcc = 2.7~3.6V)
NOTE :
1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle.
UNIT
R0201-BS616LV2019
4
Revision 1.2
May 2004
Page 5
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
ADDRESS
D
(1,2,4)
t AA
t OH
OUT
BS616LV2019
t RC
t OH
READ CYCLE2
CE2
CE
D
OUT
READ CYCLE3
ADDRESS
OE
CE2
CE
(1,4)
(1,3,4)
t CLZ
tACS2
(5,6)
t CLZ
(6)
t ACS1
t ACS1
(5,6)
t AA
t ACS2
t OLZ
(5,6)
t CHZ
t RC
t OHZ
t CHZ
t OH
(5)
(1,5,6)
t OE
(6)
LB,UB
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V
3. Address valid prior to or coincident with CE transition low.
4. OE = V
5. The parameter is guaranteed but not 100% tested.
6. 48B BGA ignore this parameters related to CE2 .
R0201-BS616LV2019
IL .
t BE
IL and CE2 = VIH.
t BDO
t BA
5
Revision 1.2
May 2004
Page 6
BSI
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85
WRITE CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
E1LWH
t
AVWL
t
AVWH
t
WLWH
t
WHAX
t
BW
t
WLQZ
t
DVWH
t
WHDX
t
GHQZ
t
WHOX
(48B BGA ignore CE2 condition)
PARAMETER
NAME
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
(1)
t
BW
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
Write Cycle Time
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write recovery Time
Date Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
DESCRIPTION
(CE,CE2)
(CE,CE2,WE)
(LB,UB)25----30---- ns
o
C )
CYCLE TIME : 55ns
(Vcc = 2.7~3.6V)
MIN. TYP. MAX.
55 -- -- 70 -- -- ns
55 -- -- 70 -- -- ns
0----0---- ns
55 -- -- 70 -- -- ns
30 -- -- 35 -- -- ns
0----0---- ns
-- -- 25 -- -- 30 ns
25 -- -- 30 -- -- ns
0----0---- ns
-- -- 25 -- -- 30 ns
5----5---- ns
BS616LV2019
CYCLE TIME : 70ns
(Vcc = 2.7~3.6V)
MIN. TYP. MAX.
NOTE :
1. tBW is 25ns/30ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle.
UNIT
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
ADDRESS
OE
CE2
CE
LB,UB
WE
t AS
(4,10)
(5,12)
(5)
(5)
t OHZ
D
OUT
t AW
t WC
t CW
t BW
t WP
(11)
(3)
t WR
(3)
(2)
t DH
t DW
D
IN
R0201-BS616LV2019
6
Revision 1.2
May 2004
Page 7
BSI
BS616LV2019
WRITE CYCLE2
ADDRESS
CE2
CE
LB,UB
WE
D
OUT
D
IN
(1,6)
t AS
(5,12)
(5)
(5)
(4,10)
t WHZ
t AW
t WC
t CW
t BW
t WP
(11)
t WR
(3)
(2)
t OW
(7) (8)
t DW
t DH
(8,9)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. T
WR is measured from the earlier of CE2 going low, or CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE2 high transition or CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
7. D
OUT is the same phase of write data of this write cycle.
8. D
OUT is the read data of next address.
9. If CE2 is high or CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. T
CW is measured from the later of CE2 going high or CE going low to the end of write.
12. 48B BGA ignore this parameters related to CE2 .
R0201-BS616LV2019
IL ).
7
Revision 1.2
May 2004
Page 8
BSI
BS616LV2019
ORDERING INFORMATION
BS616LV2019 X X Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
o
C ~ +70oC
C: +0
o
I: -40
C ~ +85oC
PACKAGE
T: TSOP1-48
A: BGA-48-0608
D: DICE
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
1.4 Max.
D1
e
VIEW A
48 mini-BGA (6 x 8)
NOTES:
1: CONTROLLING DIMENSIONS ARE I N MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER O R PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
EN
8.0 6.0
E1
48 3.75
5.25
E1D1
R0201-BS616LV2019
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Revision 1.2
May 2004
Page 9
BSI
PACKAGE DIMENSIONS
1
24
24
1
TSOP1-48PIN
BS616LV2019
12°(2x)
12°(2x)
SYMBOL
UNIT
A
A1
A2
b
b1
c
c1
D
E
e
HD
L
L1
y
θ
A
A
L
L1
±0.004
0.0433
±0.002
0.004
±0.002
0.039
±0.002
0.009
±0.001
0.008
0.004 ~ 0.008
0.004 ~ 0.006
±0.004
0.645
±0.004
0.472
0.020
±0.004
0.708
±0.008
0.0236±0.006
±0.004
0.0315
0.004 Max.
0
°~ 8°
GAUGE PLANE
0
0.254
MMINCH
±0.10
1.10
±0.05
0.10
±0.05
1.00
±0.05
0.22
±0.03
0.20
0.10 ~ 0.21
0.10 ~ 0.16
16.40±0.10
±0.10
11.80
±0.10
0.50
±0.20
18.00
±0.15
0.60
0.80
±0.10
0.1 Max.
0
°~ 8°
HD
48
25
D
"A"
25
48
12°(2X)
WITH PLATING
BASE METAL
c
12°(2X)
e
b
E
Seating Plane
c1
y
A
b
b1
SECTION A-A
A2
A1
SEATING PLANE
"A" DETAIL VIEW
R0201-BS616LV2019
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Revision 1.2
May 2004
Page 10
BSI
REVISION HISTORY
Revision Description Date Note
BS616LV2019
1.1 Initial release
1.2 Change Vcc_min
from 2.4V to 2.7V
Jan., 05, 2004
May, 03, 2004
R0201-BS616LV2019
10
Revision 1.2
May 2004
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