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BSI
Very Low Power/Voltage CMOS SRAM
128K X 16 bit
BS616LV2017
FEATURES
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 60mA (@55ns) operating current
I -grade: 62mA (@55ns) operating current
C-grade: 53mA (@70ns) operating current
I -grade: 55mA (@70ns) operating current
1.0uA(Typ.)CMOS standby current
• High speed access time :
-55 55ns
-70 70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The BS616LV2017 is a high performance , very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
1.0uA at 5.0V /25oC and maximum access time of 55ns at 5.0V/ 85oC.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The BS616LV2017 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2017 is available in DICE form , JEDEC standard 44-pin
TSOP Type II package and 48-ball BGA package.
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
55ns: 4.5~5.5V
70ns: 4.5~5.5V
BS616LV2017DC DICE
BS616LV2017EC TSOP2-44
+0O C to +70O C
4.5V ~5.5V 55/70
BS616LV2017AC
BS616LV2017DI DICE
BS616LV2017EI TSOP2-44
-40O C to +85O C
4.5V ~ 5.5V
55/70
BS616LV2017AI
PIN CONFIGURATIONS
1
A4
2
A3
3
A2
4
A1
5
A0
6
CE
7
DQ0
8
DQ1
9
DQ2
10
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
A
B
C
D
E
F
G
H
BS616LV2017EC
11
12
BS616LV2017EI
13
14
15
16
17
18
19
20
21
22
123456
LB
D8
D9
VSS
VCC
D14
D15
N.C.
UBOEA3
D10 A5
D11
D12
D13
N.C.
A8 A9
A0
N.C.
N.C.
A14
A12
A1 A2
A4
A6
A7
A16
A15WED5
A13
A10
CE
A11
44
A5
43
A6
42
A7
41
OE
40
UB
39
LB
38
DQ15
37
DQ14
36
DQ13
35
DQ12
34
GND
33
VCC
32
DQ11
31
DQ10
30
DQ9
29
DQ8
28
NC
27
A8
26
A9
25
A10
24
A11
23
NC
N.C.
D0
D2
D1
VCC
D3
VSS
D4
D6
D7
N.C.
BLOCK DIAGRAM
POWER DISSIPATION
STANDBY
CCSB1
( I
, Max )
Vcc=5.0V Vcc=5.0V
10uA
30uA
A8
A13
A15
Address
A16
A14
A12
A7
A6
A5
A4
DQ0
DQ15
Vcc
Gnd
Input
Buffer
16
.
.
.
.
.
.
.
CE
WE
OE
UB
LB
16
.
Control
20
Operating
55ns
60mA
62mA
Row
Decoder
Data
Input
Buffer
Data
Output
Buffer
( ICC, Max )
PKG TYPE
70ns
53mA
BGA-48-0608
55mA
BGA-48-0608
1024
Memory Array
1024 x 2048
2048
16
16
Column I/O
Write Driver
Sense Amp
Column Decoder
Address Input Buffer
A9
A3 A2 A1
A11
128
14
A10
A0
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
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BSI
PIN DESCRIPTIONS
Name Function
BS616LV2017
A0-A16 Address Input
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Ports
Vcc
Gnd
Power Supply
Ground
TRUTH TABLE
MODE CE WE OE LB UB D0~D7 D8~D15 Vcc CURRENT
H
Not selected
(Power Down) X
Output Disabled
Read L H L
Write L L X
X X X X High Z High Z I
X X H H High Z High Z I
L
XX
L
H H X X High Z High Z I
H
H
L L Dout Dout I
H L High Z Dout I
L H Dout High Z I
LL Din Din I
HL X Din I
LH Din X I
High Z
High Z
CCSB
CCSB
, I
CCSB1
, I
CCSB1
I
CC
CC
CC
CC
CC
CC
CC
CC
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ABSOLUTE MAXIMUM RATINGS
SYMBOL PARAMETER RATING UNITS
TERM
V
BIAS
T
STG
T
T
P
OUT
I
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Terminal Voltage with
Respect to GND
Temperature Under Bias -40 to +85
Storage Temperature -60 to +150
Power Dissipation 1.0 W
DC Output Current 20 mA
DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85
PAR AME TER
NAME
IL
V
IH
V
IL
I
ILO Output Leakage Current
VOL Output Low Voltage Vcc = Max, IOL = 2.0mA
VOH Output High Voltage Vcc = Min, IOH = -1.0mA
(5)
CC
I
CCSB
I
Standby Current-TTL
PAR AMETER TEST CONDITIONS MIN. TYP.
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
(2)
Voltage
Input Leakage Current Vcc = Max, V
Operating Power Supply
Current
(1)
-0.5 to
Vcc+0.5
IN
Vcc = Max,CE = V
I/O
V
= 0V to Vcc
IL
,
CE = V
DQ
= 0mA, F = Fmax
I
IH
CE=V
DQ
I
= 0mA
V
O
C
O
C
= 0V to Vcc
IH
or OE = VIH,
(3)
BS616LV2017
OPERATING RANGE
RANGE
Commercial 0O C to +70O C4.5V ~ 5.5V
Industrial -40O C to +85O C4.5V ~ 5.5V
CAPACITANCE
SYMBOL PARAMETER CONDITIONS MAX. UNIT
C
C
1. This parameter is guaranteed and not 100% tested.
o
C )
Vcc =5.0V
Input
IN
Capacitance
Input/Output
DQ
Capacitance
Vcc =5.0V -0.5 -- 0.8 V
Vcc =5.0V 2.2 -- V
Vcc =5.0V -- -- 0.4 V
Vcc =5.0V 2.4 -- -- V
Vcc =5.0V -- -- 1.0 mA
AMBIENT
TEMPERATURE
(1)
(TA = 25oC, f = 1.0 MHz)
Vcc
VIN=0V 6 pF
I/O
V
=0V 8 pF
(1)
MAX.
+0.3
cc
V
UNITS
-- -- 1 uA
-- -- 1 uA
70ns 55
55ns
-- -62
mA
CE
Vcc-0.2V,
(4)
CCSB1
I
Standby Current-CMOS
1. Typical characteristics are at TA = 25oC.
≧
IN
≧
V
or
-0.2
IN
V
V
≦
0.2
V
cc
V
Vcc =5.0V -- 1.0 30 uA
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
5. Icc_Max. is 60mA(@55ns) / 53mA(@70ns) at Vcc=5.0 and TA=0~70oC.
DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.
I
1. Vcc = 1.5V, TA= + 25OC 2.tRC= Read Cycle Time
3. Icc
. 4.IccsB1_Max. is 10uA at Vcc=5.0V and TA=70oC.
RC
o
C )
V
CCDR
t
CDR
t
DR_MAX. is 0.7uA at TA=70
Vcc for Data Retention
DR
(3)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
R
o
C.
CE ≧ Vcc - 0.2V,
≧ Vcc - 0.2V or VIN ≦ 0.2V
V
IN
CE ≧ Vcc - 0.2V,
≧
IN
Vcc - 0.2V or VIN ≦ 0.2V
V
See Retention Waveform
1.5 -- -- V
-- 0.1 1.0 uA
0 -- -- ns
(2)
T
RC
-- -- ns
(1)
MAX. UNITS
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LOW VCCDATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
≥
Vcc
CE
Vcc
t CDR
VDR 1.5V
≥
CE Vcc - 0.2V
BS616LV2017
Vcc
t R
VIHVIH
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
Vcc / 0V
1V/ns
0.5Vcc
CL = 100pF+1TTL
= 30pF+1TTL
C
L
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
o
C )
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
E1LQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS
(1)
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
(CE)
(LB,UB)----30----35 ns
(CE)
(LB,UB)10----10---- ns
(CE)
(LB,UB) -- -- 30 -- -- 35 ns
CYCLE TIME : 55ns
(Vcc = 4.5~5.5V)
MIN. TYP. MAX.
55 -- -- 70 -- -- ns
-- -- 55 -- -- 70 ns
-- -- 55 -- -- 70 ns
-- -- 30 -- -- 35 ns
10 -- -- 10 -- -- ns
5----5---- ns
-- -- 30 -- -- 35 ns
-- -- 25 -- -- 30 ns
10 -- -- 10 -- -- ns
NOTE :
1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle.
CYCLE TIME : 70ns
(Vcc = 4.5~5.5V)
MIN. TYP. MAX.
UNIT
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SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
ADDRESS
D
(1,2,4)
t AA
t OH
OUT
BS616LV2017
t RC
t OH
READ CYCLE2
CE
LB,UB
D
OUT
READ CYCLE3
ADDRESS
OE
CE
LB,UB
(1,3,4)
(1,4)
t CLZ
(5)
t ACS
t CLZ
(5)
t BA
t AA
t ACS
t BE
t BE
t OLZ
t BA
t OE
t RC
t BDO
t BDO
t OHZ
t CHZ
(1,5)
t CHZ
t OH
(5)
(5)
D
OUT
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = V
3. Address valid prior to or coincident with CE transition low.
4. OE = V
5. The parameter is guaranteed but not 100% tested.
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BSI
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85
o
C )
BS616LV2017
WRITE CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
E1LWH
t
AVWL
t
AVWH
t
WLWH
t
WHAX
t
BW
t
WLQZ
t
DVWH
t
WHDX
t
GHQZ
t
WHOX
PARAMETER
NAME
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
(1)
t
BW
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
DESCRIPTION
Write Cycle Time
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write recovery Time
Date Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
(CE)
(CE,WE)
(LB,UB)25----30---- ns
NOTE :
1. tBW is 25ns/30ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle.
CYCLE TIME : 55ns
(Vcc = 4.5~5.5V)
MIN. TYP. MAX.
CYCLE TIME : 70ns
(Vcc = 4.5~5.5V)
MIN. TYP. MAX.
55 -- -- 70 -- -- ns
55 -- -- 70 -- -- ns
0----0---- ns
55 -- -- 70 -- -- ns
30 -- -- 35 -- -- ns
0----0---- ns
-- -- 25 -- -- 30 ns
25 -- -- 30 -- -- ns
0----0---- ns
-- -- 25 -- -- 30 ns
5----5---- ns
UNIT
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
ADDRESS
OE
CE
LB,UB
WE
(1)
(5)
t AS
(4,10)
t OHZ
D
OUT
t AW
t WC
t CW
t WP
(11)
t BW
(3)
t WR
(3)
(2)
t DH
t DW
D
IN
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BSI
BS616LV2017
WRITE CYCLE2
ADDRESS
CE
LB,UB
WE
D
OUT
D
IN
(1,6)
t AS
(5)
(4,10)
t WHZ
t AW
t WC
t CW
t WP
t BW
(11)
t WR
(3)
(2)
t OW
(7) (8)
t DW
t DH
(8,9)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. T
WR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
7. D
OUT is the same phase of write data of this write cycle.
8. D
OUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. T
CW is measured from the later of CE going low to the end of write.
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BS616LV2017
ORDERING INFORMATION
BS616LV2017 X X Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
o
C: +0
C ~ +70oC
o
C ~ +85oC
I: -40
PACKAGE
E: TSOP2-44
A: BGA-48-0608
D: DICE
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
1.4 Max.
D1
e
VIEW A
48 mini-BGA (6 x 8)
NOTES:
1: CONTROLLING DIMENSIONS ARE I N MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER O R PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
EN
8.0 6.0
E1
48 3.75
5.25
E1D1
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BSI
PACKAGE DIMENSIONS
BS616LV2017
TSOP2-44
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