Page 1
Very Low Power/Voltage CMOS SRAM
BSI
1M x 16 or 2M x 8 bit switchable
FEATURES
• Wide Vcc operation voltage : 2.4 ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 45mA (@55ns) operating current
I -grade: 46mA (@55ns) operating current
C-grade: 36mA (@70ns) operating current
I -grade: 37mA (@70ns) operating current
3.0uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 113mA (@55ns) operating current
I -grade: 115mA (@55ns) operating current
C-grade: 90mA (@70ns) operating current
I -grade: 92mA (@70ns) operating current
15uA (Typ.) CMOS standby current
• High speed access time :
-55 55ns
-70 70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
PRODUCT FAMILY
PRODUCT FAMILY
OPERATING
TEMPERATURE
BS616LV1622TC +0O C to +70O C 2.4V ~ 5.5V 55 / 70 10uA 110uA 36mA 90mA TSOP1-48(12mmx20mm)
Vcc
RANGE
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
DESCRIPTION
The BS616LV1622 is a high performance, very low power CMOS Static
Random Access Memory organized as 1,048,676 words by 16 bits or
2,097,152 bytes by 8 bits selectable by CIO pin and operates in a wide
range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 3.0uA at 3V/25
This device provide three control inputs and three states output drivers
for easy memory expansion.
The BS616LV1622 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1622 is available in 48-pin 12mmx20mm TSOP1 package.
SPEED
(ns)
55ns : 3.0~5.5V
70ns : 2.7~5.5V
POWER DISSIPATION
STANDBY
(ICCSB1, Max)
Vcc=3V Vcc=5V
BS616LV1622
o
C and maximum access time of 55ns at 3.0V/85oC .
Operating
(ICC, Max)
Vcc=3V Vcc=5V
70ns 70ns
PKG TYPE
BS616LV1622TI -40O C to +85O C 2.4V ~ 5.5V 55 / 70 20uA 220uA 37mA 92mA
PIN CONFIGURATIONS
148A4
A3
A2
A1
A0
/CE1
D0
D1
9
D2
10
D3
Vcc
A19
/WE
A18
A17
A16
A15
A14
CIO
Vss
13
D4
D5
16
D6
17
D7
24
BS616LV1622TC
BS616LV1622T I
48-pin 12mmx20mm TSOP1 top view
47
46
37
27
25
BLOCK DIAGRAM
A5
A6
A7
/OE
/UB
/LB
CE2
SAE
D15
D14
D13
D12
Vss
Vcc
D11
D10
D9
D8
A8
A9
A10
A11
A12
A13
A19
A15
A14
A13
A12
A11
A10
A9
A8
A17
A7
A6
D15
CE1
CE2
Vdd
Vss
CIO
Address
24
Input
Buffer
D0
.
.
.
.
WE
OE
UB
LB
16(8)
.
.
16(8)
.
.
Control
Data
Input
Buffer
Data
Output
Buffer
Decoder
Row
TSOP1-48(12mmx20mm)
4096
16(8)
16(8)
Column Decoder
Address Input Buffer
A0
A16
Memory Array
4096 x 4096
Column I/O
Write Driver
Sense Amp
256(512)
A1 A2 A3
4096
16(18)
A4
A5
A18
(SAE)
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV1622
1
Revision 2.1
Jan. 2004
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BSI
PIN DESCRIPTIONS
Name Function
BS616LV1622
A0-A19 Address Input
SAE Address Input
CIO x8/x16 select input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
D0 - D15 Data Input/Output Ports
Vcc
Gnd
These 20 address inputs select one of the 1,048,576 x 16-bit words in the RAM.
This address input incorporates with the above 20 address inputs select one of the
2,097,152 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.
This input selects the organization of the SRAM. 1,048,576 x 16-bit words
configuration is selected if CIO is HIGH. 2,097,152 x 8-bit bytes configuration is
selected if CIO is LOW.
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins. The chip is deselected when
both LB and UB pins are HIGH.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
R0201-BS616LV1622
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Revision 2.1
Jan. 2004
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BSI
TRUTH TABLE
MODE CE1 CE2 OE WE CIO LB UB SAE D0~7 D8~15 VCC Current
BS616LV1622
Fully Standby
X L
X X X
X X
X High-Z High-Z I
Output Disable L H H H X X X X High-Z High-Z ICC
L H Dout High-Z
H X X X
Read from SRAM
( WORD mode )
L H L H H
H L High-Z Dout
L L
X
Dout Dout
L H Din X
Write to SRAM
( WORD mode )
Read from SRAM
( BYTE Mode )
Write to SRAM
( BYTE Mode )
L H X L H
H L X Din
L L
X
Din Din
L H L H L X X A-1 Dout High-Z I
L H X L L X X A-1 Din X I
CCSB
I
I
, I
CC
CC
CC
CC
CCSB1
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL PARAM E TER RATING UNITS
TERM
V
BIAS
T
STG
T
PT
OUT
I
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
Terminal Voltage with
Resp ect to G ND
Temperature Under Bias -40 to +85
Storage Temperature
Power Dissipation
DC Output Current 20 mA
-0.5 to
Vcc+0.5
-60 to +150
1.0 W
V
O
C
O
C
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
R0201-BS616LV1622
OPERATING RANGE
RANGE
Commercial 0
Industrial -40
CAPACITANCE
SYMBOL
C
C
1. This parameter is guaranteed and not 100% tested.
PARAMETER CONDITIONS MAX. UNIT
Input
IN
Capacitance
Input/Output
DQ
Capacitance
AMBIENT
TEMPERATURE
O
O
(1)
O
C to +70
C to +85
C 2.4V ~ 5.5V
O
C 2.4V ~ 5.5V
(TA = 25oC, f = 1.0 MHz)
VIN=0V 10 pF
I/O
V
=0V
3
Vcc
12
Revision 2.1
Jan. 2004
pF
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BSI
BS616LV1622
DC ELECTRICAL CHARACTERISTICS ( TA = -40
PARAMETER
NAME
IL
V
V
IH
IL
I
LO
I
V
OL
V
OH
(4)
CC
I
I
CCSB
(5)
CCSB1
I
PARAMETER TEST CONDITIONS MIN. TYP.
Guaranteed Input Low
(3)
Voltage
Guaranteed Input High
(3)
Voltage
Input Leakage Current Vcc = Max, V
Output Leakage Current
Vcc = Max, CE1 = V
OE = VIH, V
Output Low Voltage Vcc = Max, IOL= 2mA
Output High Voltage Vcc = Min, IOH= -1mA
Operating Power Supply
Current
Standby Current-TTL
Standby Current-CMOS
CE1 = VILand CE2 =
, IDQ= 0mA, F = Fmax
CE1 = V
, IDQ= 0mA
≧
CE1
Vcc-0.2V, or
LB and UB
Vcc - 0.2V
≧
V
IN
o
C to + 85oC )
(1)
MAX.
Vcc=3V
Vcc=5V
Vcc=3V
Vcc=5V
IN
= 0V to Vcc -- -- 1 uA
≦
0.2V, or
≦
0.2V
70ns
70ns
ViL, or
Vcc=3V
Vcc=5V
Vcc=3V
Vcc=5V
Vcc=3V
Vcc=5V
Vcc=3V
Vcc=5V
Vcc=3V
Vcc=5V
I/O
or CE2 =
IH
≧
, or CE2 =
IH
= 0V to Vcc
V
(2)
V
IL
CE2
Vcc - 0.2V
IN
or V
IH
-0.5 --
-0.5
2.0 --
2.2 --
-- 0.8
Vcc+0.3
Vcc+0.3
-- -- 1 uA
-- -- 0.4
-- -- 0.4
2.4 -- --
2.4 -- --
-- -- 37
-- -- 92
-- -- 1.3
-- -- 2.5
-- 320
-- 15 220
0.8
1. Typical characteristics are at TA = 25oC. 2. Fmax = 1/tRC.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
_Max. is 46mA(@3.0V) / 115mA(@5.0V) under 55ns operation. 5.IccsB1 is 10uA/110uA at Vcc=3.0V/5.0V and TA=70
4. Icc
UNITS
o
C.
V
V
V
V
mA
mA
uA
R0201-BS616LV1622
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Revision 2.1
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BSI
BS616LV1622
DATA RETENTION CHARACTERISTICS ( TA = -40
o
C to +85oC )
SYMBOL PAR AME TER TEST CONDITIONS MIN. TYP.
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V or
V
DR
I
CCDR
t
CDR
t
R
1. Vcc = 1.5V, TA= + 25OC
= Read Cycle Time
2. t
RC
3. I
ccDR(Max.) is 2.5uA at TA=70
LOW V
Vcc for Data Retention
(3)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
CC
Vcc
CE1
O
C.
LB ≧ Vcc - 0.2V and UB ≧ Vcc - 0.2V
≧ Vcc - 0.2V or VIN ≦ 0.2V
V
IN
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V or
LB ≧ Vcc - 0.2V and UB ≧ Vcc - 0.2V
V
≧ Vcc - 0.2V or VIN ≦ 0.2V
IN
See Retention Waveform
Data Retention Mode
Vcc
VDR ≧ 1.5V
t CDR
CE1 ≧ Vcc - 0.2V
1.5 -- --
-- 1.5 5
0 -- --
(2)
T
RC
Vcc
t R
VIHVIH
(1)
MAX. UNITS
uA
ns
-- -- ns
V
LOW V
DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
CC
Vcc
CE2
R0201-BS616LV1622
Data Retention Mode
Vcc
VDR ≧ 1.5V
t CDR
VIL
CE2 ≦ 0.2V
5
Vcc
t R
VIL
Revision 2.1
Jan. 2004
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BSI
BS616LV1622
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
Vcc / 0V
1V/ns
0.5Vcc
CL = 30pF+1TTL
= 100pF+1TTL
C
L
AC ELECTRICAL CHARACTERISTICS ( TA = -40
READ CYCLE
o
C to +85oC )
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV
t
ELQV
t
BA
t
GLQV
t
ELQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
NOTE :
1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle .
t
BA is 70ns/55ns (@speed=70ns/55ns) without address toggle .
R0201-BS616LV1622
PARAMETER
NAME
t
RC
t
AA
t
ACS1
t
ACS2
(1)
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
DESCRIPTION UNIT
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
(CE2,CE1)
(CE2,CE1)
6
(CE1)
(CE2)
(LB,UB)
(LB,UB)
(LB,UB)
CYCLE TIME : 70ns
Vcc = 2.7~5.5V Vcc = 3.0~5.5V
MIN. TYP. MAX.
CYCLE TIME : 55ns
MIN. TYP. MAX.
70 -- -- 55 -- -- ns
-- -- 70 -- -- 55 ns
-- -- 70 -- -- 55 ns
-- -- 70 -- -- 55 ns
-- -- 35 -- -- 30 ns
-- -- 35 -- -- 30 ns
10 -- -- 10 -- -- ns
5 -- -- 5 -- -- ns
5 -- -- 5 -- -- ns
-- -- 35 -- -- 30 ns
-- -- 35 -- -- 30 ns
-- -- 30 -- -- 25 ns
10 -- -- 10 -- -- ns
Revision 2.1
Jan. 2004
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BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
ADDRESS
D
READ CYCLE2
(1,2,4)
t OH
OUT
(1,3,4)
t AA
BS616LV1622
t RC
t OH
CE2
CE1
D
OUT
READ CYCLE3
ADDRESS
OE
CE2
CE1
(1,4)
t CLZ
(5)
t ACS2
t ACS1
t CLZ
(5)
t AA
t OLZ
t ACS1
t ACS2
t OE
t RC
t OHZ
t CHZ
(1,5)
t CHZ
t OH
(5)
(5)
LB,UB
t BE
t BA
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = V
5. The parameter is guaranteed but not 100% tested.
R0201-BS616LV1622
IL .
IL and CE2 = VIH.
7
t BDO
Revision 2.1
Jan. 2004
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BSI
AC ELECTRICAL CHARACTERISTICS ( TA = -40
o
C to +85oC )
BS616LV1622
WRITE CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
E1LWH
t
AVWL
t
AVWH
t
WLWH
t
WHAX
t
BW
t
WLQZ
t
DVWH
t
WHDX
t
GHQZ
t
WHOX
NOTE :
1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle.
PARAMETER
NAME
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
(1)
t
BW
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
DESCRIPTION UNIT
Write Cycle Time
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write recovery Time
Date Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
(CE2,CE1,WE) 0 -- -- 0 -- -- ns
(LB,UB) 30 -- -- 25 -- -- ns
CYCLE TIME : 70ns
Vcc = 2.7~5.5V
MIN. TYP. MAX.
CYCLE TIME : 55ns
Vcc = 3.0~5.5V
MIN. TYP. MAX.
70 -- -- 55 -- -- ns
70 -- -- 55 -- -- ns
0----0---- ns
70 -- -- 55 -- -- ns
35 -- -- 30 -- -- ns
-- -- 30 -- -- 25 ns
30 -- -- 25 -- -- ns
0----0---- ns
-- -- 30 -- -- 25 ns
5 -- -- 5 -- -- ns
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
t WC
ADDRESS
OE
CE2
CE1
LB,UB
WE
D
OUT
D
IN
t AS
(4,10)
t OHZ
(3)
t WR
(5)
(11)
(5)
t CW
t BW
(5)
t AW
t WP
(2)
(3)
t DH
t DW
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BSI
BS616LV1622
WRITE CYCLE2
ADDRESS
CE2
CE1
LB,UB
WE
D
OUT
D
IN
(1,6)
t AS
(5)
(5)
(4,10)
t WHZ
t AW
t WC
t CW
t BW
t WP
(11)
t WR
(3)
(2)
t OW
(7) (8)
t DW
t DH
(8,9)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low.
All signals must be active to initiate a write and any one signal can terminate
a write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. T
WR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
7. D
OUT is the same phase of write data of this write cycle.
8. D
OUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. T
CW is measured from the later of CE2 going high or CE1 going low to the end of write.
R0201-BS616LV1622
IL ).
9
Revision 2.1
Jan. 2004
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BSI
BS616LV1622
ORDERING INFORMATION
BS616LV1622 X X Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
o
C ~ +70oC
C: +0
o
I: -40
C ~ +85oC
PACKAGE
T : TSOP1-48(12mmx20mm)
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
TSOP1-48 (12mm x 20mm)
R0201-BS616LV1622
10
Revision 2.1
Jan. 2004
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