BSI BS616L1615 User Manual

BSI

Very Low Power/Voltage CMOS SRAM
1M X 16 bit

(Dual CE Pins)

BS616LV1615

 FEATURES

• Vcc operation voltage : 4.5~5.5V

• Very low power consumption :
Vcc = 5.0V C-grade: 113mA (@55ns) operating current

I -grade: 115mA (@55ns) operating current

C-grade: 90mA (@70ns) operating current

I -grade: 92mA (@70ns) operating current

15uA (Typ.) CMOS standby current

• High speed access time :

-55 55ns

-70 70ns

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE2,CE1 and OE options

• I/O Configuration x8/x16 selectable by LB and UB pin

 PRODUCT FAMILY

PRODUCT FAMILY

OPERATING

TEMPERATURE

BS616LV1615FC +0O C to +70O C 4.5V ~ 5.5V 55 / 70

BS616LV1615FI -40O C to +85O C 4.5V ~ 5.5V 55 / 70

Vcc

RANGE

 DESCRIPTION

The BS616LV1615 is a high performance, very low power CMOS Static
Random Access Memory organized as 1,048,576 words by 16 bits and
operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 15uA at 5.0V/25oC and maximum access time of 55ns at 5.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable(CE1)
, active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
The BS616LV1615 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1615 is available in 48-pin BGA package.

SPEED

(ns)

55ns : 4.5~5.5V
70ns : 4.5~5.5V

POWER DISSIPATION

STANDBY

(ICCSB1, Max)

Vcc=5V

110uA

220

uA

Vcc=5V Vcc=5V

113mA 90mA BGA-48-0912

115mA 92mA BGA-48-0912

Operating

(ICC, Max)

55ns 70ns

PKG TYPE

 PIN CONFIGURATIONS

123456

A

LB OE A0 A1 A2

B

D8 UB

D9

C

VSS D11 A17 A7 D3 VCC

D

VCC D12

E

D14 D 13 A 14 A15

F

D15

G

A8

1

H

48-Ball CSP top View

A3 A4 CE1 D0

A5 A6 D1 D2

D10

NC

A12

A19.

A8 A9

A16 D4

A13 WE D7

A10 A11

CE2

VSS

D5 D6

NC

 BLOCK DIAGRAM

A4
A3
A2

A1

Address

A0

CE2
CE1

WE

OE

UB

LB

Input

Buffer

16

.

.

.

.

.

.
.

16

.

Control

D0

D15

A17

A16

A15
A14
A13
A12

Vcc

Vss

22

Data

Input

Buffer

Data

Output

Buffer

Row

Decoder

2048

16

16

Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.

R0201-BS616LV1615

1

Write Driver

Column Decoder

Address Input Buffer

A10

A11

Memory Array

2048 x 8192

Column I/O

Sense Amp

512

A9 A8 A7

8192

18

A5

A18

A6

Revision 2.1
Jan. 2004

A19

BSI

 PIN DESCRIPTIONS

Name Function

BS616LV1615

A0-A19 Address Input

CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input

WE Write Enable Input

OE Output Enable Input

LB and UB Data Byte Control Input

D0 - D15 Data Input/Output Ports

Vcc

Vss

These 20 address inputs select one of the 1,048,576 x 16-bit words in the RAM.

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

Lower byte and upper byte data input/output control pins.

These 16 bi-directional ports are used to read data from or write data into the RAM.

Power Supply

Ground

 TRUTH TABLE

MODE CE1 CE2 WE OE LB UB D0~D7 D8~D15 Vcc CURRENT

H

Not selected

(Power Down)

Output Disabled

Read L H H L

Write L H L X

 ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAM ETER RATING UNITS

TERM

V

BIAS

T

STG

T

PT

OUT

I

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

R0201-BS616LV1615

Terminal Voltage with
Respect to GND

Temperature Under Bias -40 to +85

Storage Temperature

Power Dissipation

DC Output Current 20 mA

X X X X X High Z High Z I

X

L X X X X High Z High Z I

L

H H H X X High Z High Z I

(1)

-0.5 to

Vcc+0.5

-60 to +150

1.0 W

, I

CCSB

CCSB1

, I

CCSB

CCSB1

CC

L L Dout Dout I

H L High Z Dout I

L H Dout High Z I

LL Din Din I

HL X Din I

LH Din X I

CC

CC

CC

CC

CC

CC

 OPERATING RANGE

RANGE

V

O

C

O

C

Commercial 0O C to +70O C 4.5V ~ 5.5V

Industrial -40O C to +85O C 4.5V ~ 5.5V

 CAPACITANCE

SYMBOL PARAMETER CONDITIONS MAX. UNIT

IN

C

DQ

C

1. This parameter is guaranteed and not 100% tested.

2

AMBIENT

TEMPERATURE

(1)

(TA = 25oC, f = 1.0 MHz)

Input
Capacitance
Input/Output
Capacitance

Vcc

VIN=0V 10 pF

I/O

V

=0V 12 pF

Revision 2.1
Jan. 2004

is

BSI

 DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85

PARAMETER

NAME

IL

V

V

IH

IL

I

LO

I

V

OL

PARAMETER TEST CONDITIONS MIN. TYP.

Guaranteed Input Low

(3)

Voltage

Guaranteed Input High

(3)

Voltage

Input Leakage Current Vcc = Max, V

Output Leakage Current

Vcc = Max, CE1 = V
OE = VIH, V

IN

= 0V to Vcc -- -- 1 uA

, or CE2 =

IH

I/O

= 0V to Vcc

Output Low Voltage Vcc = Max, IOL= 2mA

BS616LV1615

o

C )

ViL, or

Vcc=5V

Vcc=5V

Vcc=5V

(1)

MAX.

-0.5

2.2

--

--

0.8

Vcc+0.3

-- -- 1 uA

--

--

0.4 V

UNITS

V

V

V

CC

I

I

CCSB

CCSB1

I

OH

55ns

70ns

Vcc=5V

Vcc=5V

Vcc=5V

Vcc=5V

2.4

-- -- 115

-- -- 92

--

--

Output High Voltage Vcc = Min, IOH= -1mA

(4)

Operating Power Supply
Current

Standby Current-TTL

(5)

Standby Current-CMOS

CE1 = VILand CE2 =

, IDQ= 0mA, F = Fmax

CE1 = V

or CE2 =

IH

, IDQ= 0mA

≧

CE1

Vcc-0.2V or

≧

CE2 ≦0.2V ;V

≦

IN

or V

0.2V

Vcc - 0.2V

IN

VIH

(2)

V

IL

-- --

--

15

1. Typical characteristics are at TA = 25oC. 2. Fmax = 1/tRC.

3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

4. Icc_Max. is 113mA(@55ns) / 90mA(@70ns) during 0~70oC operation. 5. IccsB1 is 110uA at Vcc=5.0V and TA=70oC.

 DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85

SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.

V

I

CCDR

t

CDR

DR

Vcc for Data Retention

(3)

Data Retention Current

Chip Deselect to Data
Retention Time

t

Operation Recovery Time

R

CE1 ≧Vcc - 0.2V or CE2≦0.2V,

IN

V

Vcc - 0.2V or V

≧

CE1 ≧Vcc - 0.2V or CE2≦0.2V,

IN

V

Vcc - 0.2V or V

≧

See Retention Waveform

o

C )

(1)

MAX. UNITS

IN

0.2V

≦

IN

0.2V

≦

1.5 -- -- V

-- 1.5

5

0---- ns

(2)

T

RC

-- -- ns

1. Vcc = 1.5V, TA= + 25OC2.tRC= Read Cycle Time

3. IccDR(Max.) is 2.5uA at TA=70OC.

 LOW VCCDATA RETENTION WAVEFORM (1) ( CE1 Controlled )

2.5

220

V

mA

mA

uA

uA

Data Retention Mode

≥

Vcc

Vcc

VDR 1.5V

t CDR

≥

CE1 Vcc - 0.2V

CE1

 LOW VCCDATA RETENTION WAVEFORM (2) ( CE2 Controlled )

Data Retention Mode

Vcc

CE2

R0201-BS616LV1615

Vcc

t CDR

VIL

VDR ≧ 1.5V

CE2 ≦ 0.2V

3

Vcc

t R

VIHVIH

Vcc

t R

VIL

Revision 2.1
Jan. 2004

BSI

 AC TEST CONDITIONS

(Test Load and Input/Output Reference)

Input Pulse Levels

Input Rise and Fall Times

Input and Output
Timing Reference Level

Output Load

Vcc / 0V

1V/ns

0.5Vcc

CL = 30pF+1TTL
C

= 100pF+1TTL

L

BS616LV1615

 KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM H TO L

MAY CHANGE
FROM L TO H

,

DON T CARE:
ANY CHANGE
PERMITTED

DOES NOT
APPLY

MUST BE
STEADY

WILL BE
CHANGE
FROM H TO L

WILL BE
CHANGE
FROM L TO H

CHANGE :
STATE
UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE

 AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85

READ CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

AVQV

t

ELQV

t

ELQV

t

BA

t

GLQV

t

ELQX

t

BE

t

GLQX

t

EHQZ

t

BDO

t

GHQZ

t

AXOX

NOTE :

1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle .

BA is 70ns/55ns (@speed=70ns/55ns) without address toggle .

t

PARAMETER

NAME

t

RC

t

AA

t

ACS1

t

ACS2

(1)

t

BA

t

OE

t

CLZ

t

BE

t

OLZ

t

CHZ

t

BDO

t

OHZ

t

OH

DESCRIPTION UNIT

Read Cycle Time

Address Access Time

Chip Select Access Time

Chip Select Access Time

Data Byte Control Access Time

Output Enable to Output Valid

Chip Select to Output Low Z

Data Byte Control to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Data Byte Control to Output High Z

Output Disable to Output in High Z

Data Hold from Address Change

(CE2,CE1)

(CE2,CE1)

o

C )

(CE1)

(CE2)

(LB,UB)

(LB,UB)

(LB,UB)

CYCLE TIME : 70ns

Vcc = 4.5~5.5V Vcc = 4.5~5.5V

MIN. TYP. MAX.

CYCLE TIME : 55ns

MIN. TYP. MAX.

70 -- -- 55 -- -- ns

-- -- 70 -- -- 55 ns

-- -- 70 -- -- 55 ns

-- -- 70 -- -- 55 ns

-- -- 35 -- -- 30 ns

-- -- 35 -- -- 30 ns

10 -- -- 10 -- -- ns

5 -- -- 5 -- -- ns

5 -- -- 5 -- -- ns

-- -- 35 -- -- 30 ns

-- -- 35 -- -- 30 ns

-- -- 30 -- -- 25 ns

10 -- -- 10 -- -- ns

R0201-BS616LV1615

4

Revision 2.1
Jan. 2004

BSI

 SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

ADDRESS

D

(1,2,4)

t AA

t OH

OUT

BS616LV1615

t RC

t OH

READ CYCLE2

CE2

CE1

D

OUT

READ CYCLE3

ADDRESS

OE

CE2

CE1

(1,4)

(1,3,4)

t CLZ

(5)

t CLZ

t ACS2

t ACS1

t ACS1

(5)

t AA

t ACS2

t OLZ

t OE

t RC

t OHZ

t CHZ

(1,5)

t OH

(5)

t CHZ

(5)

LB,UB

D

OUT

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE1 = V

3. Address valid prior to or coincident with CE1 transition low.

4. OE = V

5. The parameter is guaranteed but not 100% tested.

R0201-BS616LV1615

IL .

t BE

t BA

IL and CE2 = VIH.

5

t BDO

Revision 2.1
Jan. 2004

BSI

 AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85

o

C )

BS616LV1615

WRITE CYCLE

JEDEC

PARAMETER

NAME

t

AVAX

t

E1LWH

t

AVWL

t

AVWH

t

WLWH

t

WHAX

t

BW

t

WLQZ

t

DVWH

t

WHDX

t

GHQZ

t

WHOX

NOTE :

1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle.

 SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

PARAMETER

NAME

t

WC

t

CW

t

AS

t

AW

t

WP

t

WR

(1)

t

BW

t

WHZ

t

DW

t

DH

t

OHZ

t

OW

(1)

DESCRIPTION UNIT

Write Cycle Time

Chip Select to End of Write

Address Setup Time

Address Valid to End of Write

Write Pulse Width

Write recovery Time

Date Byte Control to End of Write

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End of Write to Output Active

(CE2,CE1,WE) 0 -- -- 0 -- -- ns

(LB,UB) 30 -- -- 25 -- -- ns

t WC

CYCLE TIME : 70ns

Vcc = 4.5~5.5V

MIN. TYP. MAX.

CYCLE TIME : 55ns

Vcc = 4.5~5.5V

MIN. TYP. MAX.

70 -- -- 55 -- -- ns

70 -- -- 55 -- -- ns

0----0---- ns

70 -- -- 55 -- -- ns

35 -- -- 30 -- -- ns

-- -- 30 -- -- 25 ns

30 -- -- 25 -- -- ns

0----0---- ns

-- -- 30 -- -- 25 ns

5 -- -- 5 -- -- ns

ADDRESS

OE

CE2

CE1

LB,UB

WE

D

OUT

D

IN

t AS

(4,10)

t OHZ

(3)

t WR

(5)

(11)

(5)

t CW

t BW

(5)

t AW

t WP

(2)

(3)

t DH

t DW

R0201-BS616LV1615

6

Revision 2.1
Jan. 2004

BSI

BS616LV1615

WRITE CYCLE2

ADDRESS

CE2

CE1

LB,UB

WE

D

OUT

D

IN

(1,6)

t AS

(5)

(5)

(4,10)

t WHZ

t AW

t WC

t CW

t BW

t WP

(11)

t WR

(3)

(2)

t OW

(7) (8)

t DW

t DH

(8,9)

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.

WR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.

3. T

4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.

5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

OUT is the same phase of write data of this write cycle.

7. D

8. D

OUT is the read data of next address.

9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.

10. The parameter is guaranteed but not 100% tested.

CW is measured from the later of CE2 going high or CE1 going low to the end of write.

11. T

R0201-BS616LV1615

IL ).

7

Revision 2.1
Jan. 2004

BSI

BS616LV1615

 ORDERING INFORMATION

BS616LV1615 X X Z Y Y

SPEED

55: 55ns
70: 70ns

PKG MATERIAL

-: Normal
G: Green
P: Pb free

GRADE

C: +0oC ~ +70oC

I: -40oC ~ +85oC

PACKAGE

F :BGA-48-0912

Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.

 PACKAGE DIMENSIONS

1.4 Max.

3.375

e

VIEW A

SIDE VIEW

D0.1

D1

48 mini-BGA (9mm x 12mm)

0.05

±

0.25

E1

±

E0.1

2.625

NOTES:

1: CONTROLLING DIMENSIONS ARE IN MI LLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

N ED

48 12.0 9.0

E1D1 e

3.755.25 0.75

SOLDER BALL 0.35±0.05

R0201-BS616LV1615

8

Revision 2.1
Jan. 2004