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查询BS616LV1011供应商
BSI
Very Low Power/Voltage CMOS SRAM
64K X 16 bit
BS616LV1011
FEATURES
• Wide Vcc operation voltage : 2.4 ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 22mA (@55ns) operating current
Vcc = 5.0V C-grade : 48mA (55ns) operating current
• High speed access time :
-55 55ns
-70 70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
PRODUCT FAMILY
PRODUCT
FAMILY
BS616LV1011EC TSOP2-44
BS616LV1011AC
BS616LV1011EI TSOP2-44
BS616LV1011AI
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A15
A14
A13
A12
NC
A
B
C
D
E
F
G
H
I- grade : 23mA (@55ns) operating current
C-grade : 17mA (@70ns) operating current
I- grade : 18mA (@70ns) operating current
0.4uA (Typ.) CMOS standby current
I- grade : 50mA (55ns) operating current
C-grade : 36mA (70ns) operating current
I- grade : 38mA (70ns) operating current
1.3uA (Typ.) CMOS standby current
OPERATING
TEMPERATURE
O
C to +70
+0
O
C to +85
-40
1
2
3
4
5
6
7
8
9
BS616LV1011EC
10
11
BS616LV1011EI
12
13
14
15
16
17
18
19
20
21
22
12345
A0
A5
NC
NC
A15 IO5
A13 WE IO7
A9A8NC
A4A1CEA2IO0
A6
IO1
A7
IO3
NC
IO4
IO8LBUBOEA3
IO9
IO10
VSS
IO11
VCC
IO12
IO14
IO13 A14
IO15 NC A12
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
6
NC
IO2
VCC
VSS
IO6
NCA11A10
RANGE
O
C 2.4V ~ 5.5V 55/70 4uA 1.3uA 36mA
O
C 2.4V ~ 5.5V 55/70 8uA
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
Vcc
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The BS616LV1011 is a high performance , very low power CMOS Static
Random Access Memory organized as 65,536 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.4uA at 3V/25oC and maximum access time of 55ns at 3V/85oC.
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable(OE) and three-state output drivers.
The BS616LV1011 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1011 is available in the JEDEC standard 44-pin TSOP
Type II and 48-pin BGA package.
SPEED
(ns)
55ns:2.8~5.5V
70ns:2.5~5.5V
Vcc=5.0V Vcc=3.0V
POWER DISSIPATION
STANDBY
CCSB1
(I
, Max)
2.5uA
Operating
Vcc=5.0V
70ns
38mA
(ICC, Max)
Vcc=3.0V
70ns
17mA
18mA
BGA-48-0608
BGA-48-0608
BLOCK DIAGRAM
A8
A13
Address
A15
A14
A12
A7
A6
A5
A4
DQ0
DQ15
CE
WE
UB
Vcc
Gnd
.
.
.
.
.
.
.
.
OE
LB
Input
Buffer
Control
18
Data
16
Input
Buffer
16
Data
Output
Buffer
Row
Decoder
512
Memory Array
512 x 2048
2048
16
16
Column I/O
Write Driver
Sense Amp
Column Decoder
Address Input Buffer
A9
A3 A2 A1
A11
128
14
PKG TYPE
A0
A10
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV1011
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BSI
PIN DESCRIPTIONS
Name Function
BS616LV1011
A0-A15 Address Input
CE Chip Enable Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
These 16 address inputs select one of the 65,536 x 16-bit words in the RAM.
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Ports
Vcc
Gnd
Power Supply
Ground
TRUTH TABLE
MODE CE WE OE LB UB DQ0~DQ7 DQ8~DQ15 Vcc CURRENT
Not selected
(Power Down)
Output Disabled L H H X X High Z High Z I
Read L H L
Write L L X
H X X X X High Z High Z I
L L Dout Dout I
H L High Z Dout I
L H Dout High Z I
LL Din Din I
HL X Din I
LH Din X I
CCSB
, I
CCSB1
CC
CC
CC
CC
CC
CC
CC
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BS616LV1011
ABSOLUTE MAXIMUM RATINGS
SYMBOL PARAMETER RATING UNITS
TERM
V
cc
V
BIAS
T
STG
T
T
P
OUT
I
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
Terminal Voltage with
Respect to GND
Power Supply Voltage
Temperature Under Bias -40 to +85
Storage Temperature -60 to +150
Power Dissipation 1.0 W
DC Output Current 20 mA
(1)
-0.5 to
Vcc+0.5
-0.5 to
Vcc+0.5
OPERATING RANGE
RANGE
V
V
O
C
O
C
Commercial 0
Industrial -40
CAPACITANCE
SYMBOL PARAMETER CONDITIONS MAX. UNIT
C
C
1. This parameter is guaranteed and not 100% tested.
IN
DQ
Input
Capacitance
Input/Output
Capacitance
AMBIENT
TEMPERATURE
O
O
O
C to +70
C to +85
(1)
C2.4V ~ 5.5V
O
C2.4V ~ 5.5V
(TA = 25oC, f = 1.0 MHz)
VIN=0V 6 pF
I/O
V
=0V 8 pF
reliability.
DC ELECTRICAL CHARACTERISTICS ( TA = -40
PAR AM ETE R
NAME
IL
V
VIH
IL
I
ILO Output Leakage Current
VOL Output Low Voltage Vcc = Max, IOL = 2mA
VOH Output High Voltage Vcc = Min, IOH = -1mA
(6)
CC
I
CCSB
I
Standby Current-TTL CE = VIH, IDQ = 0mA
(5)
CCSB1
I
Standby Current-CMOS
1. Typical characteristics are at TA = 25oC. 2. Undershoot : -1.5V in case of pulse width ≦20ns.
3. Overshoot : Vcc+1.5V in case of pulse width
ccsB1_Max. is 1.3uA/4.0uA at Vcc=3.0V/5.0V and TA=70
5. I
PAR AM ETE R TEST CONDITIONS MIN. TYP.
Guaranteed Input Low
(2)
Voltage
Guaranteed Input High
Voltage
(3)
Input Leakage Current Vcc = Max, V
Vcc = Max, CE = V
V
= 0V to Vcc
I/O
Operating Power Supply
Current
CE = V
F = Fmax
, IDQ = 0mA,
IL
CE ≧ Vcc-0.2V,
≧ Vcc - 0.2V or VIN ≦ 0.2V
V
IN
≦20ns. 4. Fmax = 1/t
DATA RETENTION CHARACTERISTICS ( TA = -40
SYMBOL PAR AM ETE R TEST CONDITIONS MIN. TYP.
V
Vcc for Data Retention
DR
(3)
I
Data Retention Current
CCDR
t
CDR
t
R
1. Vcc = 1.5V, TA= + 25OC2.tRC= Read Cycle Time
ccDR_MAX. is 0.45uA at TA=70
3. I
Chip Deselect to Data
Retention Time
Operation Recovery Time
O
C.
CE ≧ Vcc - 0.2V
≧
V
IN
Vcc - 0.2V or VIN ≦ 0.2V
CE ≧ Vcc - 0.2V
≧
V
IN
Vcc - 0.2V or VIN ≦ 0.2V
See Retention Waveform
o
C to + 85oC )
(1)
= 0V to Vcc
IN
, or OE = VIH,
IH
(4)
o
C. 6. Icc_Max. is 23mA(@3V)/ 50mA(@5V) under 55ns operation.
70ns
o
C to + 85oC )
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
Vcc=3.0V
Vcc=5.0V
.
RC
-0.5 -- 0.8 V
2.0
2.2
-- Vcc+0.3 V
-- -- 1 uA
-- -- 1 uA
-- -- 0.4 V
2.4 -- -- V
-- -- 18
-- -- 38
-- -- 1
-- -- 2
-- 0.4 2.5
-- 1.3 8
(1)
MAX. UNITS
1.5 -- -- V
-- 0.15 0.8 uA
0 -- -- ns
(2)
T
RC
-- -- ns
R0201-BS616LV1011
3
MAX.
Vcc
UNITS
mA
mA
uA
Revision 1.0
Apr. 2004
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BSI
LOW VCCDATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
≥
Vcc
CE
Vcc
t CDR
VDR 1.5V
≥
CE Vcc - 0.2V
BS616LV1011
Vcc
t R
VIHVIH
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
Vcc / 0V
1V/ns
0.5Vcc
CL = 30pF+1TTL
= 100pF+1TTL
C
L
AC ELECTRICAL CHARACTERISTICS ( TA = -40
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV
t
BA
t
GLQV
t
E1LQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS
(1)
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
Data Hold from Address Change
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
o
C to + 85oC )
CYCLE TIME : 55ns
(Vcc = 2.8~5.5V)
MIN. TYP. MAX.
CYCLE TIME : 70ns
MIN. TYP. MAX.
55 -- -- 70 -- -- ns
-- -- 55 -- -- 70 ns
-- -- 55 -- -- 70 ns
(LB,UB)----25----35 ns
-- -- 25 -- -- 35 ns
10 -- -- 10 -- -- ns
(LB,UB) 10 -- -- 10 -- -- ns
5 -- -- 5 -- -- ns
-- -- 20 -- -- 25 ns
(LB,UB)----20----25 ns
-- -- 20 -- -- 25 ns
10 -- -- 10 -- -- ns
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
(Vcc = 2.5~5.5V)
UNIT
NOTE :
1. tBA is 25ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle.
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SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
ADDRESS
D
(1,2,4)
t AA
t OH
OUT
BS616LV1011
t RC
t OH
READ CYCLE2
CE
LB,UB
D
OUT
READ CYCLE3
ADDRESS
OE
CE
LB,UB
(1,3,4)
(1,4)
t CLZ
(5)
t ACS
t CLZ
(5)
t BA
t ACS
t BE
t BE
t AA
t OLZ
t BA
t OE
t RC
t BDO
t BDO
t OHZ
t CHZ
(1,5)
t CHZ
t OH
(5)
(5)
D
OUT
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = V
3. Address valid prior to or coincident with CE transition low.
4. OE = V
5. The parameter is guaranteed but not 100% tested.
R0201-BS616LV1011
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IL.
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BS616LV1011
AC ELECTRICAL CHARACTERISTICS ( TA = -40
o
C to + 85oC )
WRITE CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
E1LWH
t
AVWL
t
AVWH
t
WLWH
t
WHAX
t
BW
t
WLQZ
t
DVWH
t
WHDX
t
GHQZ
t
WHOX
NOTE :
1. tBW is 35ns/45ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle.
PARAMETER
NAME
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
(1)
t
BW
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
DESCRIPTION
Write Cycle Time
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write recovery Time
Date Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
(CE,WE)
(LB,UB)35----45---- ns
CYCLE TIME : 55ns
(Vcc = 2.8~5.5V)
MIN. TYP. MAX.
55 -- -- 70 -- -- ns
55
-- -- 70 -- -- ns
0----
55 -- -- 70 -- -- ns
35 -- -- 45 -- -- ns
0 -- -- 0 -- -- ns
-- -- 25 -- -- 30 ns
35 -- -- 40 -- -- ns
0 -- -- 0 -- -- ns
-- -- 20 -- -- 25 ns
5 -- -- 5 -- -- ns
CYCLE TIME : 70ns
(Vcc = 2.5~5.5V)
MIN. TYP. MAX.
0
-- -- ns
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
t WC
UNIT
ADDRESS
OE
CE
LB,UB
WE
D
OUT
D
IN
t AS
(4,10)
t OHZ
(3)
t WR
(11)
(5)
t CW
t BW
t AW
t WP
(2)
(3)
t DH
t DW
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BSI
BS616LV1011
WRITE CYCLE2
ADDRESS
CE
LB,UB
WE
D
OUT
D
IN
(1,6)
t AS
(5)
(4,10)
t WHZ
t AW
t WC
t CW
t WP
t BW
(11)
t WR
(3)
(2)
t OW
(7) (8)
t DW
t DH
(8,9)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. T
WR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
OUT is the same phase of write data of this write cycle.
7. D
8. D
OUT is the read data of next address.
9. If CE goes low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
CW is measured from the later of CE going low to the end of write.
11. T
R0201-BS616LV1011
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Revision 1.0
Apr. 2004
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BSI
BS616LV1011
ORDERING INFORMATION
BS616LV1011 X X Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
o
C ~ +85oC
I: -40
PACKAGE
E: TSOP2-44
A: BGA-48-0608
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
TSOP2-44
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PACKAGE DIMENSIONS (continued)
1.4 Max.
D1
e
VIEW A
BS616LV1011
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MI LLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
EN
8.0 6. 0
E1
48 3.75
5.25
E1D1
48 mini-BGA (6 x 8)
R0201-BS616LV1011
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Revision 1.0
Apr. 2004
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