Page 1
Ultra Low Power/High Speed CMOS SRAM
R0201
-BH62UV8001
Revision
1.1
Write Driver
Sense Amp
Address Input Buffer
A15 A13 A16 A2 A1
DQ7
12
A11
A10A9A8A7A6A5A4
A3
8
10
A17 A19
A14
CE1
CE2WEOE
CC
GND
A0 A18
G H F
D C B A 1 2 3 4 5 6 A9 A11 A10 A19 A12 A14 A13 A15 WE NC NC NC DQ7 A17
A7
VCC
DQ1
DQ5
A5 OE A3 A0 A6 A4 A1 A2 CE2 NC NC NC CE1
DQ4 NC
NC NC DQ0 VSS
DQ3 NC A18 NC A8
1M X 8 bit
Green package materials are compliant to RoHS
BH62UV8001
n FEATURES
Ÿ Wide VCC low operation voltage : 1.65V ~ 3.6V
Ÿ Ultra low power consumption :
VCC = 3.6V Operation current : 12mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 2.5uA (Typ.) at 3.0V/25OC
VCC = 1.2V Data retention current : 1.2uA (Typ.) at 25OC
Ÿ High speed access time :
-55 55ns (Max.) at VCC=1.65~3.6V
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE1, CE2 and OE options
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation, no clock, no refresh
Ÿ Data retention supply voltage as low as 1.0V
n DESCRIPTION
The BH62UV8001 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 1,048,576 by 8 bits
and operates in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical operating current of
1.5mA at 1MHz at 3.6V/25OC and maximum access time of 55ns at
1.65V/85OC.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH62UV8001 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BH62UV8001 is available in DICE form and 48-ball BGA
package.
n POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BH62UV8001DI DICE
BH62UV8001AI
OPERATING
TEMPERATURE
Industrial
-40OC to +85OC
STANDBY
(I
, Max)
CCSB1
VCC=3.6V VCC=1.8V
1MHz 10MHz f
VCC=3.6V VCC=1.8V
15uA 12uA 2mA 6mA 12mA 1.5mA 5mA 8mA
Operating
(ICC, Max)
1MHz 10MHz
Max.
f
Max.
PKG TYPE
BGA-48-0608
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A
Address
Input
Buffer
Decoder
Row
1024
Memory Array
1024 x 8192
E
VCC
DQ2
NC
A16
DQ6
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
8
8
Data
Input
Buffer
Data
Output
Buffer
8
V
Control
8192
Column I/O
1024
Column Decoder
10
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
Detailed product characteristic test report is available upon request and being accepted.
1
May 2006
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BH6
2U
V
8001
Revision
1.1
. With the
data will be present on the DQ pins and they
n PIN DESCRIPTIONS
Name Function
A0-A19 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
DQ0-DQ7 Data Input/Output
Ports
VCC
VSS
n TRUTH TABLE
MODE
Chip De-selected
(Power Down)
These 20 address inputs select one of the 1,048,576 x 8 bit in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
The write enable input is active LOW and controls read and write operations
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive,
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
8 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
CE1
H X X X
X L X X
CE2
WE OE
I/O OPERATION VCC CURRENT
High Z I
CCSB
, I
CCSB1
Output Disabled L H H H High Z ICC
Read L H H L D
Write L H L X DIN ICC
NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
n ABSOLUTE MAXIMUM RATINGS
(1)
n OPERATING RANGE
SYMBOL PARAMETER RATING UNITS
V
TERM
T
BIAS
T
PT Power Dissipation 1.0 W
I
OUT
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. –2.0V in case of AC pulse width less than 30 ns
Terminal Voltage with
Respect to GND
Temperature Under
Bias
Storage Temperature -60 to +150
STG
DC Output Current 20 mA
(2)
-0.5
to 4.6V V
-40 to +125
O
C
O
C
n CAPACITANCE
ICC
OUT
RANG
Industrial -40OC to + 85OC 1.65V ~ 3.6V
AMBIENT
TEMPERATURE
(1)
(TA = 25OC, f = 1.0MHz)
VCC
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
CIN
CIO
1. This parameter is guaranteed and not 100% tested.
Input
Capacitance
Input/Output
Capacitance
VIN = 0V 6 pF
V
= 0V 8 pF
I/O
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8001
Revision
1.1
Data Retention Mode
V
CC
t
CDR
V
CC
n DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
PARAMETER
NAME
PARAMETER TEST CONDITIONS MIN. TYP.
(1)
MAX. UNITS
VCC
VIL
VIH
IIL
ILO
VOL
VOH
ICC
I
CC1
I
CCSB
I
CCSB1
Power Supply 1.65 -- 3.6 V
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Operating Power Supply
Current
Standby Current – TTL
Standby Current – CMOS
VIN = 0V to VCC,
CE1 = VIH or CE2 = VIL
V
= 0V to V
I/O
,
CC
CE1 = VIH or CE2 = VIL or OE = VIH
VCC = Max, IOL = 0.1mA
VCC = Max, IOL = 2.0mA
VCC = Min, I
VCC = Min, I
= -0.1mA
OH
= -1.0mA
OH
CE1 = VIL, CE2 = VIH,
IDQ = 0mA, f = F
MAX
(4)
CE1 = VIL and CE2 = VIH,
IDQ = 0mA, f = 1MHz
CE1 = VIH, or CE2 = VIL,
IDQ = 0mA
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC-0.2
1. Typical characteristics are at TA=25OC and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. F
=1/t
RC.
MAX
5. VCC=3.0V
n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.
-0.3
1.4
2.2
(2)
--
-- VCC+0.3
0.4
0.6
(3)
-- -- 1 uA
-- -- 1 uA
-- --
2.4
--
--
-- --
--
2.5
-- -- V
6 8
8 12
1.0 1.5
1.5 2.0
2.0 12
(5)
0.2
0.4
0.5
1.0
15
(1)
MAX. UNITS
V
V
V
mA
mA
mA
uA
n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
R0201-BH62UV8001
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
See Retention Waveform
I
CCDR
t
VDR
CDR
tR
VCC for Data Retention
(3)
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
1. Typical characteristics are at TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
V
CC
V
CE1
IH
VDR≧1.0V
CE1≧VCC - 0.2V
3
VCC=1.2V
1.0 -- -- V
-- 1.2 7.0 uA
0 -- -- ns
(2)
t
-- -- ns
RC
t
R
V
IH
May 2006
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BH6
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V
8001
Revision
1.1
(1)
1
TTL
→ ←
CC
GND
90%
→ ←
Data Retention Mode
V
CC
V
CC
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
V
CC
t
CDR
CE2
V
IL
VDR≧1.0V
CE2≦0.2V
n AC TEST CONDITIONS
(Test Load and Input/Output Reference)
n KEY TO SWITCHING WAVEFORMS
Input Pulse Levels VCC / 0V
WAVEFORM INPUTS OUTPUTS
t
R
V
IL
Input Rise and Fall Times 1V/ns
Input and Output Timing
Reference Level
Output Load
Output
C
L
0.5Vcc
t
, t
, t
, t
CLZ1
t
CHZ2
CLZ2
, t
, t
OHZ
WHZ
OLZ
CHZ1
, tOW
,
CL = 5pF+1TTL
Others CL = 30pF+1TTL
ALL INPUT PULSES
V
Rise Time:
1V/ns
90%
10%
Fall Time:
1V/ns
10%
1. Including jig and scope capacitance.
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
JEDEC
PARAMETER
NAME
t
tRC
AVAX
t
tAA
AVQX
t
t
E1LQV
t
t
E2LQV
t
tOE
GLQV
t
t
E1LQX
t
t
E2LQX
t
t
GLQX
t
t
E1HQZ
t
t
E2HQZ
t
t
GHQZ
t
tOH
AVQX
PARANETER
NAME
ACS1
ACS2
CLZ1
CLZ2
OLZ
CHZ1
CHZ2
OHZ
DESCRIPTION
Read Cycle Time 55 -- -- ns
Address Access Time -- -- 55 ns
Chip Select Access Time (CE1)
Chip Select Access Time (CE2)
Output Enable to Output Valid -- -- 30 ns
Chip Select to Output Low Z (CE1)
Chip Select to Output Low Z (CE2) 10 -- -- ns
Output Enable to Output Low Z 5 -- -- ns
Chip Select to Output High Z (CE1)
Chip Select to Output High Z (CE2)
Output Enable to Output High Z -- -- 25 ns
Data Hold from Address Change 10 -- -- ns
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CYCLE TIME : 55ns
MIN. TYP. MAX.
MUST BE
STEADY
WILL BE CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “L” TO “H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
UNITS
-- -- 55 ns
-- -- 55 ns
10 -- -- ns
-- -- 25 ns
-- -- 25 ns
R0201-BH62UV8001
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8001
Revision
1.1
OH
AA
(5)
OUT
CE2 CE1
ACS2
ACS1
(5)
OH
RC
OE
(5)
(2,5
)
OE
(5)
ACS1
CHZ1
(1,5)
(5)
OLZ
AA
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
t
ADDRESS
t
t
OH
RC
D
OUT
READ CYCLE 2
(1,3,4)
t
D
t
t
CLZ
READ CYCLE 3
(1, 4)
ADDRESS
t
t
CE1
CE2
t
CLZ1
D
OUT
t
CLZ2
t
t
ACS2
t
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
t
t
, t
CHZ1
CHZ2
t
t
t
OHZ
t
t
CHZ2
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8001
Revision
1.1
(3)
(11)
(11)
(2)
(4,10)
AS
(3)
DH
tDW
OE
(5) (5)
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
WRITE CYCLE
JEDEC
PARAMETER
NAME
t
tWC
AVAX
t
tAS
AVWL
t
tAW
AVWH
t
tCW
ELWH
t
tWP
WLWH
t
t
WHAX
t
t
E2LAX
t
t
WLQZ
t
tDW
DVWH
t
tDH
WHDX
t
t
GHQZ
t
tOW
WHQX
PARANETER
NAME
WR1
WR2
WHZ
OHZ
DESCRIPTION
Write Cycle Time 55 -- -- ns
Address Set up Time 0 -- -- ns
Address Valid to End of Write 45 -- -- ns
Chip Select to End of Write 45 -- -- ns
Write Pulse Width 35 -- -- ns
Write Recovery Time (CE1, WE)
Write Recovery Time (CE2)
Write to Output High Z -- -- 20 ns
Data to Write Time Overlap 25 -- -- ns
Data Hold from Write Time 0 -- -- ns
Output Disable to Output in High Z -- -- 25 ns
End of Write to Output Active 5 -- -- ns
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1
(1)
t
WC
CYCLE TIME : 55ns
MIN. TYP. MAX.
0 -- -- ns
0 -- -- ns
UNITS
ADDRESS
CE1
CE2
WE
D
OUT
D
IN
t
WR1
t
CW
t
CW
t
AW
t
t
t
OHZ
WP
t
WR2
t
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Revision
1.1
t
WC
(11)
(11)
(2)
(4,10)
AS
(3)
DH
tDW
OUT
(5) (5)
OW
(7) (8) (8,9)
WRITE CYCLE 2
(1,6)
ADDRESS
CE1
t
CW
CE2
WE
t
t
WHZ
D
t
CW
t
AW
t
WP
t
WR2
t
t
D
IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE
low. All signals must be active to initiate a write and any one signal can terminate a write by
going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. D
is the same phase of write data of this write cycle.
OUT
8. D
is the read data of next address.
OUT
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11. tCW is measured from the later of CE1 going low or CE2 going high to the end of write.
R0201-BH62UV8001
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V
8001
Revision
1.1
PACKAGE
A
GRADE
I: -40oC ~ +85
C
SPEED
PKG MATERIAL
G: Green
, RoHS Compliant
1.
Max.
e
E1
BALL PITCH e = 0.75
n ORDERING INFORMATION
BH62UV8001 X X Z Y Y
55: 55ns
-: Normal
o
D: DICE
: BGA-48-0608
Note:
Brilliance Semiconductor Inc. (BSI) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
2
D1
VIEW A
48 mini-BGA (6 x 8)
D
8.0 6.0
E N
5.25
E1D1
3.75
48
R0201-BH62UV8001
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8001
Revision
1.1
n Revision History
Revision No. History Draft Date Remark
1.0 Initial Production Version May 10,2006 Initial
1.1 Change I-grade operation temperature range May. 25, 2006
- from –25OC to –40OC
R0201-BH62UV8001
9
May 2006
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