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Broadcom Corporation reserves the right to make changes to the products or information contained
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Epigram, InsideLine, and iLine10 are trademarks of Broadcom Corporation.
This program runs in two modes: Manufacturing mode and Engineering mode. The mode is
determined with the command line option or the configuration file. When the program is
running in manufacturing mode, it starts to run all tests in the configuration. If it detects an
error, it displays an error and exits the program. When the program is in engineering mode,
it prompts user to enter commands. The commands are explained in the later chapters. This
document provides the information on configuration file specification, command line options
and engineering diagnostic commands on Broadcom NetXtreme Ethernet adapter, in
particular to check out the functionality of the BCM5700 Family of Ethernet controllers and
its related components. In general, this program has a set of default configuration. It is
overwritten by configuration file. The command line option overwrites both default and the
configuration files.
The tests are divided into seven groups: Register Tests, Memory Tests, Miscellaneous Tests, Data
Tests, Cable Tests, APE Register Tests and APE Diagnostics Tests. They numbered as group ‘A’,
‘B’, ‘C’, ‘D’, ‘E’, ‘F’, and ‘G’.
Note: For few special scenairos, not all tests are supported. Refer to online help for more
information.
The lists of each group are shown as below. Their detailed explanation will be described later.
Group A.
A1. Indirect Register Test
A2. Control Register Test
A3. Interrupt Test
A4. BIST
A5. PCI Cfg Register Test
A6. Serial Number Reg Test
A7. Power Register Test
A8. MailBox Register Test
Groupt B.
B1. Scratch Pad Test
B2. BD SRAM Test
B3. DMA SRAM Test
B4. MBUF SRAM Test
B5. MBUF SRAM via DMA Test
B6. External SRAM Test
B7. CPU GPR SRAM Test
Function: Each Register specified in the configuration contents is tested for read only bit and
read/write bit defines. The test writes zeroes and ones into the test bits to insure the read only
bits are not changed, and read/write bits are changed accordingly.
Default: Enabled.
3.2.3 A3. Interrupt Test
Command: intrtest
Function: This test verifies the interrupt functionality. It enables interrupt and waits for
interrupt to occur. It waits for 500ms and reports error if could not generate interrupts.
Default: Enabled
3.2.4 A4. BIST
Command: bist
Function: Hardware Built-In-Self-Test (BIST). This test initiates BIST, and wait for the test
result returned by hardware.
Default: Enabled
3.2.5 A5. PCI Cfg Register Test
Command: pcicfg
Function: This test verifies the access integrity of the PCI config registers.
Default: Enabled
3.2.6 A6. Serial Number Reg Test
Command: serial
Function: Tests the PCI-E Serial Number capabilities registers on chips that support the
Serial Number capability. This command is supported on 5751Cx, 5755, 5787.
Function: Tests the PCI-E Power capabilities registers on chips that support the Power
capability. This command is supported on 5751Cx, 5755 and 5787 only.
Default: Enabled.
3.2.8 A8. Mailbox Register Test
Function: This test verifies the access integrity of the Mailbox registers. This test is for
5719 and 5720 only.
Default: Enabled
3.3 Memory Test - B Group
3.3.1 B1. Scratch Pad Test
Command: memtest -s
Function: This test tests the scratch pad SRAM on board. The following tests are
performed:
Data Pattern Test: Write test data into SRAM, read back to ensure data is correct. The test
data used is 0x00000000, 0xffffffff, 0xaa55aa55, and 0x55aa55aa.
Alternate Data Pattern Test: Write test data into SRAM. Write complement test data into
next address. Read back both data to insure the data is correct. After the test, the program
reads back data one more time to insure the data stays correct. The test data used is
0x00000000, 0xffffffff, 0xaa55aa55, and 0x55aa55aa.
Address Test: Write each address with unique increment data. Read back data to insure
data is correct. After fill the entire data with the unique data, the program reads back data
again to insure data stays the same.
Walking Bit Test: For each address location, starting at bit 0, each bit is set, tested and
then shifted left by one. This process is repeated for each of the 32 bits in each address
location in the entire memory test range.
Pseudo Random Data Test: A pre-calculated pseudo random data is used to write a unique
data into each test RAM. After the first pass the test, the program reads back one more time
to insure data stays correct.
Function: This test tests the BD SRAM. This performs exact the same way of testing as
described in B1, the Scratch Pad Test.
Default: Enabled
3.3.3 B3. DMA SRAM Test
Command: memtest -d
Function: It tests DMA SRAM by performing the tests described in test B1, the Scratch Pad
Test.
Default: Enabled
3.3.4 B4. MBUF SRAM Test
Command: memtest -m
Function: It tests MBUF SRAM by performing the tests described in test B1, the Scratch
Pad Test.
Default: Enabled
3.3.5 B5. MBUF SRAM via DMA Test
Command: memtest -x
Function: Eight test pattern data are used in the test. They are described below. A 0x1000
sized data buffer is used for this test. Before each pattern test, the buffer is initialized and
filled with the test pattern. It then, performs size 0x1000 transmit DMA from host buffer to
NIC MBUF memory. Verify the data integrity in MBUF against host memory and repeat the
DMA for the entire MBUF buffer. Then it performs receive DMA from NIC to host. The
0x1000-byte test buffer is cleared to zero before each receive-DMA. Verify the data integrity
and test is repeated for the entire MBUF SRAM range.
Test Pattern Description
“16 00's 16 FF's” Full the entire host DMA buffer with 16 bytes of 00’s and then 16 bytes
of FF’s.
“16 FF's 16 0's” Full the entire host DMA buffer with 16 bytes of 00’s and then 16 bytes
of FF’s.
“32 00's 32 FF's” Full the entire host DMA buffer with 32 bytes of 00’s and then 32 bytes
of FF’s.
“32 FF's 32 00's” Full the entire host DMA buffer with 32 bytes of FF’s and then 32 bytes
of 00’s.
“00000000's” Full the entire host DMA buffer with all zeros.
“FFFFFFFF's” Full the entire host DMA buffer with all FF’s.
“AA55AA55's” Full the entire host DMA buffer with data 0xAA55AA55.
“55AA55AA's” Full the entire host DMA buffer with data 0xAA55AA55.
Function: It tests external SRAM by performing the tests described in test B1, the Scratch Pad Test.
Default: Disabled
3.3.7 B7. CPU GPR Test
Command: memtest -b
Function: This test tests the CPU General Purpose Registers. This performs exact the same way of testing as described in B1 over 3 voltages (1.1V, 1.2V, 1.3V).
Default: Enable
3.4 Misc Tests – C Group
3.4.1 C1. EEPROM Test
Command: setest
Function: An increment test data is used in EEPROM test. It fills the test data into the test
range and read back to verity the content. After the test, it fills data with zero to clear the
memory.
Default: Enabled
3.4.2 C2. CPU Test
Command: cputest
Function: This test opens the file cpu.bin. If file exists and content is good, it loads code to
rx and tx CPU and verifies CPU execution.
Default: Enabled
3.4.3 C3. DMA Test
Command: dmatest
Function: Both high and low priorities DMA are tested. It moves data from host memory to
NIC SRAM, verifies data, and then moves data back to host memory again to verify data.
Function: The function is identical to A2. Control Register Test. Each Register specified in
the configuration contents read only bit and read/write bit defines. The test writing zero and
one into the test bits to insure the read only bits value are not changed, and read/write bits
are changed accordingly.
Default: Enabled.
Default Register table
The test will try to read the register configuration file ‘miireg.txt’ for the register defines. If
the file does not exists, the following table is used:
Function: It saves the content of VPD first before perform the test. Once it is done, it writes
one of the five pattern test data, 0xff, 0xaa, 0x55, increment data, or decrement data, into
VPD memory. By default, increment data pattern is used. It writes and reads back the data
for the entire test range, and then restores the original content.
Setting reset bit, poll for self-clearing. Verify reset value of registers.
2. Event Mapping Test
Setting SMB_ATTN bit. By changing ASF_ATTN LOC bits, verify the mapping bits in
TX_CPU or RX_CPU event bits.
3. Counter Test
Clear WG_TO, HB_TO, PA_TO, PL_TO, RT_TO bits by setting those bits. Make sure
the bits clear.
Clear Timestamp Counter. Writing a value 1 into each PL, PA, HB, WG, RT counters.
Set TSC_EN bit.
Poll each PA_TO bit and count up to 50 times. Check if PL_TO gets set at the end of 50
times. Continue to count up to 200 times. Check if all other TO bits are set and verify
Timestamp Counter is incremented.
Default: Enabled
3.4.7 C7. Expansion ROM Test
Command: romtest
Function: This function tests the ability to enable/disable/access the expansion
rom on the device.
Default: Enabled
3.4.8 C8. CPU Fetch Test
Command: cpufetch
Function: Test the CPU instruction-fetch logic a 100 times on 5705 and later devices. The
voltage is also varied to 1.1V and 1.3V on devices that support voltage variation.
Default: Enabled
3.5 Data Tests – D Group
3.5.1 D1. Mac Loopback Test
Command: pkttest -m
Function: This is internal loopback data transmit/receive test. It initializes MAC into
internal loopback mode, and transmits 200 packets. The data should be routed back to
receive channel and receive by the receive routine, which verifies the integrity of data. One
Giga bit rate is used for this test.
Note: This test is not available for 5718, 5719 and 5720.
3.5.2 D2. Phy Loopback Test
Command: pkttest -p
Function: This test is same as D1. Mac Loopback Test, except the data is routed back via
physical layer device. One Giga bit rate is used for this test.
Please note if the device supports E-Switch, such as 5756, the test is performed on both
laptop mode and docking mode. To perform the test only on the default port, two methods
can be used: 1. command line option ‘-disableeswitch’; 2. ‘eswitch –f’ in engineering mode
before the test.
Default: Enabled
3.5.3 D3. RJ45 Loopback Test
Command: pkttest -e
Function: This is external loopback test. From the UUT point of view, no loopback mode is
configured. The data expected to be routed back by RJ45 loopback connector. 10M/s,
100M/s, and 1000M/s are used for this test.
Please note if the device supports E-Switch, such as 5756, the test is performed on both
laptop mode and docking mode. To perform the test only on the default port, two method
can be used: 1. command line option ‘-disableeswitch’; 2. ‘eswitch –f’ in engineering mode
before the test.
Default: Disabled
3.5.4 D4. 1G False Carrier Test
Command: nictest d4
Function: This test executes the same procedure as test D3 and tests to see if a false carrier
was detected at the end of the test. The –l200, –dispgbpkt, -disppkt and –errlimit commandline options were added to configure a number of operational parameters. The details of the
command line options are provided in the “COMMAND LINE OPTION PARAMETERS”
section.
Please note if the device supports E-Switch, such as 5756, the test is performed on both
laptop mode and docking mode. To perform the test only on the default port, two method
can be used: 1. command line option ‘-disableeswitch’; 2. ‘eswitch –f’ in engineering mode
before the test.
Function: This function tests the auto-polling and phy-interrupt capabilities. These are the
functionalities of the phy.
Default: Enabled
3.5.6 D6. MSI Test
Command: msitest
Function: Testing Message Signaled Interrupt Function to see if it handles this interrupt
correctly.
Default: Enabled
3.5.7 D7. E-Switch Test
Command: nictest d7
Function: This function tests the E-Switch Ethernet porting switching hardware.
Default: Enabled (available only for NetXtreme controllers with E-Switch support)
3.5.8 D8. SADB Test
Command: nictest d8
Function: This function tests the Security Association Data Base hardware in IPsec
supported NetXtreme Ethernet controllers.
Default: Enabled (available only on NetXtreme controllers with IPSec support)
3.5.9 D9. IPsec Loopback Test
Command: nictest d9
Function: An external loopback test is performed at 10/100/1000 Mbits/s using IPsec
encrypted packets. Various hardware supported encryption ciphers are used to encrypt and
decrypt packets and verify the proper operation of the IPsec hardware.
A zero length loopback connector is placed at the RJ45 connector of the LOM/NIC. After
running the loopback test at 1000 Mbits/s the line signal quality is tested order to catch line
faults (shorts or opens). This test is used during manufacturing in order to detect
board/system build issues on the line/analog side of the Ethernet controller.
Default: Disabled (available only on NetXtreme controllers with IPSec support)
3.6 Carrier Tests
3.6.1 E1. 1G Wire Open/Short (** ZERO LEN LB RJ45 **) Test
Command: nictest e1
Function: An external loopback test is performed at 10/100/1000 Mbits/s. A zero length
loopback connector is placed at the RJ45 connector of the LOM/NIC. After running the
loopback test at 1000 Mbits/s the line signal quality is tested order to catch line faults (shorts
or opens). This test is used during manufacturing in order to detect board/system build issues
on the line/analog side of the Ethernet controller.
Default: Disabled
NOTE: The following tests in test groups F and G are only enabled for NetXtreme Ethernet
Controllers which support the Application Processing Engine (APE).
3.7 APE Registers Tests – F Group
3.7.1 F1. Indirect APE Ctrl Register Test
Command: nictest f1
Function: Using indirect addressing method, incremented data is written into APE control
registers and read back for verification. The memory read/write is done 100 times while
incrementing test data.
Default: Disabled
3.7.2 F2. APE Control Register Test
Command: nictest f2
Function: Each Register specified in the APE control register block is tested for read only
bits and read/write bits. The test writes zeroes and ones into the test bits to insure the read
only bits are not changed, and read/write bits are changed accordingly.
Function: Using indirect addressing method, incremented data is written into APE Peripheral
registers and read back for verification. The memory read/write is done 100 times while
incrementing test data.
Default: Enabled
3.7.4 F4. APE Peripheral Register Test
Command: nictest f4
Function: Each Register specified in the APE Peripheral register block is tested for read
only bits and read/write bits. The test writes zeroes and ones into the test bits to insure the
read only bits are not changed, and read/write bits are changed accordingly.
Default: Enabled
3.7.5 F5. APE Scratch Pad Test
Command: nictest f5
Function: This test tests the APE scratch pad SRAM on the APE enabled NetXtreme
controllers. The following tests are performed:
Data Pattern Test: Write test data into SRAM, read back to ensure data is correct. The test
data used is 0x00000000, 0xffffffff, 0xaa55aa55, and 0x55aa55aa.
Alternate Data Pattern Test: Write test data into SRAM. Write complement test data into
next address. Read back both data to insure the data is correct. After the test, the program
reads back data one more time to insure the data stays correct. The test data used is
0x00000000, 0xffffffff, 0xaa55aa55, and 0x55aa55aa.
Address Test: Write each address with unique increment data. Read back data to insure
data is correct. After filling the entire memory length with the unique data, the program reads
back the data again to insure data stays the same.
Walking Bit Test: For each address location, starting at bit 0, each bit is set, tested and
then shifted left by one. This process is repeated for each of the 32 bits in each address
location in the entire memory test range.
Pseudo Random Data Test: A pre-calculated pseudo random data is used to write a unique
data into each test RAM. After the first pass the test, the program reads back one more time
to insure data stays correct.
Function: Performs memory data verification tests on the APE Shared Memory. This test
uses the same the method of testing as described in F5. APE Scratch Pad Test.
Default: Enabled
3.7.7 F7. APE Shared Memory Indirect Access Test
Command: nictest f7
Function: Performs memory data verification tests using Indirect Addressing Method, on the
APE Shared Memory. This test uses the same the method of testing as described in F5. APE
Scratch Pad Test.
Default: Enabled
3.7.8 F8. APE Mutex Register Test
Command: nictest f8
Function: Each of the registers in the APE Mutex Register block is tested to verify that
each bit set in the Mutex Request register can acquire a corresponding grant bit in its paired
Mutex Grant register. After each grant bit is set it is written with back to verify the grant bit
can be cleared.
Default: Disabled
3.7.9 F9. APE Timers Test
Command: nictest f9
Function: This test each of the APE internal timer registers from the host interface. The
test verifies that the APE timers are functioning and within acceptable tolerances.
Default: Disabled
3.8 APE Diagnostics Tests – G Group
3.8.1 G1. APE CPU Memory Test
Command: nictest g1
Function: This test executes a series of memory tests using the APE CPU.
Data Pattern Test: Write test data into SRAM, read back to ensure data is correct. The test
data used is 0x00000000, 0xffffffff, 0xaa55aa55, and 0x55aa55aa.
Alternate Data Pattern Test: Write test data into SRAM. Write complement test data into
next address. Read back both data to insure the data is correct. After the test, the program
reads back data one more time to insure the data stays correct. The test data used is
0x00000000, 0xffffffff, 0xaa55aa55, and 0x55aa55aa.
Address Test: Write each address with unique increment data. Read back data to insure
data is correct. After fill the entire data with the unique data, the program reads back data
again to insure data stays the same.
WalkingOne bit Test: For each address. Data one is written and read back for testing. Then
shift the data left one bit, so the data becomes two and do the same test again. It repeats for
32 times until the test bit is shifted out of test data. The same is test is repeated for entire test
range.
Pseudo Random Data Test: A pre-calculated pseudo random data is used to write a unique
data into each test RAM. After the first pass the test, the program reads back one more time
to insure data stays correct.
Default: Enabled
3.8.2 G2. APE CPU Packet Test
Command: nictest g2
Function: An Ethernet packet is transmitted via internal loopback from the APE CPU and
verified for data integrity and that packet interrupts are generated.
Default: Enabled
3.8.3 G3. APE CPU SMBus Loopback Test
Command: nictest g3
Function: This test sends and receives SMBus messages from the APE CPU via loopback
on the SMBus controllers and verifies that correct data was received. (Requires loopback
jumpers to be installed).
Default: Disabled
3.8.4 G4. APE CPU GPIO Register Test
Command: nictest g4
Function: This test writes zeroes and ones to the GPIO output pins via the APE CPU to
insure the bits are changed accordingly and that GPIO state change interrupts are generated.
Function: In this test the APE CPU writes to the APE event registers to verify that each
event state can generate a corresponding interrupt.
Default: Enabled
3.8.6 G6. APE CPU Mutex Register Test
Command: nictest g6
Function: Each of the registers in the APE Mutex Register block is tested from the APE
CPU. This test verifies that each bit set in the Mutex Request register can acquire a
corresponding grant bit in its paired Mutex Grant register. After each grant bit is set it is
written with back to verify the grant bit can be cleared.
Default: Enabled
3.8.7 G7. APE CPU Timers Test
Command: nictest g7
Function: This test each of the APE internal timer registers using the APE CPU. The test
verifies that the timers are functioning and within acceptable tolerances.
Default: Enabled
3.8.8 G8. APE CPU GRC Reset Test
Command: nictest g8
Function: This test verifies that the GRC port interrupt function can be detected via the
APE CPU.
Default: Enabled
3.8.9 G9. APE USB Test (UEFI only)
Command: nictest g9
Function: This test verifies that the APE USB port can be detected from the host controller
by executing a series USB descriptor query commands. This test is only available on the
UEFI version of B57diag.
When users invoke this program, a set of option parameter can be used to overwrite the configuration
file or the default configuration. This section summarizes the options. The options are case sensitive.
-putil Call “b57putil.exe” utility to unload PXE driver.
When "-putil" was entered, diag will call another application "b57putil.exe". "b57putil.exe"
will unload PXE and such that diag can have full control over the device. This option switch
should be used when updating firmware with "-firmall" option switch via PXE connection.
-seldev <VID_DID> option to select devices that match VID and DID
Use this option to select target devices. Other devices, which have different VIDs and DIDs,
will not be selected and listed. This option switch can be used along with “-firm” and “firmall” option switches.
Example: a:\b57diag –b57eng –seldev 14e411677
-uump <filename> used for field program of UMP firmware
The feature is used to execute a field upgrade of UMP firmware. The firmware is
programmed into a/the device/s specified by “-c” option switch if UMP firmware is
originally loaded in NVRAM
-dir used for displaying file directory in NVRAM
The feature is used to display file directory in NVRAM. The file directory in the
NVRAM of device/s specified by"-c" option switch will be display. If no "-c" option
switch has been entered, the file directory of all detected devices will be
displayed. In order to log the file directory to a log file, "-l" option switch option
must be entered BEFORE "-dir" option switch. Since this is a single function
command, the will be no "nictest" or other functions will be preformed.
-pump <file> Program UMP firmware
This option needs to follow the –e and –c options. If this option is entered, the program will
retrieve the UMP firmware filename from the command line then it will start programming.
Example:
b57diag –e <code> -c 0 –pump ee5714c1.00
-pump1 <file> Program UMP firmware only
The feature is used to execute a field upgrade of NVRAM to add UMP firmware. The
firmware is programmed into a/the device/s specified by “-c” option switch.
This option needs to follow the –e and –c options. If this option is entered, the program will
retrieve the ISCSI firmware filename from the command line then it will start programming.
Example:
b57diag –e <code> -c 0 –piscsi iscsi.bin
-piscsicfg Force program ISCSI CFG firmware
If this option is entered, it will force program the ISCSI CFG firmware to NVRAM. This
option must be used along with –piscsi option.
-piscsi1 <filename> used for field program of ISCSI firmware
The feature is used to execute a field upgrade of NVRAM to add ISCSI firmware. The
firmware is programmed into a/the device/s specified by “-c” option switch.
-smbaddr <hex1> | <hex2> | …….| <hexn> used for programming SMBus Address for
ASF/IPMI firmware.
The feature will allow user to program SMBus Address for ASF/IPMI firmware. This
switch can take multiple parameters in HEX.
Example
1. -smbaddr A4 (SMB Address = 0xA4)
2. -smbaddr A4 A6 (SMB Address for 1st device=0xA4 and 2nd device = 0xA6)
This switch must be used along with -c option to indicate the target device.
Example:
b57diag -c 0 3 6 -smbaddr A4 A6 A8 -t abcd.
b57diag –c 0 –e b57kia –pasf asf.bin –smbaddr A4 –t abcd
-chksecfg <file_p> | <file_s> will enable the NVRAM SecfgTest
Boot code configuration will be checked against input files. The input files are in the
same format as EEPROM.TXT. <file_p> is for the primary port and <file_s> is for the
secondary port. Software will read command from input files and compare with the
boot code configuration and return “Passed” or “Failed” accordingly.
page 30
Broadcom Confidential and Proprietary
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