The Broadcom® HCPL-90xx and HCPL-09xx CMOS digital
isolators feature high speed performance and excellent
transient immunity specifications. The symmetric magnetic
coupling barrier gives these devices a typical pulse width
distortion of 2 ns, a typical propagation delay skew of 4 ns
and 100 Mbaud data rate, making them the industry’s
fastest digital isolators.
The single-channel digital isolators (HCPL-9000/-0900)
feature an active-low logic output enable. The dual-channel
digital isolators are configured as unidirectional (HCPL9030/-0930) and bidirectional (HCPL-9031/-0931),
operating in full-duplex mode, making them ideal for digital
fieldbus applications.
The quad-channel digital isolators are configured as
unidirectional (HCPL-900J/-090J), two channels in one
direction and two channels in opposite direction (HCPL901J/-091J), and one channel in one direction and three
channels in opposite direction (HCPL-902J/-092J). This
high channel density makes them ideally suited to isolating
data conversion devices, parallel buses, and peripheral
interfaces.
They are available in 8-pin PDIP, 8-pin Gull Wing, 8-pin
SOIC packages, and 16-pin SOIC narrow-body and widebody packages. They are specified over the temperature
range of –40°C to +100°C.
Digital fieldbus isolation
Multiplexed data transmission
Computer peripheral interface
High-speed digital systems
Isolated data interfaces
Logic level shifting
CAUTION! Take normal static precautions in handling and
assembly of this component to prevent damage
and/or degradation which may be induced by
ESD. The components featured in this data
sheet are not to be used in military or
aerospace applications or environments.
BroadcomAV02-0137EN
July 13, 2022
Page 2
HCPL-9000/-0900, -9030/-0930,
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
Selection Guide
Device NumberChannel ConfigurationPackage
HCPL-9000Single8-pin DIP (300 Mil)
HCPL-0900Single8-pin Small Outline
HCPL-9030Dual8-pin DIP (300 Mil)
HCPL-0930Dual8-pin Small Outline
HCPL-9031Dual, Bidirectional8-pin DIP (300 Mil)
HCPL-0931Dual, Bidirectional8-pin Small Outline
HCPL-900JQuad16-pin Small Outline, Wide Body
HCPL-090JQuad16-pin Small Outline, Narrow Body
HCPL-901JQuad, 2/2, Bidirectional16-pin Small Outline, Wide Body
HCPL-091JQuad, 2/2, Bidirectional16-pin Small Outline, Narrow Body
HCPL-902JQuad, 1/3, Bidirectional16-pin Small Outline, Wide Body
HCPL-092JQuad, 1/3, Bidirectional16-pin Small Outline, Narrow Body
Ordering Information
HCPL-09xx and HCPL-90xx are UL Recognized with 2500 V
Option
Part Number
HCPL-9000
HCPL-9030
HCPL-9031
HCPL-0900
HCPL-0930
HCPL-0931
HCPL-900J
HCPL-901J
HCPL-902J
HCPL-090J
HCPL-091J
HCPL-092J
-000E300 mil DIP-850 per tube
-300EXX50 per tube
-500EXXX1000 per reel
-000ESO-8X100 per tube
-500EXX1500 per reel
-000EWide Body SO-16X50 per tube
-500EXX1000 per reel
-000ENarrow Body SO-16X50 per tube
-500EXX1000 per reel
PackageSurface MountGull WingTape and ReelQuantityRoHS Compliant
for 1 minute per UL1577.
rms
To order, choose a part number from the part number column and combine with the desired option from the option column
to form an order entry.
Example 1:
HCPL-9031-500E to order product of 300-mil DIP Gull Wing Surface-Mount package in Tape and Reel in RoHS
compliant.
Option data sheets are available. Contact your Broadcom sales representative or authorized distributor for information.
BroadcomAV02-0137EN
2
Page 3
HCPL-9000/-0900, -9030/-0930,
V
DD1
IN
1
NC
GND
1
GND
2
OUT
1
V
DD2
V
OE
8
7
6
5
1
2
3
4
Galvanic Isolation
HCPL-9000/0900
V
DD1
IN
1
IN
2
GND
1
GND
2
OUT
2
V
DD2
OUT
1
8
7
6
5
1
2
3
4
Galvanic Isolation
V
DD1
IN
1
OUT
2
GND
1
GND
2
IN
2
V
DD2
OUT
1
8
7
6
5
1
2
4
Galvanic Isolation
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
Pin Descriptions
SymbolDescription
V
DD1
V
DD2
IN
X
OUT
GND
GND
V
OE
X
1
2
Power Supply 1
Power Supply 2
Logic Input Signal
Logic Output Signal
Power Supply Ground 1
Power Supply Ground 2
Logic Output Enable (Single Channel), Active Low
NCNot Connected
Functional Diagrams
Single Channel
Dual Channel
Truth Table
IN
1
LLL
HLH
LHZ
HHZ
V
OE
OUT
1
HCPL-9030/0930
BroadcomAV02-0137EN
HCPL-9031/0931
3
Page 4
HCPL-9000/-0900, -9030/-0930,
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
V
DD1
GND
1
IN
1
IN
2
IN
3
IN
4
NC
GND
1
GND
2
NC
OUT
4
OUT
3
OUT
2
OUT
1
GND
2
V
DD2
Galvanic Isolation
HCPL-900J/-090J
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
V
DD1
GND
1
IN
1
IN
2
OUT
3
OUT
4
NC
GND
1GND
2
NC
IN
4
IN
3
OUT
2
OUT
1
GND
2
V
DD2
Galvanic Isolation
HCPL-901J/-091J
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
V
DD1
GND
1
IN
1
IN
2
IN
3
OUT
4
NC
GND
1GND
2
NC
IN
4
OUT
3
OUT
2
OUT
1
GND
2
V
DD2
Galvanic Isolation
HCPL-902J/-092J
0.28 (7.1)
0.33 (8.4)
0.30 (7.6)
0.38 (9.7)
0.008 (0.2)
0.015 (0.4)
Dimensions: inches (mm); scale = approx. 2.5X
0.345 (8.76)
0.40 (10.2)
0.27 (6.9)
0.24 (6.1)
0
10
0.055 (1.40)
0.065 (1.65)
0.030 (0.76)
0.045 (1.14)
0.014 (0.36)
0.045 (1.14)
0.070 (1.78)
0.09 (2.3)
0.11 (2.8)
0.015 (0.38)
0.040 (1.02)
0.13 (3.30)
0.17 (4.32)
0.023 (0.58)
NOTE:
Pin spacing is a basic
dimension; tolerances
do not accumulate
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
Quad Channel
Package Outline Drawings
HCPL-9000, HCPL-9030, and HCPL-9031 Standard DIP Packages
BroadcomAV02-0137EN
4
Page 5
HCPL-9000/-0900, -9030/-0930,
0.030 (0.762)
0.045 (1.143)
0.345 (8.76)
0.400 (10.160)
0.240 (6.096)
0.27 (6.9)
87 65
4321
0.045 (1.143)
0.070 (1.78)
0.120 (3.048)
0.150 (3.810)
0.047 (1.194)
0.070 (1.778)
0.040 (1.016)
0.047 (1.194)
0.370 (9.398)
0.390 (9.906)
0.190
(4.826)
0.015 (0.381)
0.025 (0.635)
0.025 (0.632)
0.035 (0.892)
0.030 (0.760)
0.056 (1.400)
0.015 (0.385)
0.035 (0.885)
0.290 (7.370)
0.310 (7.870)
0.370 (9.400)
0.390 (9.900)
TYP.
12
° NOM.
0.008 (0.203)
0.015 (0.4)
0.09 (2.3)
DIMENSIONS INCHES (MILLIMETERS)
LEAD COPLANARITY = 0.004 INCHES (0.10 mm)
MIN
MAX
0.11 (2.8)
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
HCPL-9000, HCPL-9030, and HCPL-9031 Gull Wing Surface-Mount Option 300
PAD LOCATION (for reference only)
BroadcomAV02-0137EN
5
Page 6
HCPL-9000/-0900, -9030/-0930,
0.188 (4.77)
0.197 (5.00)
0.050 (1.27)
0.004 (0.1)
0.012 (0.3)
NOTE:
Pin spacing is a basic
dimension; tolerances
do not accumulate
0.054 (1.37)
0.072 (1.83)
0.228 (5.8)
0.244 (6.2)
0.150 (3.8)
0.157 (4.0)
0.052 (1.32)
0.062 (1.57)
0.013 (0.3)
0.020 (0.5)
0.007 (0.2)
0.013 (0.3)
0.016 (0.4)
0.050 (1.3)
NOM
Dimensions: inches (mm); scale = approx. 5X
0.275 (6.99)
0.050 (1.27)
0.020 (0.51)
8 PLCS
Pad Layout
Dimensions: inches (mm); scale = approx. 5X
0.160 (4.05)
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
HCPL-0900, HCPL-0930, and HCPL-0931 Small Outline SO-8 Package
BroadcomAV02-0137EN
6
Page 7
HCPL-9000/-0900, -9030/-0930,
0.049 (1.24)
0.017 (0.43)
0.022 (0.56)
0.292 (7.42)
0.299 (7.59)
0.007 (0.18)
0.010 (0.25)
0.260 (6.60)
0.280 (7.11)
0.033 (0.85)
0.043 (1.10)
0.007 (0.2)
0.013 (0.3)
Pin 1 identied by
either an indent
or a marked dot
0.08 (2.0)
0.10 (2.5)
0.397 (10.08)
0.413 (10.49)
0.394 (10.00)
0.092 (2.34)
0.105 (2.67)
0.004 (0.1)
0.012 (0.3)
0.016 (0.4)
0.050 (1.3)
0.051 (1.30)
NOTE:
Pin spacing is a basic
dimension; tolerances
do not accumulate
0.013 (0.3)
0.020 (0.5)
Dimensions: inches (mm); scale = approx. 5X
0.419 (10.64)
0.050 (1.27)
0.449 (11.40)
0.020 (0.51)
16 PLCS
Pad Layout
Dimensions: inches (mm); scale = approx. 5X
0.317 (8.05)
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
HCPL-900J, HCPL-901J, and HCPL-902J Wide Body SOIC-16 Package
BroadcomAV02-0137EN
7
Page 8
HCPL-9000/-0900, -9030/-0930,
0.386 (9.8)
0.394 (10.0)
0.049 (1.24)
0.007 (0.2)
0.013 (0.3)
Pin 1 identified
by either an
indent or a
marked dot
0.004 (0.1)
0.012 (0.3)
0.016 (0.4)
0.050 (1.3)
0.051 (1.30)
NOTE:
Pin spacing is a basic
dimension; tolerances
do not accumulate
0.054 (1.4)
0.072 (1.8)
0.228 (5.8)
0.244 (6.2)
0.150 (3.81)
0.157 (3.99)
0.055 (1.40)
0.062 (1.58)
0.013 (0.3)
0.020 (0.5)
NOM
Dimensions: inches (mm); scale = approx. 5X
0.050 (1.27)
0.275 (6.99)
0.020 (0.51)
16 PLCS
Pad Layout
Dimensions: inches (mm); scale = approx. 5X
0.160 (4.05)
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
HCPL-090J, HCPL-091J, and HCPL-092J Narrow Body SOIC-16 Package
BroadcomAV02-0137EN
8
Page 9
HCPL-9000/-0900, -9030/-0930,
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
Package Characteristics
ParameterSymbolMin.Typ.Max.UnitTest Conditions
Capacitance (Input-Output)
a
Single Channel—1.1—
Dual Channel—2.0—
Quad Channel—4.0—
Thermal Resistanceθ
8-Pin PDIP—54—
8-Pin SOIC—144—
16-Pin SOIC Narrow Body—41—
16-Pin SOIC Wide Body—28—
Package Power DissipationP
8-Pin PDIP——150
8-Pin SOIC——150
16-Pin SOIC Narrow Body——150
16-Pin SOIC Wide Body——150
a. Single- and dual-channel device are considered two-terminal devices: pins 1 to 4 shorted and pins 5 to 8 shorted. Quad-channel devices are
considered two-terminal devices: pins 1 to 8 shorted and pins 9 to 16 shorted.
Note: This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Broadcom recommends that all
integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range
from performance degradation to complete failure.
C
I-O
JCT
PD
pFf = 1 MHz.
°C/WThermocouple located at center
underside of package.
mW
Insulation and Safety Related Specifications
ParameterConditionMin.Typ.Max.Unit
Barrier Resistance || CapacitanceΩ || pF
Single Channel—
Dual Channel—
Quad Channel—
>1014 || 3
>1014 || 3
14
|| 7
>10
Creepage Distance (External)mm
8-Pin PDIP7.04——
8-Pin SOIC4.04——
16-Pin SOIC Narrow Body4.03——
16-Pin SOIC Wide Body8.08——
Leakage Current240 V
, 60 Hz—0.2—μA
rms
—
—
—
BroadcomAV02-0137EN
9
Page 10
HCPL-9000/-0900, -9030/-0930,
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
Installation Classification per DIN VDE 0110/1.89, Table 1
For Rated Mains Voltage
For Rated Mains Voltage
≤ 150 V
≤ 300 V
rms
rms
I – IIII – IV
I – III
Pollution Degree (DIN VDE 0110/1.89)22
Maximum Working Insulation VoltageV
IORM
150300V
Soldering Profile
The recommended reflow soldering conditions are per JEDEC Standard J-STD-020 (latest revision).
Absolute Maximum Ratings
ParameterSymbolMin.Max.Unit
Storage TemperatureT
Ambient Operating Temperature
a
Supply VoltageV
Input VoltageV
Voltage Output Enable (HCPL-9000/-0900)V
Output VoltageV
Output Current DriveI
DD1
S
T
A
, V
IN
OE
OUT
OUT
DD2
Lead Solder Temperature (10s)—260°C
ESD2 kV Human Body Model
a. Absolute maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee performance.
–55150°C
–55125°C
–0.57V
–0.5V
–0.5V
–0.5V
+ 0.5V
DD1
+ 0.5V
DD2
+ 0.5V
DD2
—10mA
Unit
rms
Recommended Operating Conditions
ParameterSymbolMin.Max.Unit
Ambient Operating TemperatureT
Supply VoltageV
Logic High Input VoltageV
Logic Low Input VoltageV
Input Signal Rise and Fall TimestIR, t
Note: This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Broadcom recommends that all
integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range
BroadcomAV02-0137EN
DD1
A
, V
IH
IL
DD2
IF
–40100°C
3.05.5V
2.4V
DD1
V
00.8V
—1μs
10
Page 11
HCPL-9000/-0900, -9030/-0930,
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
from performance degradation to complete failure.
3.3V Operation: Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications
are at T
Quiescent Supply Current 1I
Quiescent Supply Current 2I
Logic Input CurrentI
Logic High Output VoltageV
Logic Low Output VoltageV
Switching Specifications
= +25°C, V
A
DD1
= V
DD2
= +3.3V.
ParameterSymbolMin.Typ .Max.UnitTest Conditions
DD1
HCPL-9000/-0900—0.0080.01
HCPL-9030/-0930—0.0080.01
HCPL-9031/-0931—1.52.0
HCPL-900J/-090J—0.0180.02
HCPL-901J/-091J—3.34.0
HCPL-902J/-092J—1.52.0
DD2
HCPL-9000/-0900—3.34.0
HCPL-9030/-0930—3.34.0
HCPL-9031/-0931—1.52.0
HCPL-900J/-090J—5.58.0
HCPL-901J/-091J—3.34.0
HCPL-902J/-092J—3.06.0
IN
OH
OL
–10—10µA
V
DD2
0.8 * V
– 0.1V
DD2VDD2
DD2
– 0.5—VI
—VI
—00.1VI
—0.50.8VI
mAVIN = 0V
mAVIN = 0V
= –20 µA, VIN = V
OUT
= –4 mA, VIN = V
OUT
= 20 µA, VIN = V
OUT
= 4 mA, VIN = V
OUT
IH
IH
IL
IL
BroadcomAV02-0137EN
11
Page 12
HCPL-9000/-0900, -9030/-0930,
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
ParameterSymbolMin.Typ .Max.UnitTest Conditions
Maximum Data Rate100110—MBdCL = 15 pF
Clock Frequencyfmax——50MHz
Propagation Delay Time to Logic Low Outputt
Propagation Delay Time to Logic High Outputt
Pulse Widtht
Pulse Width Distortiona |t
Propagation Delay Skew
PHL
b
– t
PLH
|
|PWD|—23ns
Output Rise Time (10% to 90%)t
Output Fall Time (10% to 90%)t
PHL
PLH
t
PSK
PW
R
F
—1218ns
—1218ns
10——ns
—4 6ns
—2 4ns
—2 4ns
Propagation Delay Enable to Output
(Single Channel)
High to High Impedancet
Low to High Impedancet
High Impedance to Hight
High Impedance to Lowt
Channel-to-Channel Skew
PHZ
PLZ
PZH
PZL
t
CSK
—3 5ns
—3 5ns
—3 5ns
—3 5ns
—2 3ns
(Dual and Quad Channels)
Common Mode Transient Immunity
(Output Logic High or Logic Low)
a. PWD is defined as |t
is equal to the magnitude of the worst-case difference in t
b. t
PSK
is the maximum common mode voltage slew rate that can be sustained while maintaining V
c. CM
H
common mode input voltage that can be sustained while maintaining V
and falling common mode voltage edges.
Note: This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Broadcom recommends that all
integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range
from performance degradation to complete failure.
PHL
c
– t
|. %PWD is equal to the PWD divided by the pulse width.
PLH
|CMH|,
|CM
L
|
1518—kV/µsV
PHL
and/or t
that will be seen between units at 25°C.
PLH
> 0.8V
< 0.8V. The common mode voltage slew rates apply to both rising
OUT
OUT
. CML is the maximum
DD2
= 1000V
cm
5V Operation: Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications
are at T
Quiescent Supply Current 1I
BroadcomAV02-0137EN
= +25°C, V
A
DD1
= V
DD2
= +5.0V.
ParameterSymbolMin.Typ.Max.UnitTest Conditions
DD1
HCPL-9000/-0900—0.0120.018
HCPL-9030/-0930—0.0120.018
HCPL-9031/-0931—2.53.0
HCPL-900J/-090J—0.0240.036
HCPL-901J/-091J—5.06.0
HCPL-902J/-092J—2.53.0
mAVIN = 0V
12
Page 13
HCPL-9000/-0900, -9030/-0930,
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
ParameterSymbolMin.Typ.Max.UnitTest Conditions
Quiescent Supply Current 2I
DD2
mAVIN = 0V
HCPL-9000/-0900—5.06.0
HCPL-9030/-0930—5.06.0
HCPL-9031/-0931—2.53.0
HCPL-900J/-090J—8.012.0
HCPL-901J/-091J—5.06.0
HCPL-902J/-092J—6.09.0
Logic Input CurrentI
Logic High Output VoltageV
Logic Low Output VoltageV
IN
OH
OL
–10—10µA
V
– 0.1 V
DD2
0.8 * V
DD2VDD2
DD2
– 0.5—VI
—00.1VI
—0.50.8VI
—VI
OUT
OUT
OUT
OUT
= –20 µA, VIN = V
= –4 mA, VIN = V
= 20 µA, VIN = V
= 4 mA, VIN = V
IH
IH
IL
IL
Switching Specifications
Maximum Data Rate100110—MBdC
= 15 pF
L
Clock Frequencyfmax——50MHz
Propagation Delay Time to Logic Low Outputt
Propagation Delay Time to Logic High Outputt
Pulse Widtht
Pulse Width Distortion
a
Propagation Delay Skew
|t
– t
PLH
|
PHL
b
|PWD|—23ns
Output Rise Time (10% to 90%)t
Output Fall Time (10% to 90%)t
PHL
PLH
t
PSK
PW
R
F
—1015ns
—1015ns
10——ns
—46ns
—13ns
—13ns
Propagation Delay Enable to Output
(Single Channel)
High to High Impedancet
Low to High Impedancet
High Impedance to Hight
High Impedance to Lowt
Channel-to-Channel Skew
PHZ
PLZ
PZH
PZL
t
CSK
—35ns
—35ns
—35ns
—35ns
—23ns
(Dual and Quad Channels)
Common Mode Transient Immunity
(Output Logic High or Logic Low)
a. PWD is defined as |t
is equal to the magnitude of the worst-case difference in t
b. t
PSK
is the maximum common mode voltage slew rate that can be sustained while maintaining V
c. CM
H
common mode input voltage that can be sustained while maintaining V
and falling common mode voltage edges.
Note: This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Broadcom recommends that all
integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range
from performance degradation to complete failure.
PHL
c
– t
|. %PWD is equal to the PWD divided by the pulse width.
PLH
|CMH|,
|CM
L
|
1518—kV/µsV
PHL
and/or t
that will be seen between units at 25°C.
PLH
> 0.8V
< 0.8V. The common mode voltage slew rates apply to both rising
OUT
OUT
. CML is the maximum
DD2
= 1000V
cm
BroadcomAV02-0137EN
13
Page 14
HCPL-9000/-0900, -9030/-0930,
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
Mixed 5V/3.3V or 3.3V/5V Operation: Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications
are at T
= +25°C, V
A
ParameterSymbolMin.Typ.Max.UnitTest Conditions
Quiescent Supply Current 1I
HCPL-9000/-0900—0.0120.018
HCPL-9030/-0930—0.0120.018
HCPL-9031/-0931—2.53.0
HCPL-900J/-090J—0.0240.036
HCPL-901J/-091J—5.06.0
HCPL-902J/-092J—2.53.0
Quiescent Supply Current 2I
HCPL-9000/-0900—5.06.0
HCPL-9030/-0930—5.06.0
HCPL-9031/-0931—2.53.0
HCPL-900J/-090J—8.012.0
HCPL-901J/-091J—5.06.0
HCPL-902J/-092J—6.09.0
Logic Input CurrentI
Logic High Output VoltageV
Logic Low Output VoltageV
Switching Specifications
Maximum Data Rate100110—MBdC
Clock Frequencyfmax——50MHz
Propagation Delay Time to Logic Low Outputt
Propagation Delay Time to Logic High Outputt
Pulse Widtht
Pulse Width Distortion
Propagation Delay Skew
Output Rise Time (10% to 90%)t
Output Fall Time (10% to 90%)t
Propagation Delay Enable to Output
(Single Channel)
High to High Impedancet
Low to High Impedancet
High Impedance to Hight
High Impedance to Lowt
Channel-to-Channel Skew
(Dual and Quad Channels)
= +5.0V, V
DD1
a
|t
PHL
b
– t
PLH
= +3.3V.
DD2
DD1
DD2
IN
OH
OL
–10—10µA
V
DD2
0.8 * V
– 0.1V
DD2VDD2
DD2
– 0.5—VI
—VI
—00.1VI
—0.50.8VI
PHL
PLH
PW
|
|PWD|—23ns
t
PSK
R
F
PHZ
PLZ
PZH
PZL
t
CSK
—1218ns
—1218ns
10——ns
—46ns
—24ns
—24ns
—35ns
—35ns
—35ns
—35ns
—23ns
mAVIN = 0V
mAVIN = 0V
= –20 µA, VIN = V
OUT
= –4 mA, VIN = V
OUT
= 20 µA, VIN = V
OUT
= 4 mA, VIN = V
OUT
= 15 pF
L
IH
IH
IL
IL
BroadcomAV02-0137EN
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Page 15
HCPL-9000/-0900, -9030/-0930,
1
2
3
45
6
7
8
V
DD1
IN
1
C1
C2
Note: C1, C2 = 47 nF ceramic capacitors.
NC
GND
1
V
DD2
OUT
1
GND
2
HCPL-9000
or
HCPL-0900
V
OE
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
ParameterSymbolMin.Typ.Max.UnitTest Conditions
Common Mode Transient Immunity
(Output Logic High or Logic Low)
a. PWD is defined as |t
is equal to the magnitude of the worst-case difference in t
b. t
PSK
is the maximum common mode voltage slew rate that can be sustained while maintaining V
c. CM
H
mode input voltage that can be sustained while maintaining V
common mode voltage edges.
Note: This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Broadcom recommends that all
integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range
from performance degradation to complete failure.
PHL
c
– t
|. %PWD is equal to the PWD divided by the pulse width.
PLH
|CMH|,
|CM
L
|
1518kV/µsV
OUT
Bypassing and PC Board Layout
= 1000V
The HCPL-90xx and HCPL-09xx digital isolators are
extremely easy to use. No external interface circuitry is
required because the isolators use high-speed CMOS IC
and/or t
PHL
< 0.8V. The common mode voltage slew rates apply to both rising and falling
that will be seen between units at 25°C.
PLH
technology allowing CMOS logic to be connected directly to
> 0.8V
the inputs and outputs. As shown in Figure 1, the only
OUT
DD2
external components required for proper operation are low
ESR 47 nF ceramic capacitors for decoupling the power
supplies. Ground planes for both GND
highly recommended for data rates above 10 Mb/s.
cm
. CML is the maximum common
and GND2 are
1
Capacitors must be located as close as possible to the V
pins.
Application Information
Figure 1: Functional Diagram of Single-Channel HCPL-0900
or HCPL-0900
Power Consumption
The HCPL-90xx and HCPL-09xx CMOS digital isolators
achieves low power consumption from the manner by which
they transmit data across isolation barrier. By detecting the
edge transitions of the input logic signal and converting this
to a narrow current pulse, which drives the isolation barrier,
the isolator then latches the input logic state in the output
latch. Since the current pulses are narrow, about 2.5 ns
wide, the power consumption is independent of mark-tospace ratio and solely dependent on frequency.
DD
The approximate power supply current per channel is:
I(Input) = 40(f/fmax)(1/4) mA
where f = operating frequency, fmax = 50 MHz.
Signal Status on Start-up and
Shut Down
To minimize power dissipation, the input signals to the
channels of HCPL-90xx and HCPL-09xx digital isolators are
differentiated and then latched on the output side of the
isolation barrier to reconstruct the signal. This could result in
an ambiguous output state depending on power up,
shutdown, and power loss sequencing. Therefore, the
designer should consider the inclusion of an initialization
signal in this start-up circuit. Initialization consists of toggling
the input either high then low or low then high.
BroadcomAV02-0137EN
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HCPL-9000/-0900, -9030/-0930,
INPUT
O
2.5 V CMOS
0 V
V
OH
V
OL
V
OUT
V
IN
t
PLH
t
PHL
50%
10%
90%
90%
10%
V
IN
V
OUT
V
OUT
V
IN
t
PSK
50%
50%
2.5 V
CMOS
2.5 V
CMOS
DATA
DATA
INPUTS
CLOCK
OUTPUTS
CLOCK
t
PSK
t
PSK
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
Propagation Delay, Pulse Width
Distortion and Propagation Delay
Skew
Propagation Delay is a figure of merit, which describes how
quickly a logic signal propagates through a system as
illustrated in Figure 2.
Figure 2: Timing Diagram to Illustrate Propagation Delay, t
and t
PHL
UTPUT
The propagation delay from low to high, t
, is the amount
PLH
of time required for an input signal to propagate to the
output, causing the output to change from low to high.
Similarly, the propagation delay from high to low, t
PHL
amount of time required for the input signal to propagate to
the output, causing the output to change from high to low.
PLH
5 V CMOS
, is the
propagation delays, either t
PLH
or t
, among two or more
PHL
channels within a single device (applicable to dual and quad
channel devices) that are operating under the same
conditions.
As illustrated in Figure 3, if the inputs of two or more devices
are switched either ON or OFF at the same time, t
difference between the minimum propagation delay, either
t
or t
PLH
t
PLH
or t
Figure 3: Timing Diagram to Illustrate Propagation Delay
Skew
, and the maximum propagation delay, either
PHL
.
PHL
PSK
is the
Pulse Width Distortion, PWD, is the difference between t
and t
and often determines the maximum data rate
PLH
PHL
capability of a transmission system. PWD can be expressed
in percent by dividing the PWD (in ns) by the minimum pulse
width (in ns) being transmitted. Typically, PWD on the order
of 20% to 30% of the minimum pulse width is tolerable.
Propagation Delay Skew, t
Skew, t
, are critical parameters to consider in parallel
CSK
, and Channel-to-Channel
PSK
data transmission applications where synchronization of
signals on parallel data lines is a concern. If the parallel data
is being sent through channels of the digital isolators,
differences in propagation delays will cause the data to
arrive at the outputs of the digital isolators at different times.
If this difference in propagation delay is large enough, it will
limit the maximum transmission rate at which parallel data
can be sent through the digital isolators.
t
is defined as the difference between the minimum and
PSK
maximum propagation delays, either t
two or more devices that are operating under the same
PLH
or t
, among
PHL
conditions (i.e., the same drive current, supply voltage,
output load, and operating temperature). t
the difference between the minimum and maximum
is defined as
CSK
As mentioned previously, t
, can determine the maximum
PSK
parallel data transmission rate. Figure 4 shows the timing
diagram of a typical parallel data transmission application
with both the clock and data lines being sent through the
digital isolators. The figure shows data and clock signals at
the inputs and outputs of the digital isolators. In this case,
the data is clocked off the rising edge of the clock.
Figure 4: Parallel Data Transmission
BroadcomAV02-0137EN
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HCPL-9000/-0900, -9030/-0930,
50%
50%
90%
10%10%
90%
V
IN
V
OUT
V
OE
t
PW
t
PLZ
t
PZH
t
PHZ
t
PZL
t
F
t
R
tPW Minimum Pulse Width t
PHZ
Propagation Delay, High to High Impedance
t
PLZ
Propagation Delay, Low to High Impedance t
PZL
Propagation Delay, High Impedance to Low
t
PZH
Propagation Delay, High Impedance to High tR Rise Time
t
F
Fall Time
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J Data Sheet High-Speed Digital Isolators
Propagation delay skew represents the uncertainty of where an edge might be after being sent through a digital isolator.
Figure 4 shows that there will be uncertainty in both the data and clock lines. It is important that these two areas of
uncertainty not overlap. Otherwise, the clock signal might arrive before all of the data outputs have settled, or some of the
data outputs might start to change before the clock signal has arrived. From these considerations, the absolute minimum
pulse width that can be sent through digital isolators in a parallel application is twice t
. A cautious design should use a
PSK
slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem.
Figure 5 shows the minimum pulse width, rise and fall time, and propagation delay enable to output waveforms for
HCPL-9000 or HCPL-0900.
Figure 5: Timing Diagram to Illustrate the Minimum Pulse Width, Rise and Fall Time, and Propagation Delay Enable to Output
Waveforms for HCPL9000 or HCPL-0900
Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability,
function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does
not assume any liability arising out of the application or use of this information, nor the application or use of any product or
circuit described herein, neither does it convey any license under its patent rights nor the rights of others.
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