Broadcom BCM5720, BCM5717, BCM5718, BCM5719 Programmer's Manual

Programmer’s Guide

BCM5718

NetXtreme®/NetLink® BCM5718 Family

Programmer’s Guide

5718-PG108-R

5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 January 29, 2016

Revision History

Revision Date Change Description

5718-PG-108-R 01/29/16 Updated:

• “Other Considerations Relating to Producer Ring Setup” on page 90

• “RCB Setup Pseudo Code” on page 91

• “Summary of Register Settings to Support Jumbo Frames” on page 129

• “Receive MTU Size Register (offset: 0x43C)” on page 316

• “BM Hardware Diagnostic 2 Register (offset: 0x4450)” on page 431

5718-PG-107-R 07/17/13 Updated:

• “Send Rings” on page 106

• “Initialization Procedure” on page 140

• Table 49: “GPIO Usage for Power Management for Broadcom Drivers,” on page 192

• Table 101: “Multiple Send Ring Mail Boxes,” on page 357

• “Send BD Ring Host Producer Index Register (offset: 0x5900)” on page 465

• “Send BD Ring NIC Producer Index Register (offset: 0x5980)” on page 466

• Table 121: “GbE Port Internal PHY Register Map,” on page 553

• Table 127: “AUTONEG LINK PARTNER ABILITY,” on page 559

Added:

• Table 124: “02h: PHY_Identifier_MSB_Register,” on page 558

• Table 125: “03h: PHY_Identifier_LSB_Register,” on page 558

Broadcom Corporation

5300 California Avenue

Irvine, CA 92617

Printed in the U.S.A.

Broadcom

NetXtreme II

affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names

, the pulse logo, Connecting everything®, the Connecting everything logo, NetLink®,

, NetXtreme®, and NetXtreme® I are among the trademarks of Broadcom Corporation and/or its

mentioned are the property of their respective owners.

Revision Date Change Description

5718-PG-106-R 06/25/12 Updated:

• “Base Address Register 1 (offset: 0x10)” on page 275

• “Base Address Register 2 (offset: 0x14)” on page 275

• “Base Address Register 3 (offset: 0x18)” on page 275

• “Base Address Register 4 (offset: 0x1c)” on page 276

• “Mode Control Register (offset: 0x6800)” on page 475

Added:

• Section 8: “IEEE1588,” on page 152

• “RX TIME STAMP LSB REG [Offset 0X06B0]” on page 163

• “RX TIME STAMP MSB REG [Offset 0x06B4]” on page 163

• “RX PTP SEQUENCE ID REG [Offset 0X06B8]” on page 163

• “RX LOCK TIMER LSB REG [Offset 0x06C0]” on page 164

• “RX LOCK TIMER MSB REG [Offset 0x06C4]” on page 164

• “RX PTP CONTROL REG [Offset 0X06C8]” on page 164

• Section 12: “IO Virtualization (IOV),” on page 264

• “Perfect Match Destination Address Registers” on page 465

• “VRQ Filter Set Registers” on page 461

• “VRQ Mapper Registers” on page 462

• “Base Address Register 5 (offset: 0x20)” on page 276

• “Base Address Register 6 (offset: 0x24)” on page 277

Revision HistoryBCM5718 Programmer’s Guide

Broadcom®

January 29, 2016 • 5718-PG108-R Page 3

Revision Date Change Description

5718-PG-105-R 02/24/12 Updated:

• Table 3: “Family Revision Levels,” on page 48

• Table 5: “Flag Fields for a Ring,” on page 70

• Figure 24: “Ring Control Block,” on page 118

• “Summary of Register Settings to Support Jumbo Frames” on page 126

• “Initialization Procedure” on page 136

• “Reading a PHY Register” on page 186

• “Writing a PHY Register” on page 187

• “Subsystem ID/Vendor ID Register (offset: 0x2C)” on page 251

• “DMA Read/Write Control Register (Offset: 0x6c)” on page 258

• “PCI State Register (offset: 0x70)” on page 259

• “Receive BD Standard Producer Ring Index Register (offset: 0x2680x26f)” on page 281

• “Transmit MAC Status Register (offset: 0x460)” on page 296

• “Receive MAC Mode Register (offset: 0x468)” on page 297

• “Statistics Registers” on page 319

• “H2B Statistics Registers” on page 320

• “Receive Data and Receive BD Initiator Mode Register (offset: 0x2400)” on page 341

• “Link Speed 10 MB/No Link Power Mode Clock Policy Register (offset: 0x3604)” on page 356

• “Link Speed 100 MB Power Mode Clock Policy Register (offset: 0x3608)” on page 357

• “Link Aware Power Mode Clock Policy Register (offset: 0x3610)” on page 359

• “D0u Clock Policy Register (offset: 0x3614)” on page 360

• “Link Idle Power Mode Clock Policy Register (offset: 0x3618)” on page 360

• “APE CLK Policy Register (offset: 0x361C)” on page 361

• “APE Sleep State Clock Policy Register (offset: 0x3620)” on page 363

• “Clock Speed Override Policy Register (offset: 0x3624)” on page 364

• “Clock Status Register (offset: 0x3630)” on page 367

• “Padring Control Register (offset: 0x3668)” on page 376

• “Receive Coalescing Ticks Register (offset: 0x3C08)” on page 393

• “Send Coalescing Ticks Register (offset: 0x3C0C)” on page 394

• “Receive Max Coalesced BD Count Register (offset: 0x3C10)” on page 395

• “Send Max Coalesced BD Count Register (offset: 0x3C14)” on page 397

• “Status Block Host Address Register (offset: 0x3C38)” on page 400

Revision HistoryBCM5718 Programmer’s Guide

Broadcom®

January 29, 2016 • 5718-PG108-R Page 4

Revision Date Change Description

• “Status Block Base Address Register (offset: 0x3C44)” on page 426

• “BM Hardware Diagnostic 2 Register (offset: 0x4450)” on page 436

• “LSO Read DMA Mode Register (offset: 0x4800)” on page 438

• “LSO Read DMA Reserved Control Register (offset: 0x4900)” on page 445

• “LSO Read DMA Flow Reserved Control Register (offset: 0x4904)” on page 446

• “LSO/Non-LSO/BD Read DMA Corruption Enable Control Register (offset: 0x4910)” on page 446

• “BD Read DMA Mode Register (Offset: 0x4A00)” on page 449

• “BD READ DMA Reserved Control Register (offset: 0x4A70)” on page 456

• “BD READ DMA Flow Reserved Control Register (offset: 0x4A74)” on page 457

• “BD READ DMA Corruption Enable Control Register (offset: 0x4A78)” on page 457

• “Non_LSO Read DMA Mode Register (offset: 0x4B00)” on page 458

• “Non-LSO Read DMA Reserved Control Register (offset: 0x4B74)” on page 461

• “Non-LSO Read DMA Corruption Enable Control Register (offset: 0X4B7C)” on page 462

• “Write DMA Mode Register (offset: 0x4C00)” on page 464

• “Low Priority Mailboxes” on page 469

• “Interrupt Mailbox 0 Register (offset: 0x5800)” on page 469

• “Other Interrupt Mailbox Register (offset: 0x5808–0x5818)” on page 469

• “General Mailbox Registers 1-8 (offset: 0x5820–0x5824)” on page 469

• “Receive BD Standard Producer Ring Index Register (offset: 0x5868)” on page 470

• “Receive BD Return Ring 0 Consumer Index Register (offset: 0x58800x5887)” on page 470

• “Send BD Ring Consumer Index Register (offset: 0x5900)” on page 471

• “NVM Write Register (offset: 0x7008)” on page 497

• “NVM Address Register (offset: 0x700C)” on page 497

• “NVM Read Register (offset: 0x7010)” on page 498

• “NVM Config 1 Register (offset: 0x7014)” on page 498

• “NVM Access Register (offset: 0x7024)” on page 502

• “00h: MII_Control_Register” on page 513

• “03h: PHY_Identifier_LSB_Register” on page 515

• “04h: Auto_Negot_Advertisement_Register” on page 515

• “09h: 1000Base_T_Control_Register” on page 518

• “10h: PHY_Extended_Control_Register” on page 522

• “18h: Auxiliary Control Register (Shadow Register Selector = “000”)” on page 526

Revision HistoryBCM5718 Programmer’s Guide

Broadcom®

January 29, 2016 • 5718-PG108-R Page 5

Revision Date Change Description

• “18h: Miscellaneous Control Register (Shadow Register Selector = “111”)” on page 533

• “1Ch: Cabletron LED Register (Shadow Register Selector = “00h”)” on page 538

• “1Ch: Spare Control 4 Register (Shadow Register Selector = “0bh”)” on page 547

• “1Ch: External SerDes Control Register (Shadow Register Selector = “14h”)” on page 557

• “1Ch: SGMII Slave Register (Shadow Register Selector = “15h”)” on page 559

• “1Ch: Misc 1000-X Control 2 Register (Shadow Register Selector = “16h”)” on page 561

• “1Ch: Misc 1000-X Control Register (Shadow Register Selector = “17h”)” on page 563

• “1Ch: Auto-Detect SGMII/GBIC Register (Shadow Register Selector = “18h”)” on page 564

• “1Ch: Auto-Detect Medium Register (Shadow Register Selector = “1eh”)” on page 572

• “1Ch: Mode Control Register (Shadow Register Selector = “1fh”)” on page 573

Added:

• Table 1: “Register Access Methods,” on page 46

• “Device Reset Procedure” on page 146

• “PHY Loopback Configuration” on page 205

• “PHY Configuration Auto-Negotiation (10/100/1000 Speed with Half and Full Duplex Support)” on page 206

• “MSI-X Capabilities Registers” on page 281

• “PCIe Capabilities Registers” on page 282

• “VRQ Flush Control Register (Offset: 0x2410)” on page 369

• “VRQ Flush Timer Register (offset: 0x2414)” on page 370

• “RDI B2HRX Hardware Debugging Register (offset: 0x2418)” on page 370

• “Receive BD Ring Initiator Local NIC Standard Receive BD Consumer Index (offset: 0x2474)” on page 373

• “B2HRX Byte-count Statistics Count (offset: 0x24D0)” on page 374

• “B2HRX Unicast Statistics Count (offset: 0x24D4)” on page 374

• “B2HRX Multicast Statistics Count (offset: 0x24D8)” on page 374

• “B2HRX Broadcast Statistics Count (offset: 0x24DC))” on page 374

• “B2HRX Drop Packet Count (offset: 0x24E0)” on page 374

• “B2HRX Drop Packet Byte Count (offset: 0x24E4)” on page 374

• “B2HRX APE Byte-count Statistics Count (offset: 0x24E8)” on page 375

• “B2HRX APE Unicast Statistics Count (offset: 0x24EC)” on page 375

• “B2HRX APE Multicast Statistics Count (offset: 0x24F0)” on page 375

• “B2HRX APE Broadcast Statistics Count (offset: 0x24F4)” on page 375

• “B2HRX APE Drop Packet Count (offset: 0x24F8)” on page 375

• “B2HRX APE Drop Packet Byte Count (offset: 0x24FC)” on page 375

Revision HistoryBCM5718 Programmer’s Guide

Broadcom®

January 29, 2016 • 5718-PG108-R Page 6

Revision Date Change Description

• “Receive Max Coalesced BD Count During Interrupt Register (offset: 0x3C18)” on page 424

• “Send Max Coalesced BD Count During Interrupt Register (offset: 0x3C1C)” on page 425

• “NIC Mini Receive BD Consumer Index (offset: 0x3c58)” on page 428

• “Send BD Ring Producer Index Register (offset: 0x5980)” on page 471

• “DMA Completion Mode Register (Offset: 0x6400)” on page 477

• Figure 58: “Copper PHY Register Mapping Table,” on page 511

• Figure 59: “SerDes PHY Register Map,” on page 512

• “Clause 45 Registers” on page 601

• “SerDes PHY Register Definitions” on page 578

• “PHY 0x18 Shadow 0x1 register read Procedure” on page 527

• Added PHY 0x1C Shadow 0x1 register read Procedure information to “1Ch: Cabletron LED Register (Shadow Register Selector = “00h”)” on page 538

• Added Clause 45 register Dev3 Reg803Eh read Procedure to “Clause 45 Register Dev 3 Reg14h (20d): EEE Capability Register” on page 601

• NIC Ring Addresses information to Memory map tables in Appendix C: “Device Register and Memory Map,” on page 611

Deleted

• Section 11: Host to/from BMC Pass Through

• Appendix D: Appendix

• Top Level MII Registers

5718-PG104-R 06/29/11 Updated:

• Table 27: “Flag Field Description,” on page 113

• Table 31: “Send Buffer Descriptor Flags,” on page 123

• “Clock Control” on page 191

• Table 47: “Ethernet Controller Power Pins,” on page 191

• “Internal Memory” on page 214

• “ISR Flow” on page 230

• Table 82: “Interrupt-Related Registers,” on page 235

• “Status Register (offset: 0x362C)” on page 391

• “Clock Status Register (offset: 0x3630)” on page 393

• “LSO Read DMA Mode Register (offset: 0x4800)” on page 438

• “NVM Write Register (offset: 0x7008)” on page 497

Added:

• “Device Closing Procedure” on page 147

• “TX TIME STAMP LSB REG (offset: 0x5C0)” on page 327

• “TX TIME STAMP MSB REG (offset: 0x5C4)” on page 327

Revision HistoryBCM5718 Programmer’s Guide

Broadcom®

January 29, 2016 • 5718-PG108-R Page 7

Revision Date Change Description

5718-PG103-R 01/26/11 Updated:

• Added BCM5720 to Section 1: “Introduction,” on page 49.

• Added BCM5720 to “Introduction” on page 49.

• Added Host to BMC to “Transmit MAC Mode Register (offset: 0x45C)” on page 317.

• Added Host to BMC to “Transmit MAC Lengths Register (offset: 0x464)” on page 319.

• Added Host to BMC to “Mode Control Register (offset: 0x6800)” on page 477.

Added

• “HTX2B Perfect Match[1–4] HI Reg (offset: 0x4880, 0x4888, 0x4890, 0x4898)” on page 330.

• “HTX2B Perfect Match[1–4] LO Reg (offset: 0x4884, 0x488C, 0x4894, 0x489C)” on page 330.

• “HTX2B Protocol Filter Reg (offset: 0x6D0)” on page 331.

• “HTX2B Global Filter Reg (address: 0x6D4)” on page 333.

• “H2B Statistics Registers” on page 346.

• “HTX2B Statistics” on page 347

• “B2HRX Statistics” on page 347

• “RMU Registers” on page 504

• “RMU_EGRESS_DA1_MATCH[1-8]_REG (offsets: 0x00B0, 0x00B8, 0x00C0, 0x00C8 … 0xE8)” on page 504

• “RMU_EGRESS_DA2_MATCH[1-8]_REG (Offsets 0x00B4, 0x00BC, 0x00C4, 0xCC …0xEC)” on page 504

• “RMU_EGRESS_STATUS_REG (Offset 0x0000)” on page 504

Revision HistoryBCM5718 Programmer’s Guide

Broadcom®

January 29, 2016 • 5718-PG108-R Page 8

Revision Date Change Description

5718-PG102-R 12/16/10 Updated:

• Added BCM5719 to “Introduction” on page 39.

• Added BCM5719 to “Related Documents” on page 39.

• Added BCM5719 to Table 1: “BCM5718 Family Product Features,” on page 40.

• Removed PHY core column and added BCM5717 B0, BCM5718 BO, and BCM5719 to Table 2: “Family Revision Levels,” on page 42.

• Updated note in “Revision Levels” on page 42.

• Added Memory Arbiter to Figure 1: “Individual Port Functional Block Diagram,” on page 45.

• Added BCM5719 to “Overview of Features” on page 46.

• Added note about BCM5719 to Figure 2: “High-Level System Functional Block Diagram,” on page 47.

• Added max ring sizes to “Ring Control Block” on page 99.

• Added BCM5719 toTable 6: “Defined Flags for Send Buffer Descriptors,” on page 67.

• Updated Host Ring Size to Table 7: “Receive Return Rings,” on page 70.

• Corrected typo in Figure 26: “Send Driver Interface,” on page 119.

• Corrected typo in Figure 27: “Receive Producer Interface,” on page 120.

• Corrected typo in Figure 28: “Receive Return Interface,” on page 121.

• Updated Step 36 in “Initialization Procedure” on page 137.

• Added BCM5719 to “Description” on page 168.

• Corrected typo in “PCI Classcode and Revision ID Register (offset: 0x08)—Function 0” on page 255

• Corrected typos in “Power Management Control/Status Register (offset: 0x4C) — Function 0” on page 261

• Added note to Enable Endian Byte Swap in “Miscellaneous Host Control Register (offset: 0x68)” on page 264.

• Updated all Indirection Table register descriptions in “RSS Registers” on page 276.

• Added BCM5717 and BCM5718 values to “CPMU Control Register (offset: 0x3600)” on page 346.

• Added BCM5719 to “Link Aware Power Mode Clock Policy Register (offset: 0x3610)” on page 349.

• Added BCM5719 to “APE CLK Policy Register (offset: 0x361C)” on page 352.

Revision HistoryBCM5718 Programmer’s Guide

Broadcom®

January 29, 2016 • 5718-PG108-R Page 9

Revision Date Change Description

Updated (continued):

• Added BCM5718 to “Clock Speed Override Policy Register (offset: 0x3624) for BCM5718” on page 354

• Added BCM5718 to “Clock Status Register (offset: 0x3630)” on page 358

• Added Reserved for BCM5719 to “PCIE Status Register (offset: 0x3634)” on page 359

• Added BCM5719 to “GPHY Control/Status Register (offset: 0x3638)” on page 360

• Updated introduction to “PCIE Idle Detection De-Bounce Control Register (offset: 0x364C)” on page 362

• Corrected typo and added BCM5719 to “DLL Lock Timer Register (offset: 0x3654)” on page 364

• Updated Chip ID default value in “CHIP ID Register (offset: 0x3658)” on page 365

• Added BCM5719 to “Padring Control Register (offset: 0x3668)” on page 367

• Added BCM5719 to “Reserved (offset: 0x366C)” on page 368

• Added BCM5719 to “Reserved (offset: 0x367C)” on page 373

• Added BCM5719 to “Read DMA Mode Register (offset: 0x4800)” on page 398

• “LSO Read DMA Corruption Enable Control Register (offset: 0x4910)” on page 413

• Added BCM5719 to “Write DMA Mode Register (offset: 0x4C00)” on page 443

• Added BCM5719 to “MSI Mode Register (offset: 0x6000)” on page 454

Added:

• “Receive BD Standard Producer Ring Index (High Priority Mailbox) Register (offset: 0x268-0x26f)” on page 276

• “TX Time Stamp LSB Reg (offset: 0x5C0)” on page 282

• “TX Time Stamp MSB Reg (offset: 0x5C4)” on page 283

• “RX Time Stamp LSB Reg (offset 0x06B0)” on page 308

• “RX Time Stamp MSB Reg (offset 0x06B4)” on page 308

• “RX PTP Sequence ID Reg (offset 0x06B8)” on page 308

• “RX Lock Timer LSB Reg (offset 0x6C0)” on page 309

• “RX Lock Timer MSB Reg (offset 0x06C4)” on page 309

• “RX PTP Control Reg (offset: 0x6C8)” on page 310

• “Clock Speed Override Policy Register (offset: 0x3624)” on page 355

• “Clock Status Register (offset: 0x3630)” on page 358

• “Global Mutex Request Register (offset: 0x36F0)” on page 381

• “Global Mutex Grant Register (offset: 0x36F4)” on page 381

• “Temperature Monitor Control Register (offset: 0x36FC)” on page 382

• “BCM5719 Registers” on page 469

Removed:

• “Reserved (offset: 0x378C)”

Revision HistoryBCM5718 Programmer’s Guide

Broadcom®

January 29, 2016 • 5718-PG108-R Page 10

Revision Date Change Description

5718-PG101-R 11/12/10 Updated:

• Table 1: “BCM5718 Family Product Features,” on page 40

• IP cksum description in “Receive Buffer Descriptors” on page 70

• “Extended RX Buffer Descriptor (BD)” on page 110

• Table title for Table 34: “Jumbo Producer Ring Host Address Low Register (offset: 0x2444),” on page 123

• Default value and description in Table 36: “Jumbo Producer Ring NIC Address Register (offset: 0x244C),” on page 123

• NIC ring address values in Table 45: “NIC Ring Addresses,” on page 126

• PCI version in “Description” on page 148

• “EMAC Status Register (offset: 0x404)” on page 279

• “DMA Flag Register for TCP Segmentation (offset: 0xCEC)” on page 321

• “Jumbo Producer Ring NIC Address Register (offset: 0x244C)” on page 337

• “Receive Producer Length/Flags Register (offset: 0x2458)” on page 337

• “Receive Producer Ring NIC Address Register (offset: 0x245C)” on page 338

• “GPHY Strap Register (offset: 0x3664)” on page 366

• “Read DMA Mode Register (offset: 0x4800)” on page 398

• “BCM5718 Family MII Bus PHY Addressing” on page 496

Added:

• Section 8: “Device Control,” on page 137

• Registers 0x00 to 0x3c and 0x48 to 0x64 to “PCI Configuration Registers” on page 254

• Section 14: “Transceiver Registers,” on page 496

Removed:

• References to BCM5724 throughout

• Column from Table 1: “BCM5718 Family Product Features,” on page 40

• Register control mode from “MDI Register Access” on page 187

• MDI Control Register (offset: 0x6844)

5718-PG100-R 04/13/10 Initial release

Revision HistoryBCM5718 Programmer’s Guide

Broadcom®

January 29, 2016 • 5718-PG108-R Page 11

Table of ContentsBCM5718 Programmer’s Guide

About This Document................................................................................................................................44

Purpose and Audience .......................................................................................................................... 44

Acronyms and Abbreviations................................................................................................................. 44

Document Conventions ......................................................................................................................... 44

References ............................................................................................................................................ 45

Technical Support...................................................................................................................................... 46

Section 1: Introduction .....................................................................................................47

Product Features........................................................................................................................................ 47

Revision Levels .......................................................................................................................................... 49

Programming the Ethernet Controllers.................................................................................................... 50

Section 2: Hardware Architecture....................................................................................51

Theory of Operation................................................................................................................................... 51

Overview of Features ................................................................................................................................. 52

Receive Data Path ...................................................................................................................................... 54

RX Engine ............................................................................................................................................. 54

RX FIFO ................................................................................................................................................ 54

Rules Checker....................................................................................................................................... 55

RX List Initiator ...................................................................................................................................... 55

Transmit Data Path..................................................................................................................................... 56

TX MAC................................................................................................................................................. 56

TX FIFO................................................................................................................................................. 56

DMA Read.................................................................................................................................................... 57

Read Engine.......................................................................................................................................... 57

Read FIFO............................................................................................................................................. 57

Buffer Manager...................................................................................................................................... 58

DMA Write ................................................................................................................................................... 58

Write Engine.......................................................................................................................................... 58

Write FIFO............................................................................................................................................. 58

Buffer Manager...................................................................................................................................... 59

LED Control................................................................................................................................................. 59

Memory Arbiter........................................................................................................................................... 59

Host Coalescing ......................................................................................................................................... 60

Host Coalescing Engine ........................................................................................................................ 60

MSI FIFO............................................................................................................................................... 61

Status Block .......................................................................................................................................... 61

10BT/100BTx/1000BASE-T Transceiver ................................................................................................... 62

Broadcom

January 29, 2016 • 5718-PG108-R Page 12

Table of ContentsBCM5718 Programmer’s Guide

Auto-Negotiation.................................................................................................................................... 62

Automatic MDI Crossover ..................................................................................................................... 62

PHY Control................................................................................................................................................ 62

MII Block................................................................................................................................................ 62

GMII Block............................................................................................................................................. 64

MDIO Register Interface........................................................................................................................ 66

Management Data Clock................................................................................................................ 66

Management Data Input/Output..................................................................................................... 66

Management Data Interrupt ........................................................................................................... 66

Management Register Block .......................................................................................................... 66

Section 3: NVRAM Configuration.....................................................................................67

Overview...................................................................................................................................................... 67

Self-Boot...................................................................................................................................................... 68

Section 4: Common Data Structures...............................................................................69

Theory of Operation................................................................................................................................... 69

Descriptor Rings......................................................................................................................................... 69

Producer and Consumer Indices........................................................................................................... 70

Ring Control Blocks............................................................................................................................... 71

Send Ring Control Blocks .............................................................................................................. 71

Receive Ring Control Blocks.......................................................................................................... 72

Send Rings............................................................................................................................................ 73

Send Buffer Descriptors ................................................................................................................. 75

Standard (Not Large Segment Offload) ................................................................................. 75

Large Segment Offload (LSO) Send BD................................................................................ 76

Receive Rings ....................................................................................................................................... 77

Receive Producer Ring .................................................................................................................. 77

Receive Return Rings .................................................................................................................... 78

Receive Buffer Descriptors ............................................................................................................ 78

Additional Ring Information for the BCM5718 Family .................................................................... 81

Status Block................................................................................................................................................ 82

Status Block Format .............................................................................................................................. 82

INTx/MSI — Legacy Mode Status Block Format ............................................................................ 83

Single-Vector or INTx — RSS Mode Status Block Format ............................................................. 84

Multivector RSS Mode Status Block Format .................................................................................. 85

Status Block and INT MailBox Addresses...................................................................................... 86

Section 5: Receive Data Flow...........................................................................................88

Introduction................................................................................................................................................. 88

Receive Producer Ring.............................................................................................................................. 90

Broadcom

January 29, 2016 • 5718-PG108-R Page 13

Table of ContentsBCM5718 Programmer’s Guide

Setup of Producer Rings Using RCBs................................................................................................... 90

Receive Producer Ring RCB—Register Offset 0x2450–0x245f .................................................... 90

Other Considerations Relating to Producer Ring Setup......................................................... 90

RCB Setup Pseudo Code .............................................................................................................. 91

Receive Buffer Descriptors.................................................................................................................... 91

Management of Rx Producer Rings with Mailbox Registers and Status Block ..................................... 92

Status Block ................................................................................................................................... 92

Mailbox........................................................................................................................................... 92

Receive BD Producer Ring Producer Index........................................................................... 92

Receive Return Rings ................................................................................................................................93

Management of Return Rings with Mailbox Registers and Status Block .............................................. 94

Host Buffer Allocation............................................................................................................................ 94

Receive Rules Setup and Frame Classification ....................................................................................95

Receive Rules Configuration Register ........................................................................................... 95

Receive List Placement Rules Array..............................................................................................96

Class of Service Example .............................................................................................................. 97

Checksum Calculation............................................................................................................................... 98

VLAN Tag Strip........................................................................................................................................... 98

RX Data Flow Diagram ............................................................................................................................. 100

Receive Side Scaling................................................................................................................................101

Overview ............................................................................................................................................. 101

Functional Description......................................................................................................................... 101

RSS Parameters ................................................................................................................................. 102

Hash Function .............................................................................................................................. 102

Hash Type.................................................................................................................................... 102

Hash Mask ................................................................................................................................... 102

Indirection Table........................................................................................................................... 103

Secret Hash Key .......................................................................................................................... 103

RSS Initialization ................................................................................................................................. 103

RSS Rx Packet Flow ........................................................................................................................... 104

Section 6: Transmit Data Flow .......................................................................................105

Introduction............................................................................................................................................... 105

Send Rings................................................................................................................................................ 105

Ring Control Block............................................................................................................................... 107

Host-Based Send Ring........................................................................................................................ 108

Checksum Offload.................................................................................................................................... 109

Large Segment Offload............................................................................................................................ 110

QuickStart............................................................................................................................................ 110

LSO-Related Hardware Control Bits ................................................................................................... 111

Broadcom

January 29, 2016 • 5718-PG108-R Page 14

Table of ContentsBCM5718 Programmer’s Guide

Send Buffer Descriptor ........................................................................................................................ 112

Host Address................................................................................................................................ 112

Length[15:0] ................................................................................................................................. 112

VLAN Tag[15:0]............................................................................................................................ 112

HdrLen[7:0] .................................................................................................................................. 112

MSS[13:0] .................................................................................................................................... 113

Flags ............................................................................................................................................ 113

LSO Limitations ................................................................................................................................... 114

Additional LSO Notes .......................................................................................................................... 114

Example TCP-segmentation-related (LSO) register values ......................................................... 115

Jumbo Frames.......................................................................................................................................... 116

Affected Data Structures ..................................................................................................................... 117

Extended RX Buffer Descriptor (BD)............................................................................................ 117

Receive Jumbo Producer Ring .................................................................................................... 120

Ring Control Blocks...................................................................................................................... 121

Receive Return Ring(s)................................................................................................................ 122

Send Buffer Descriptor ................................................................................................................. 122

Status Block ................................................................................................................................. 124

Misc BD Memory.......................................................................................................................... 125

Device Driver Interface........................................................................................................................ 125

Send Interface.............................................................................................................................. 125

Receive Interface ......................................................................................................................... 126

Large Segment Offload (LSO/TSO) ............................................................................................. 128

Summary of Register Settings to Support Jumbo Frames.................................................................. 129

Scatter/Gather........................................................................................................................................... 130

VLAN Tag Insertion.................................................................................................................................. 131

TX Data Flow Diagram.............................................................................................................................. 131

Reset.......................................................................................................................................................... 134

MAC Address Setup/Configuration........................................................................................................ 135

Packet Filtering......................................................................................................................................... 135

Multicast Hash Table Setup/Configuration .......................................................................................... 135

Ethernet CRC Calculation ................................................................................................................... 136

Generating CRC.................................................................................................................................. 136

Checking CRC..................................................................................................................................... 136

Initializing the MAC Hash Registers .................................................................................................... 136

Promiscuous Mode Setup/Configuration............................................................................................. 138

Broadcast Setup/Configuration ........................................................................................................... 138

Section 7: Device Control............................................................................................... 139

Initialization Procedure............................................................................................................................ 139

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Device Reset Procedure .......................................................................................................................... 146

Device Closing Procedure....................................................................................................................... 147

™

Energy Efficient Ethernet

...................................................................................................................... 148

Section 8: IEEE1588........................................................................................................152

IEEE1588 Time Sync Introduction .......................................................................................................... 152

NetXtreme Time Sync Assist................................................................................................................... 152

Coexistence......................................................................................................................................... 152

PTP Link Delay Measurement............................................................................................................. 153

PTP Time Synchronization Messaging ............................................................................................... 153

Hardware Description .............................................................................................................................. 154

EAV Reference Clock/Counter ............................................................................................................ 155

EAV Reference Corrector ........................................................................................................................ 156

Time Watchdogs ................................................................................................................................. 156

Divided EAV Reference Clock Output................................................................................................. 156

Transmit Time Stamping Service............................................................................................................ 157

Receive Time Stamp and Sequence ID Registers................................................................................. 158

Time Sync Registers................................................................................................................................160

GRC MODE REG [0x6800] ................................................................................................................. 160

EAV REF COUNT CAPTURE LSB REG [Offset 0x6900] ................................................................... 160

EAV REF COUNT CAPTURE MSB REG [Offset 0x6904] .................................................................. 160

EAV REF CLOCK CONTROL REG [Offset 0x6908]........................................................................... 161

EAV REF-COUNT SNAP-SHOT LSB[0] REG [Offset 0X6910] .......................................................... 162

EAV REF-COUNT SNAP-SHOT MSB[0] REG [Offset 0X6914] ......................................................... 162

EAV REF CORRECTOR REG [Offset 0x6928]................................................................................... 162

TX TIME STAMP LSB REG [Offset 0x05C0] ...................................................................................... 162

TX TIME STAMP MSB REG [Offset 0X05C4]..................................................................................... 163

RX TIME STAMP LSB REG [Offset 0X06B0] ..................................................................................... 163

RX TIME STAMP MSB REG [Offset 0x06B4] ..................................................................................... 163

RX PTP SEQUENCE ID REG [Offset 0X06B8] .................................................................................. 163

RX LOCK TIMER LSB REG [Offset 0x06C0]...................................................................................... 164

RX LOCK TIMER MSB REG [Offset 0x06C4]..................................................................................... 164

RX PTP CONTROL REG [Offset 0X06C8] ......................................................................................... 164

TX TIME WATCHDOG LSB[0] REG [Offset 0x6918].......................................................................... 165

TX TIME WATCHDOG MSB[0] REG [Offset 0x691C] ........................................................................ 165

TX TIME WATCHDOG LSB[1] REG [Offset 0x6920].......................................................................... 166

TX TIME WATCHDOG MSB[1] REG [Offset 0x6924]......................................................................... 166

EAV REF-COUNT SNAP-SHOT LSB[1] REG [Offset 0X6930] .......................................................... 166

EAV REF-COUNT SNAP-SHOT MSB[1] REG [Offset 0X6934] ......................................................... 167

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Section 9: PCI ..................................................................................................................168

Configuration Space ................................................................................................................................168

Description .......................................................................................................................................... 168

Functional Overview............................................................................................................................ 171

PCI Configuration Space Registers ............................................................................................. 171

PCI Required Header Region ......................................................................................................171

Indirect Mode ............................................................................................................................... 172

Indirect Register Access .............................................................................................................. 173

Indirect Memory Access............................................................................................................... 175

UNDI Mailbox Access .................................................................................................................. 177

Standard Mode............................................................................................................................. 179

Memory Mapped I/O Registers ........................................................................................................... 184

PCI Command Register ............................................................................................................... 184

PCI State Register ....................................................................................................................... 184

PCI Base Address Register ......................................................................................................... 184

Bus Interface............................................................................................................................................. 186

Description .......................................................................................................................................... 186

Operational Characteristics................................................................................................................. 187

Read/Write DMA Engines ............................................................................................................ 187

Expansion ROM........................................................................................................................................ 187

Description .......................................................................................................................................... 187

Operational Characteristics................................................................................................................. 187

BIOS.................................................................................................................................................... 187

Preboot Execution Environment...................................................................................................188

Power Management.................................................................................................................................. 188

Description .......................................................................................................................................... 188

Operational Characteristics................................................................................................................. 189

Device State D0 (Uninitialized) .................................................................................................... 189

Device State D0 (Active) .............................................................................................................. 190

Device State D3 (Hot) .................................................................................................................. 190

Device State D3 (Cold) ................................................................................................................ 190

Wake on LAN ...................................................................................................................................... 190

GPIO ................................................................................................................................................... 191

Power Supply in D3 State ................................................................................................................... 191

Clock Control....................................................................................................................................... 191

Device ACPI Transitions ..................................................................................................................... 192

Disable Device Through BIOS ............................................................................................................ 192

Endian Control (Byte and Word Swapping)........................................................................................... 193

Background ......................................................................................................................................... 193

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Architecture ......................................................................................................................................... 194

Enable Endian Word Swap and Enable Endian Byte Swap Bits......................................................... 194

Word Swap Data and Byte Swap Data Bits ........................................................................................ 197

Word Swap Data = 0, and Byte Swap Data = 0 ........................................................................... 197

Word Swap Data = 0, and Byte Swap Data = 1 ........................................................................... 198

Word Swap Data = 1, and Byte Swap Data = 0 ........................................................................... 198

Word Swap Data = 1, and Byte Swap Data = 1 ........................................................................... 199

Word Swap Non-Frame Data and Byte Swap Non-Frame Data Bits .................................................. 200

Word Swap Non-Frame Data = 0 and Byte Swap Non-Frame Data = 0...................................... 201

Word Swap Non-Frame Data = 1 and Byte Swap Non-Frame Data = 0...................................... 201

Word Swap Non-Frame Data = 0 and Byte Swap Non-Frame Data = 1...................................... 201

Word Swap Non-Frame Data = 1 and Byte Swap Non-Frame Data = 1...................................... 202

Section 10: Ethernet Link Configuration.......................................................................203

Overview.................................................................................................................................................... 203

GMII/MII...................................................................................................................................................... 203

Configuring the Ethernet Controller for GMII and MII Modes .............................................................. 203

Link Status Change Indications........................................................................................................... 204

Configuring the GMII/MII PHY............................................................................................................. 204

Reading a PHY Register.............................................................................................................. 204

Writing a PHY Register ................................................................................................................ 204

PHY Loopback Configuration ....................................................................................................... 205

External PHY Loopback....................................................................................................... 205

Internal PHY Loopback ........................................................................................................ 205

PHY Configuration Auto-Negotiation (10/100/1000 Speed with Half and Full Duplex Support) .. 206

MDI Register Access................................................................................................................................210

Operational Characteristics................................................................................................................. 210

Access Method.................................................................................................................................... 211

Auto-Access Method .................................................................................................................... 211

Wake on LAN Mode/Low-Power.............................................................................................................. 212

Description .......................................................................................................................................... 212

Functional Overview............................................................................................................................ 213

Operational Characteristics................................................................................................................. 214

Internal Memory ........................................................................................................................... 214

WOL Pattern Configuration Register............................................................................................ 214

WOL Streams............................................................................................................................... 215

Pattern Data Structure ................................................................................................................. 217

Firmware Mailbox......................................................................................................................... 218

PHY Auto-Negotiation .................................................................................................................. 219

Power Management ..................................................................................................................... 219

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Integrated MACs .......................................................................................................................... 220

WOL Data Flow Diagram .................................................................................................................... 221

Flow Control.............................................................................................................................................. 223

Description .......................................................................................................................................... 223

Operational Characteristics................................................................................................................. 223

Transmit MAC .............................................................................................................................. 223

Receive MAC ............................................................................................................................... 224

Statistics Block ............................................................................................................................. 225

PHY Auto-Negotiation .................................................................................................................. 226

Integrated MACs .......................................................................................................................... 226

Flow Control Initialization Pseudocode ............................................................................................... 227

Section 11: Interrupt Processing ...................................................................................229

NetXtreme Legacy Interrupt Model......................................................................................................... 229

ISR Flow.............................................................................................................................................. 230

Legacy Status TAGGING Mode................................................................................................... 231

Basic Driver Interrupt Processing Flow................................................................................................. 232

Flowchart for Servicing an Interrupt .................................................................................................... 232

Interrupt Procedure ............................................................................................................................. 233

Host Coalescing ....................................................................................................................................... 234

Description .......................................................................................................................................... 234

Operational Characteristics................................................................................................................. 234

Registers ............................................................................................................................................. 235

MSI............................................................................................................................................................. 236

Traditional Interrupt Scheme............................................................................................................... 236

Message Signaled Interrupt ................................................................................................................ 237

PCI Configuration Registers ................................................................................................................ 238

MSI Address................................................................................................................................. 238

MSI Data ...................................................................................................................................... 238

Host Coalescing Engine ...................................................................................................................... 239

Firmware ............................................................................................................................................. 239

MSI-X.......................................................................................................................................................... 240

MSI-X Plumbing........................................................................................................................................ 244

Replication of Status Blocks and INT Mailboxes................................................................................. 244

Single-Vector RSS Mode Status Block Format............................................................................ 246

Single-Vector IOV Mode Status Block Format ............................................................................. 247

Multivector RSS Mode Status Block Format ................................................................................ 248

Multivector IOV Mode Status Block Format ................................................................................. 249

MSI-X Capability Structure .................................................................................................................. 250

MSI-X Data Structures ........................................................................................................................ 251

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MSI-X Cognizant Host Coalescing ...................................................................................................... 253

Legacy Host Coalescing Parameters........................................................................................... 253

Receive Coalescing Ticks Register (Offset: 0x3c08)........................................................... 253

Send Coalescing Ticks Register (Offset: 0x3c0c)................................................................ 254

Receive Max Coalesced Bd Count Register (Offset: 0x3c10) ............................................. 254

Send Max Coalesced BD Count Register (Offset: 0x3c14) ................................................. 254

Receive Max Coalesced BD Count During Interrupt Register (Offset 0x3c18).................... 255

Send Max Coalesced BD Count During Interrupt Register (Offset 0x3c1c)......................... 255

BCM5718 Family Host Coalescing Parameter Sets .................................................................... 255

MSI-X One Shot Mode ................................................................................................................. 258

Coalesce Now or Forced Update ................................................................................................. 258

Misc Coalescing Controls............................................................................................................. 258

Broadcom Tagged Status Mode (0x68[9])........................................................................... 258

Clear Interrupt, Mask Interrupt, Mask Mode (0x68[0], 0x68[1], 0x68[8]).............................. 259

Clear Ticks On Rx Bd Events Mode (0x3c00[9]).................................................................. 259

No Interrupt On Force Update (0x3c00[11])......................................................................... 259

No Interrupt On DMAD Force (0x3c00[12]).......................................................................... 259

Do Not Interrupt On Receives (0x6800[14])......................................................................... 259

End of Receive Stream Interrupt.................................................................................................. 260

Host Coalescing Mode Register (Offset 0x3c00)................................................................. 260

End Stream Debounce Register (Offset 0x3cd4)................................................................. 260

Other Configuration Controls.................................................................................................................. 262

Broadcom Mask Mode ........................................................................................................................ 262

Broadcom Tagged Status Mode.......................................................................................................... 262

Clear Ticks on BD Events Mode ......................................................................................................... 262

No Interrupt on Force Update.............................................................................................................. 262

No Interrupt on DMAD Force............................................................................................................... 262

Section 12: IO Virtualization (IOV) ................................................................................. 263

Data Structure and Register Changes for IOV....................................................................................... 264

Mail Box Register Changes................................................................................................................. 264

Receive Mail Box Register Changes................................................................................................... 264

Send Mail Box Register Changes ....................................................................................................... 264

Ring Control Block Changes ............................................................................................................... 264

VRQ Statistics ..................................................................................................................................... 264

MSI-X Vectors Changes...................................................................................................................... 265

Register Changes................................................................................................................................ 265

IOV – Receive Side................................................................................................................................... 266

IOV – Transmit Side.................................................................................................................................. 267

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Section 13: Ethernet Controller Register Definitions................................................... 269

BCM5718 Family Register MAP............................................................................................................... 269

PCI Configuration Registers.................................................................................................................... 271

Device ID and Vendor ID Register (offset: 0x00) ................................................................................ 271

Status and Command Register (offset: 0x04) ..................................................................................... 271

PCI Classcode and Revision ID Register (offset: 0x08) ...................................................................... 273

BIST, Header Type, Latency Timer, Cache Line Size Register (offset: 0x0C).................................... 273

Base Address Register 1 (offset: 0x10)............................................................................................... 274

Base Address Register 2 (offset: 0x14)............................................................................................... 274

Base Address Register 3 (offset: 0x18)............................................................................................... 274

Base Address Register 4 (offset: 0x1c)............................................................................................... 275

Base Address Register 5 (offset: 0x20)............................................................................................... 275

Base Address Register 6 (offset: 0x24)............................................................................................... 275

Cardbus CIS Pointer Register (offset: 0x28) ....................................................................................... 276

Subsystem ID/Vendor ID Register (offset: 0x2C) ................................................................................ 277

Expansion ROM Base Address Register (offset: 0x30) ...................................................................... 277

Capabilities Pointer Register (offset: 0x34) ......................................................................................... 277

Interrupt Register (offset: 0x3C) .......................................................................................................... 278

INT Mailbox Register (offset: 0x40–0x44) ........................................................................................... 278

Power Management Capability Register (offset: 0x48) ....................................................................... 279

Power Management Control/Status Register (offset: 0x4C) ............................................................... 279

MSI Capability Header (offset: 0x58) .................................................................................................. 281

MSI Lower Address Register (offset: 0x5C) ........................................................................................ 282

MSI Upper Address Register (offset: 0x60)......................................................................................... 282

MSI Data Register (offset: 0x64) ......................................................................................................... 282

Miscellaneous Host Control Register (offset: 0x68) ............................................................................ 282

DMA Read/Write Control Register (Offset: 0x6C) ............................................................................... 283

PCI State Register (offset: 0x70)......................................................................................................... 285

Reset Counters Initial Values Register (offset: 0x74).......................................................................... 286

Register Base Register (offset: 0x78) ................................................................................................. 286

Memory Base Register (offset: 0x7C) ................................................................................................. 286

Register Data Register (offset: 0x80) .................................................................................................. 286

Memory Data Register (offset: 0x84) .................................................................................................. 287

UNDI Receive Return Ring Consumer Index Register (offset: 0x88–0x8C) ....................................... 287

UNDI Send BD Producer Index Mailbox Register (offset: 0x90–0x94) ............................................... 287

UNDI Receive BD Standard Producer Ring Producer Index Mailbox Register (offset: 0x98–0x9C) .. 287

MSI-X Capabilities Registers............................................................................................................... 288

MSI-X Capability Header Register (offset: 0xA0)......................................................................... 288

MSIX_TBL_OFF_BIR – 0xa4 ....................................................................................................... 288

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MSIX_PBA_BIR_OFF – 0xa8 ...................................................................................................... 288

PCIe Capabilities Registers................................................................................................................. 289

PCIE_CAPABILITY – 0xac ..........................................................................................................289

DEVICE_CAPABILITY – 0xb0 ..................................................................................................... 290

DEVICE_STATUS_CONTROL – 0xb4 ........................................................................................ 291

LINK_CAPABILITY – 0xb8........................................................................................................... 292

LINK_STATUS_CONTROL – 0xbc.............................................................................................. 294

SLOT_CAPABILITY – 0xc0 ......................................................................................................... 296

SLOT_CONTROL_STATUS – 0xc4 ............................................................................................ 296

ROOT_CAP_CONTROL – 0xc8 .................................................................................................. 296

ROOT_STATUS – 0xcc ............................................................................................................... 296

DEVICE_CAPABILITY_2 – 0xd0 ................................................................................................. 297

DEVICE_STATUS_CONTROL2 – 0xd4 ...................................................................................... 297

LINK_CAPABILITY_2 – 0xd8....................................................................................................... 298

LINK_STATUS_CONTROL_2 – 0xdc.......................................................................................... 298

SLOT_CAPABILITY_2 – 0xe0 ..................................................................................................... 300

SLOT_STATUS_CONTROL_2 – 0xe4 ........................................................................................ 300

Product ASIC ID (offset: 0xF4)............................................................................................................ 300

Advanced Error Reporting Enhanced Capability Header (offset: 0x100) ............................................ 301

Uncorrectable Error Status Register (offset: 0x104) ........................................................................... 301

Uncorrectable Error Mask Register (offset: 0x108) ............................................................................. 302

Uncorrectable Error Severity Register (offset: 0x10C) ........................................................................ 303

Correctable Error Status Register (offset: 0x110) ...............................................................................304

Correctable Error Mask Register (offset: 0x114).................................................................................304

Advanced Error Capabilities and Control Register (offset: 0x118)...................................................... 305

Header Log Register (offset: 0x11C)................................................................................................... 305

Header Log Register (offset: 0x120) ................................................................................................... 305

Header Log Register (offset: 0x124) ................................................................................................... 306

Header Log Register (offset: 0x128) ................................................................................................... 306

Interrupt mail box (High Priority Mailbox) Register

(offset: 0x200 – 0x21c).................................................................................................................... 306

General mail box (High Priority Mailbox)

Register (offset: 0x220–0x25c) ....................................................................................................... 306

Reload Statistics mail box (High Priority Mailbox)

Register (offset: 0x260–0x264) ....................................................................................................... 306

High Priority Mailbox Registers.............................................................................................................. 307

Receive BD Standard Producer Ring Index

Register (offset: 0x268-0x26F)........................................................................................................ 307

Receive BD Jumbo Producer Ring Index Register (offset: 0x270) .............................................. 307

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Receive BD Return Ring 0 Consumer Index

Register (offset: 0x280–0x287) ....................................................................................................... 307

Receive BD Return Ring 1 Consumer Index

Register (offset: 0x288–0x28F) ....................................................................................................... 308

Receive BD Return Ring 2 Consumer Index

Register (offset: 0x290–0x297) ....................................................................................................... 308

Receive BD Return Ring 3 Consumer Index

Register (offset: 0x298–0x29F) ....................................................................................................... 308

Send BD Ring Host Producer Index Register (offset: 0x300–0x307).................................................. 308

RX Mail Box Registers for VRQ............................................................................................................... 308

Ethernet MAC (EMAC) Registers ............................................................................................................ 309

EMAC Mode Register (offset: 0x400).................................................................................................. 310

EMAC Status Register (offset: 0x404) ................................................................................................ 311

EMAC Event Enable Register (offset: 0x408) ..................................................................................... 312

LED Control Register (offset: 0x40C).................................................................................................. 313

EMAC MAC Addresses 0 High Register (offset: 0x410) ..................................................................... 314

EMAC MAC Addresses 0 Low Register (offset: 0x414) ...................................................................... 314

EMAC MAC Addresses 1 High Register (offset: 0x418) ..................................................................... 315

EMAC MAC Addresses 1 Low Register (offset: 0x41C) ..................................................................... 315

EMAC MAC Addresses 2 High Register (offset: 0x420) ..................................................................... 315

EMAC MAC Addresses 2 Low Register (offset: 0x424) ...................................................................... 315

EMAC MAC Addresses 3 High Register (offset: 0x428) ..................................................................... 315

EMAC MAC Addresses 3 Low Register (offset: 0x42C) ..................................................................... 315

WOL Pattern Pointer Register (offset: 0x430)..................................................................................... 316

WOL Pattern Configuration Register (offset: 0x434)........................................................................... 316

Ethernet Transmit Random Backoff Register (offset: 0x438) .............................................................. 316

Receive MTU Size Register (offset: 0x43C)........................................................................................ 316

Gigabit PCS Test Register (offset: 0x440) .......................................................................................... 317

Transmit 1000BASE-X Auto-Negotiation Register (offset: 0x444) ...................................................... 317

Receive 1000BASE-X Auto-Negotiation Register (offset: 0x448) ....................................................... 317

MII Communication Register (offset: 0x44C) ......................................................................................317

MII Status Register (offset: 0x450)...................................................................................................... 318

MII Mode Register (offset: 0x454) ....................................................................................................... 318

Autopolling Status Register (offset: 0x458) ......................................................................................... 319

Transmit MAC Mode Register (offset: 0x45C) .................................................................................... 319

Transmit MAC Status Register (offset: 0x460)....................................................................................321

Transmit MAC Lengths Register (offset: 0x464) ................................................................................. 321

Receive MAC Mode Register (offset: 0x468) ...................................................................................... 322

Receive MAC Status Register (offset: 0x46C) .................................................................................... 324

MAC Hash Register 0 (offset: 0x470).................................................................................................. 324

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MAC Hash Register 1 (offset: 0x474).................................................................................................. 324

MAC Hash Register 2 (offset: 0x478).................................................................................................. 324

MAC Hash Register 3 (offset: 0x47C) ................................................................................................. 324

Receive Rules Control Registers (offset: 0x480 + 8*N) ...................................................................... 325

Receive Rules Value/Mask Registers (offset: 0x484 + 8*N) ............................................................... 326

Receive Rules Configuration Register (offset: 0x500) ........................................................................ 326

Low Watermark Maximum Receive Frame Register (offset: 0x504)................................................... 327

APE_PERFECT_MATCH[1–4]_HIGH_REG (Offsets 0x540, 0x548, 0x550, 0x558).......................... 327

APE_PERFECT_MATCH[1–4]_LOW_REG (Offsets 0x544, 0x54C, 0x554, 0x55C) ......................... 327

SGMII Control Register (offset: 0x5B0)............................................................................................... 327

SGMII Status Register (offset: 0x5B4) ................................................................................................ 328

HTX2B Perfect Match[1 – 4] HI Reg (offset: 0x4880, 0x4888, 0x4890, 0x4898) ................................. 328

HTX2B Perfect Match[1 –4] LO Reg (offset: 0x4884, 0x488C, 0x4894, 0x489C) ............................... 328

HTX2B Protocol Filter Reg (offset: 0x6D0) ......................................................................................... 329

HTX2B Global Filter Reg (address: 0x6D4) ........................................................................................331

RSS Registers........................................................................................................................................... 331

Indirection Table Register 0 (offset: 0x630) ........................................................................................ 331

Indirection Table Register 2 (offset: 0x634) ........................................................................................ 331

Indirection Table Register 3 (offset: 0x638) ........................................................................................ 332

Indirection Table Register 4 (offset: 0x63C)........................................................................................ 332

Indirection Table Register 5 (offset: 0x640) ........................................................................................ 333

Indirection Table Register 6 (offset: 0x644) ........................................................................................ 333

Indirection Table Register 8 (offset: 0x648) ........................................................................................ 333

Indirection Table Register 8 (offset: 0x64C)........................................................................................ 334

Indirection Table Register 9 (offset: 0x650) ........................................................................................ 334

Indirection Table Register 10 (offset: 0x654) ...................................................................................... 334

Indirection Table Register 11 (offset: 0x658) ...................................................................................... 335

Indirection Table Register 12 (offset: 0x65C)...................................................................................... 335

Indirection Table Register 12 (offset: 0x660) ...................................................................................... 335

Indirection Table Register 13 (offset: 0x664) ...................................................................................... 336

Indirection Table Register 14 (offset: 0x668) ...................................................................................... 336

Indirection Table Register 15 (offset: 0x66C)...................................................................................... 336

Hash Key Register 0 (offset: 0x670) ................................................................................................... 337

Hash Key Registers 1–8 (offset: 0x674–0x693) .................................................................................. 337

Hash Key Register 9 (offset: 0x694) ................................................................................................... 337

Receive MAC Programmable IPv6 Extension Header Register (offset: 0x6A0) ................................. 338

Statistics Registers .................................................................................................................................. 339

Transmit MAC Static Counters............................................................................................................ 339

ifHCOutOctets (offset: 0x800) ...................................................................................................... 339

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etherStatsCollisions (offset: 0x808) ............................................................................................. 339

outXonSent (offset: 0x80C).......................................................................................................... 339

outXoffSent (offset: 0x810) .......................................................................................................... 339

dot3StatsInternalMacTransmitErrors (offset: 0x818) ................................................................... 339

dot3StatsSingleCollisionFrames (offset: 0x81C).......................................................................... 339

dot3StatsMultipleCollisionFrames (offset: 0x820) ........................................................................ 339

dot3StatsDeferredTransmissions (offset: 0x824)......................................................................... 339

dot3StatsExcessiveTransmissions (offset: 0x82C) ...................................................................... 340

dot3StatsLateCollisions (offset: 0x830)........................................................................................ 340

iHCOutUcastPkts (offset: 0x86C).................................................................................................340

iHCOutMulticastPkts (offset: 0x870) ............................................................................................ 340

iHCOutBroadcastPkts (offset: 0x874) .......................................................................................... 340

ifCRSERRORS (offset: 0x878) .................................................................................................... 340

iOUTDISCARDS (offset: 0x87C).................................................................................................. 340

H2B Statistics Registers...................................................................................................................... 340

HTX2B Statistics .......................................................................................................................... 341

B2HRX Statistics.......................................................................................................................... 341

Receive MAC Static Counters............................................................................................................. 341

ifHCInOctets (offset: 0x880) ......................................................................................................... 341

ifHCINOctets_bad (offset: 0x884) ................................................................................................341

etherStatsFragments (offset: 0x888)............................................................................................ 341

ifHCInUcastPkts (offset: 0x88C) .................................................................................................. 342

ifHCInMulticastPkts (offset: 0x890) .............................................................................................. 342

ifHCInBroadcastPkts (offset: 0x894) ............................................................................................ 342

dot3StatsFCSErrors (offset: 0x898) ............................................................................................. 342

dot3StatsAlignmentErrors (offset: 0x89C).................................................................................... 342

xonPauseFrameReceived (offset: 0x8A0) ................................................................................... 342

xoffPauseFrameReceived (offset: 0x8A4) ................................................................................... 342

macControlFramesRecevied (offset: 0x8A8) ............................................................................... 342

xoffStateEntered (offset: 0x8AC) ................................................................................................. 342

dot3StatsFramesTooLongs (offset: 0x8B0) ................................................................................. 342

etherStatsJabbers (offset: 0x8B4)................................................................................................ 343

etherStatsUndersizePkts (offset: 0x8B8) ..................................................................................... 343

Ifnomorerxbd:0x224C................................................................................................................... 343

Ifindiscard:0x2250 ........................................................................................................................ 343

Ifinerror:0x2254 ............................................................................................................................ 343

APE_NETWORK_STATS_REGS (Offsets 0x900–0x9BC)................................................................. 344

Send Data Initiator Registers .................................................................................................................. 345

Send Data Initiator Mode Register (offset: 0xC00).............................................................................. 345

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Send Data Initiator Status Register (offset: 0xC04) ............................................................................ 345

Send Data Initiator Statistics Control Register (offset: 0xC08)............................................................ 345

Send Data Initiator Statistics Mask Register (offset: 0xC0C) .............................................................. 346

Send Data Initiator Statistics Increment Mask Register (offset: 0xC10).............................................. 346

Local Statistics Register (offset: 0xC80–0xCDF) ................................................................................ 346

TCP Segmentation Control Registers.................................................................................................... 347

Lower Host Address Register for TCP Segmentation (offset: 0xCE0) ................................................ 347

Upper Host Address Register for TCP Segmentation (offset: 0xCE4) ................................................ 347

Length/Offset Register for TCP Segmentation (offset: 0xCE8) ........................................................... 347

DMA Flag Register for TCP Segmentation (offset: 0xCEC) ................................................................ 348

VLAN Tag Register for TCP Segmentation (offset: 0xCF0) ................................................................ 349

Pre-DMA Command Exchange Register for TCP Segmentation (offset: 0xCF4) ............................... 349

Send Data Completion Control Registers.............................................................................................. 350

Send Data Completion Mode Register (offset: 0x1000) ...................................................................... 350

Pre-DMA Command Exchange Register for TCP Segmentation (offset: 0x1008) .............................. 350

Send BD Selector Control Registers...................................................................................................... 351

Send BD Ring Selector Mode Register (offset: 0x1400) ..................................................................... 351

Send BD Ring Selector Status Register (offset: 0x1404) .................................................................... 351

Send BD Ring Selector Hardware Diagnostics Register (offset: 0x1408)........................................... 351

Send BD Ring Selector Local NIC Send BD Consumer Index Register (offset: 0x1440–0x147C) ..... 352

Send BD Initiator Control Registers....................................................................................................... 353

Send BD Initiator Mode Register (offset: 0x1800)............................................................................... 353

Send BD Initiator Status Register (offset: 0x1804)..............................................................................353

Send BD Diagnostic Initiator Local NIC BD N Producer Index Registers (offset: 0x1808–0x1844).... 354

Send BD Fetch Threshold Register (offset: 0x1850)........................................................................... 355

Send Mail Box Registers..................................................................................................................... 355

Send BD Completion Control Registers................................................................................................. 356

Send BD Completion Mode Register (offset: 0x1C00)........................................................................ 356

Receive List Placement Registers.......................................................................................................... 357

Receive List Placement Mode Register (offset: 0x2000) .................................................................... 357

Receive List Placement Status Register (offset: 0x2004) ................................................................... 357

Receive Selector Non-Empty Bits Register (offset: 0x200C) .............................................................. 358

Receive List Placement Configuration Register (offset: 0x2010) ........................................................ 358

Receive List Placement Statistics Control Register (offset: 0x2014) .................................................. 359

Receive List Placement Statistics Enable Mask Register (offset: 0x2018) ......................................... 359

Receive List Placement Statistics Increment Mask Register (offset: 0x201C) .................................... 360

Receive Selector List Head & Tail Pointers (offset: 0x2100)............................................................... 360

Receive Selector List 1 Count Registers (Offset: 0x2108).................................................................. 360

Receive Data and Receive BD Initiator Control Registers.................................................................... 362

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Receive Data and Receive BD Initiator Mode Register (offset: 0x2400)............................................. 362

Receive Data and Receive BD Initiator Status Register (offset: 0x2404) ........................................... 363

VRQ Status Register (offset: 0x240C) ................................................................................................ 364

VRQ Flush Control Register (Offset: 0x2410) .....................................................................................364

VRQ Flush Timer Register (offset: 0x2414) ........................................................................................ 365

RDI B2HRX Hardware Debugging Register (offset: 0x2418) .............................................................. 365

Jumbo Producer Ring Host Address High Register (offset: 0x2440) .................................................. 365

Jumbo Producer Ring Host Address Low Register (offset: 0x2444) ................................................... 366

Jumbo Producer Length/Flags Register (offset: 0x2448).................................................................... 366

Jumbo Producer Ring NIC Address Register (offset: 0x244C) ........................................................... 366

Standard Receive BD Ring RCB Registers......................................................................................... 366

Receive Producer Ring Host Address High Register (offset: 0x2450)......................................... 366

Receive Producer Ring Host Address Low Register (offset: 0x2454).......................................... 367

Receive Producer Length/Flags Register (offset: 0x2458) .......................................................... 367

Receive Producer Ring NIC Address Register (offset: 0x245C) .................................................. 367

Receive Diagnostic Data and Receive BD Ring Initiator Local NIC Jumbo Receive BD Consumer Index

(offset: 0x2470) ............................................................................................................................... 367

Receive BD Ring Initiator Local NIC Standard Receive BD Consumer Index (offset: 0x2474) .......... 368

Receive Data and Receive BD Initiator Hardware Diagnostic Register (offset: 0x24C0).................... 368

B2HRX Byte-count Statistics Count (offset: 0x24D0).......................................................................... 368

B2HRX Unicast Statistics Count (offset: 0x24D4)............................................................................... 368

B2HRX Multicast Statistics Count (offset: 0x24D8)............................................................................. 368

B2HRX Broadcast Statistics Count (offset: 0x24DC) .......................................................................... 368

B2HRX Drop Packet Count (offset: 0x24E0)....................................................................................... 369

B2HRX Drop Packet Byte Count (offset: 0x24E4) .............................................................................. 369

B2HRX APE Byte-count Statistics Count (offset: 0x24E8).................................................................. 369

B2HRX APE Unicast Statistics Count (offset: 0x24EC) ...................................................................... 369

B2HRX APE Multicast Statistics Count (offset: 0x24F0) ..................................................................... 369

B2HRX APE Broadcast Statistics Count (offset: 0x24F4) ................................................................... 369

B2HRX APE Drop Packet Count (offset: 0x24F8)............................................................................... 370

B2HRX APE Drop Packet Byte Count (offset: 0x24FC) ...................................................................... 370

Receive Data Completion Control Registers......................................................................................... 371

Receive Data Completion Mode Register (offset: 0x2800) ................................................................. 371

Receive BD Initiator Control Registers .................................................................................................. 372

Receive BD Initiator Mode Register (offset: 0x2C00).......................................................................... 372

Receive BD Initiator Status Register (offset: 0x2C04) ........................................................................ 372

Receive BD Initiator Local NIC Jumbo Receive BD Producer Index (offset: 0x2C08) ........................ 372

Receive BD Initiator Local NIC Receive BD Producer Index Register (offset: 0x2C0C–0x2C13) ...... 373

Standard Receive BD Producer Ring Replenish Threshold Register (offset: 0x2C18) ....................... 373

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Jumbo Receive BD Producer Ring Replenish Threshold Register (offset: 0x2C1C) .......................... 373

Standard Replenish LWM Register (offset 0x2D00) ........................................................................... 373

Jumbo Replenish LWM Register (offset 0x2D04) ............................................................................... 374

BD Fetch Limit Register (Offset 0x2D08)..................................................................................... 375

Receive BD Completion Control Registers............................................................................................ 375

Receive BD Completion Mode Register (offset: 0x3000) .................................................................... 375

Receive BD Completion Status Register (offset: 0x3004)................................................................... 375

NIC Jumbo Receive BD Producer Index Register (offset: 0x3008)..................................................... 376

NIC Standard Receive BD Producer Index Register (offset: 0x300C) ................................................ 376

Central Power Management Unit (CPMU) Registers............................................................................. 376

CPMU Control Register (offset: 0x3600)............................................................................................. 376

Link Speed 10 MB/No Link Power Mode Clock Policy Register (offset: 0x3604)................................ 378

Link Speed 100 MB Power Mode Clock Policy Register (offset: 0x3608)........................................... 379

Link Speed 1000 MB Power Mode Clock Policy Register (offset: 0x360C) ........................................ 380

Link Aware Power Mode Clock Policy Register (offset: 0x3610) ........................................................ 381

D0u Clock Policy Register (offset: 0x3614)......................................................................................... 382

Link Idle Power Mode Clock Policy Register (offset: 0x3618)............................................................. 382

APE CLK Policy Register (offset: 0x361C).......................................................................................... 383

APE Sleep State Clock Policy Register (offset: 0x3620)..................................................................... 385

Clock Speed Override Policy Register (offset: 0x3624) ...................................................................... 386

Clock Override Enable Register (offset: 0x3628) ................................................................................ 386

Status Register (offset: 0x362C) ......................................................................................................... 387

Clock Status Register (offset: 0x3630)................................................................................................ 389

GPHY Control/Status Register (offset: 0x3638) .................................................................................. 391

RAM Control Register (offset: 0x363C)............................................................................................... 392

Core Idle Detection De-Bounce Control Register (offset: 0x3648)...................................................... 393

PCIE Idle Detection De-Bounce Control Register (offset: 0x364C) .................................................... 394

Energy Detection De-Bounce Timer (offset: 0x3650).......................................................................... 394

DLL Lock Timer Register (offset: 0x3654)........................................................................................... 396

CHIP ID Register (offset: 0x3658) ....................................................................................................... 396

Mutex Request Register (offset: 0x365C) ........................................................................................... 397

Mutex Grant Register (offset: 0x3660) ................................................................................................ 397

GPHY Strap Register (offset: 0x3664) ................................................................................................ 397

Padring Control Register (offset: 0x3668) ........................................................................................... 398

Flash Clock Policy Register (offset: 0x366C) ...................................................................................... 399

Link Idle Control Register (offset: 0x3670) .......................................................................................... 401

Link Idle Status Register (offset: 0x3674) ........................................................................................... 404

Top Level Miscellaneous Control 1 Register (offset: 0x367C) ............................................................ 405

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Miscellaneous Control Register (offset: 0x36AC)................................................................................ 406

EEE Mode Register (offset: 0x36B0) .................................................................................................. 407

EEE Debounce Timer 1 Control Register (offset: 0x36B4) ................................................................. 407

EEE Debounce Timer 2 Control Register (offset: 0x36B8) ................................................................. 408

EEE Link Idle Control Register (offset: 0x36BC) .................................................................................408

EEE Link Idle Status Register (offset: 0x36C0)................................................................................... 409

EEE Statistic Counter 1 Register (offset: 0x36C4).............................................................................. 409

EEE Statistic Counter 2 Register (offset: 0x36C8).............................................................................. 409

EEE Statistics Counter 3 Register (offset: 0x36CC) ........................................................................... 409

EEE Control Register (offset: 0x36D0)................................................................................................ 410

Current Measurement Control Register (offset: 0x36D4) .................................................................... 410

Current Measurement Upper 32-bit Read Register (offset: 0x36D8) .................................................. 411

Current Measurement Lower 32-bit Read Register (offset: 0x36DC) ................................................. 411

Global Mutex Request Register (offset: 0x36F0) ................................................................................ 411

Global Mutex Grant Register (offset: 0x36F4)..................................................................................... 412

Temperature Monitor Control Register (offset: 0x36FC) ..................................................................... 412

Host Coalescing Control Registers ........................................................................................................ 413

Host Coalescing Mode Register (offset: 0x3C00) ............................................................................... 413

Host Coalescing Status Register (offset: 0x3C04) .............................................................................. 414

Receive Coalescing Ticks Register (offset: 0x3C08) .......................................................................... 414

Send Coalescing Ticks Register (offset: 0x3C0C) .............................................................................. 415

Receive Max Coalesced BD Count Register (offset: 0x3C10) ............................................................ 416

Send Max Coalesced BD Count Register (offset: 0x3C14)................................................................. 418

Receive Max Coalesced BD Count During Interrupt Register (offset: 0x3C18) .................................. 419

Send Max Coalesced BD Count During Interrupt Register (offset: 0x3C1C) ...................................... 419

HC Parameter Set Reset Register (Offset: 0x3C28).................................................................... 421

Status Block Host Address Register (offset: 0x3C38).................................................................. 421

Status Block Base Address Register (offset: 0x3C44) ........................................................................ 422

Flow Attention Register (offset: 0x3C48)............................................................................................. 422

NIC Jumbo Receive BD Consumer Index Register (offset: 0x3C50–0x3C58) ............................ 423

NIC Diag Receive Return Ring BD 0 Index Register (offset: 0x3C80)......................................... 423

NIC Jumbo Receive BD Consumer Index Register (offset: 0x3C50) .................................................. 423

NIC Standard Receive BD Consumer Index Register (offset: 0x3C54) .............................................. 424

NIC Mini Receive BD Consumer Index (offset: 0x3c58) ..................................................................... 424

NIC Diagnostic Return Ring 0 Producer Index Register (offset: 0x3C80)........................................... 424

NIC Diagnostic Return Ring 1 Producer Index Register (offset: 0x3C84)........................................... 424

NIC Diagnostic Return Ring 2 Producer Index Register (offset: 0x3C88)........................................... 425

NIC Diagnostic Return Ring 3 Producer Index Register (offset: 0x3C8C) .......................................... 425

NIC Diagnostic Send BD Consumer Index Register (offset: 0x3CC0) ................................................ 425

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Memory Arbiter Control Registers.......................................................................................................... 426

Memory Arbiter Mode Register (offset: 0x4000) ................................................................................. 426

Memory Arbiter Status Register (offset: 0x4004) ................................................................................ 427

Memory Arbiter Trap Address Low Register (offset: 0x4008) ............................................................. 428

Memory Arbiter Trap Address High Register (offset: 0x400C)............................................................ 428

Buffer Manager Registers........................................................................................................................ 428

Buffer Manager Mode Register (offset: 0x4400) ................................................................................. 428

Buffer Manager Status Register (offset: 0x4404)................................................................................ 429

MBUF Pool Base Address Register (offset: 0x4408) .......................................................................... 429

MBUF Pool Length Register (offset: 0x440C) ..................................................................................... 430

Read DMA MBUF Low Watermark Register (offset: 0x4410) ............................................................. 430

MAC RX MBUF Low Watermark Register (offset: 0x4414)................................................................. 430

Read DMA MBUF High Watermark Register (offset: 0x4418) ............................................................ 430

RX RISC MBUF Cluster Allocation Request Register (offset: 0x441C) .............................................. 430

RX RISC MBUF Allocation Response Register (offset: 0x4420) ........................................................ 431

BM Hardware Diagnostic 1 Register (offset: 0x444C)......................................................................... 431

BM Hardware Diagnostic 2 Register (offset: 0x4450) ......................................................................... 431

BM Hardware Diagnostic 3 Register (offset: 0x4454) ......................................................................... 431

Receive Flow Threshold Register (offset: 0x4458) ............................................................................. 432

RDMA Registers ....................................................................................................................................... 433

LSO Read DMA Mode Register (offset: 0x4800) ................................................................................ 433

LSO Read DMA Status Register (offset: 0x4804) ............................................................................... 435

LSO Read DMA Programmable IPv6 Extension Header Register (offset: 0x4808)............................ 435

LSO Read DMA Reserved Control Register (offset: 0x4900) ............................................................. 436

LSO Read DMA Flow Reserved Control Register (offset: 0x4904)..................................................... 436

LSO/Non-LSO/BD Read DMA Corruption Enable Control Register (offset: 0x4910).......................... 437

BD Read DMA Mode Register (offset: 0x4A00) .................................................................................. 440

BD READ DMA Status Register (offset: 0x4A04) ............................................................................... 441

BD READ DMA Reserved Control Register (offset: 0x4A70).............................................................. 442

BD READ DMA Flow Reserved Control Register (offset: 0x4A74) ..................................................... 442

BD READ DMA Corruption Enable Control Register (offset: 0x4A78) ................................................ 443

Non_LSO Read DMA Mode Register (offset: 0x4B00) ....................................................................... 443

Non-LSO Read DMA Status Register (offset: 0x4B04)....................................................................... 445

Non-LSO Read DMA Programmable IPv6 Extension Header Register (offset: 0x4B08).................... 446

Host Address for the DMA Read Channel 0 (Offset: 0x4B28) ............................................................ 446

Host Address for the DMA Read Channel 1 (offset: 0x4B30) ............................................................. 446

Host Address for the DMA Read Channel 2 (offset: 0x4B38) ............................................................. 446

Host Address for the DMA Read Channel 3 (offset: 0x4B40) ............................................................. 447

Non-LSO Read DMA Reserved Control Register (offset: 0x4B74) ..................................................... 447

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Broadcom BCM5720, BCM5717, BCM5718, BCM5719 Programmer's Manual

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