Broadcom BCM2835 User guide

BCM2835 ARM Peripherals

© 2012 Broadcom Corporation.

All rights reserved

Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW

Table of Contents

1 Introduction 4

1.1 Overview 4

1.2 Address map 4

1.2.1 Diagrammatic overview 4

1.2.2 ARM virtual addresses (standard Linux kernel only) 6

1.2.3 ARM physical addresses 6

1.2.4 Bus addresses 6

1.3 Peripheral access precautions for correct memory ordering 7

2 Auxiliaries: UART1 & SPI1, SPI2 8

2.1 Overview 8

2.1.1 AUX registers 9

2.2 Mini UART 10

2.2.1 Mini UART implementation details. 11

2.2.2 Mini UART register details. 11

2.3 Universal SPI Master (2x) 20

2.3.1 SPI implementation details 20

2.3.2 Interrupts 21

2.3.3 Long bit streams 21

2.3.4 SPI register details. 22

3 BSC 28

3.1 Introduction 28

3.2 Register View 28

3.3 10 Bit Addressing 36

4 DMA Controller 38

4.1 Overview 38

4.2 DMA Controller Registers 39

4.2.1 DMA Channel Register Address Map 40

4.3 AXI Bursts 63

4.4 Error Handling 63

4.5 DMA LITE Engines 63

5 External Mass Media Controller 65

o Introduction 65
o Registers 66

6 General Purpose I/O (GPIO) 89

6.1 Register View 90

6.2 Alternative Function Assignments 102

6.3 General Purpose GPIO Clocks 105

7 Interrupts 109

7.1 Introduction 109

7.2 Interrupt pending. 110

7.3 Fast Interrupt (FIQ). 110

7.4 Interrupt priority. 110

7.5 Registers 112

8 PCM / I2S Audio 119

8.1 Block Diagram 120

8.2 Typical Timing 120

8.3 Operation 121

8.4 Software Operation 122

8.4.1 Operating in Polled mode 122

8.4.2 Operating in Interrupt mode 123

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8.4.3 DMA 123

8.5 Error Handling. 123

8.6 PDM Input Mode Operation 124

8.7 GRAY Code Input Mode Operation 124

8.8 PCM Register Map 125

9 Pulse Width Modulator 138

9.1 Overview 138

9.2 Block Diagram 138

9.3 PWM Implementation 139

9.4 Modes of Operation 139

9.5 Quick Reference 140

9.6 Control and Status Registers 141

10 SPI 148

10.1 Introduction 148

10.2 SPI Master Mode 148

10.2.1 Standard mode 148

10.2.2 Bidirectional mode 149

10.3 LoSSI mode 150

10.3.1 Command write 150

10.3.2 Parameter write 150

10.3.3 Byte read commands 151

10.3.4 24bit read command 151

10.3.5 32bit read command 151

10.4 Block Diagram 152

10.5 SPI Register Map 152

10.6 Software Operation 158

10.6.1 Polled 158

10.6.2 Interrupt 158

10.6.3 DMA 158

10.6.4 Notes 159

11 SPI/BSC SLAVE 160

11.1 Introduction 160

11.2 Registers 160

12 System Timer 172

12.1 System Timer Registers 172

13 UART 175

13.1 Variations from the 16C650 UART 175

13.2 Primary UART Inputs and Outputs 176

13.3 UART Interrupts 176

13.4 Register View 177

14 Timer (ARM side) 196

14.1 Introduction 196

14.2 Timer Registers: 196

15 USB 200

15.1 Configuration 200

15.2 Extra / Adapted registers. 202

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1 Introduction

1.1 Overview

BCM2835 contains the following peripherals which may safely be accessed by the ARM:

• Timers

• Interrupt controller

• GPIO

• USB

• PCM / I2S

• DMA controller

• I2C master

• I2C / SPI slave

• SPI0, SPI1, SPI2

• PWM

• UART0, UART1

The purpose of this datasheet is to provide documentation for these peripherals in sufficient
detail to allow a developer to port an operating system to BCM2835.

There are a number of peripherals which are intended to be controlled by the GPU. These are
omitted from this datasheet. Accessing these peripherals from the ARM is not recommended.

1.2 Address map

1.2.1 Diagrammatic overview

In addition to the ARM’s MMU, BCM2835 includes a second coarse-grained MMU for
mapping ARM physical addresses onto system bus addresses. This diagram shows the main
address spaces of interest:

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Addresses in ARM Linux are:

• issued as virtual addresses by the ARM core, then

• mapped into a physical address by the ARM MMU, then

• mapped into a bus address by the ARM mapping MMU, and finally

• used to select the appropriate peripheral or location in RAM.

1.2.2 ARM virtual addresses (standard Linux kernel only)

As is standard practice, the standard BCM2835 Linux kernel provides a contiguous mapping
over the whole of available RAM at the top of memory. The kernel is configured for a
1GB/3GB split between kernel and user-space memory.

The split between ARM and GPU memory is selected by installing one of the supplied
start*.elf files as start.elf in the FAT32 boot partition of the SD card. The minimum amount
of memory which can be given to the GPU is 32MB, but that will restrict the multimedia
performance; for example, 32MB does not provide enough buffering for the GPU to do
1080p30 video decoding.

Virtual addresses in kernel mode will range between 0xC0000000 and 0xEFFFFFFF.

Virtual addresses in user mode (i.e. seen by processes running in ARM Linux) will range
between 0x00000000 and 0xBFFFFFFF.

Peripherals (at physical address 0x20000000 on) are mapped into the kernel virtual address
space starting at address 0xF2000000. Thus a peripheral advertised here at bus address
0x7Ennnnnn is available in the ARM kenel at virtual address 0xF2nnnnnn.

1.2.3 ARM physical addresses

Physical addresses start at 0x00000000 for RAM.

• The ARM section of the RAM starts at 0x00000000.

• The VideoCore section of the RAM is mapped in only if the system is configured to

support a memory mapped display (this is the common case).

The VideoCore MMU maps the ARM physical address space to the bus address space seen
by VideoCore (and VideoCore peripherals). The bus addresses for RAM are set up to map
onto the uncached1 bus address range on the VideoCore starting at 0xC0000000.

Physical addresses range from 0x20000000 to 0x20FFFFFF for peripherals. The bus
addresses for peripherals are set up to map onto the peripheral bus address range starting at
0x7E000000. Thus a peripheral advertised here at bus address 0x7Ennnnnn is available at
physical address 0x20nnnnnn.

1.2.4 Bus addresses

The peripheral addresses specified in this document are bus addresses. Software directly
accessing peripherals must translate these addresses into physical or virtual addresses, as
described above. Software accessing peripherals using the DMA engines must use bus
addresses.

1

BCM2835 provides a 128KB system L2 cache, which is used primarily by the GPU. Accesses to memory are

routed either via or around the L2 cache depending on senior two bits of the bus address.

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Software accessing RAM directly must use physical addresses (based at 0x00000000).
Software accessing RAM using the DMA engines must use bus addresses (based at
0xC0000000).

1.3 Peripheral access precautions for correct memory ordering

The BCM2835 system uses an AMBA AXI-compatible interface structure. In order to keep
the system complexity low and data throughput high, the BCM2835 AXI system does not
always return read data in-order2. The GPU has special logic to cope with data arriving out­of-order; however the ARM core does not contain such logic. Therefore some precautions
must be taken when using the ARM to access peripherals.

Accesses to the same peripheral will always arrive and return in-order. It is only when
switching from one peripheral to another that data can arrive out-of-order. The simplest way
to make sure that data is processed in-order is to place a memory barrier instruction at critical
positions in the code. You should place:

• A memory write barrier before the first write to a peripheral.

• A memory read barrier after the last read of a peripheral.

It is not required to put a memory barrier instruction after each read or write access. Only at
those places in the code where it is possible that a peripheral read or write may be followed
by a read or write of a different peripheral. This is normally at the entry and exit points of the
peripheral service code.

As interrupts can appear anywhere in the code so you should safeguard those. If an interrupt
routine reads from a peripheral the routine should start with a memory read barrier. If an
interrupt routine writes to a peripheral the routine should end with a memory write barrier.

2

Normally a processor assumes that if it executes two read operations the data will arrive in order. So a read
from location X followed by a read from location Y should return the data of location X first, followed by the
data of location Y. Data arriving out of order can have disastrous consequences. For example:

a_status = *pointer_to_peripheral_a;
b_status = *pointer_to_peripheral_b;

Without precuations the values ending up in the variables a_status and b_status can be swapped around.

It is theoretical possible for writes to go ‘wrong’ but that is far more difficult to achieve. The AXI system
makes sure the data always arrives in-order at its intended destination. So:

*pointer_to_peripheral_a = value_a;
*pointer_to_peripheral_b = value_b;

will always give the expected result. The only time write data can arrive out-of-order is if two different
peripherals are connected to the same external equipment.

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2 Auxiliaries: UART1 & SPI1, SPI2

2.1 Overview

The Device has three Auxiliary peripherals: One mini UART and two SPI masters. These
three peripheral are grouped together as they share the same area in the peripheral register
map and they share a common interrupt. Also all three are controlled by the auxiliary enable
register.

Auxiliary peripherals Register Map

(offset = 0x7E21 5000)

Address Register Name3 Description Size

0x7E21 5000 AUX_IRQ Auxiliary Interrupt status 3

0x7E21 5004 AUX_ENABLES Auxiliary enables 3

0x7E21 5040 AUX_MU_IO_REG Mini Uart I/O Data 8

0x7E21 5044 AUX_MU_IER_REG Mini Uart Interrupt Enable 8

0x7E21 5048 AUX_MU_IIR_REG Mini Uart Interrupt Identify 8

0x7E21 504C AUX_MU_LCR_REG Mini Uart Line Control 8

0x7E21 5050 AUX_MU_MCR_REG Mini Uart Modem Control 8

0x7E21 5054 AUX_MU_LSR_REG Mini Uart Line Status 8

0x7E21 5058 AUX_MU_MSR_REG Mini Uart Modem Status 8

0x7E21 505C AUX_MU_SCRATCH Mini Uart Scratch 8

0x7E21 5060 AUX_MU_CNTL_REG Mini Uart Extra Control 8

0x7E21 5064 AUX_MU_STAT_REG Mini Uart Extra Status 32

0x7E21 5068 AUX_MU_BAUD_REG Mini Uart Baudrate 16

0x7E21 5080 AUX_SPI0_CNTL0_REG SPI 1 Control register 0 32

0x7E21 5084 AUX_SPI0_CNTL1_REG SPI 1 Control register 1 8

0x7E21 5088 AUX_SPI0_STAT_REG SPI 1 Status 32

0x7E21 5090 AUX_SPI0_IO_REG SPI 1 Data 32

0x7E21 5094 AUX_SPI0_PEEK_REG SPI 1 Peek 16

0x7E21 50C0 AUX_SPI1_CNTL0_REG SPI 2 Control register 0 32

0x7E21 50C4 AUX_SPI1_CNTL1_REG SPI 2 Control register 1 8

3

These register names are identical to the defines in the AUX_IO header file. For programming purposes these

names should be used wherever possible.

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S

S

0x7E21 50C8 AUX_SPI1_STAT_REG SPI 2 Status 32

0x7E21 50D0 AUX_SPI1_IO_REG SPI 2 Data 32

0x7E21 50D4 AUX_SPI1_PEEK_REG SPI 2 Peek 16

2.1.1 AUX registers

There are two Auxiliary registers which control all three devices. One is the interrupt status
register, the second is the Auxiliary enable register. The Auxiliary IRQ status register can
help to hierarchically determine the source of an interrupt.

AUXIRQ Register (0x7E21 5000)

YNOPSIS

The AUXIRQ register is used to check any pending interrupts which may be asserted by
the three Auxiliary sub blocks.

Bit(s) Field Name Description Type Reset

31:3

2

1

0

Reserved, write zero, read as don’t care

SPI 2 IRQ If set the SPI 2 module has an interrupt pending. R 0

SPI 1 IRQ If set the SPI1 module has an interrupt pending. R 0

Mini UART

If set the mini UART has an interrupt pending. R 0

IRQ

AUXENB Register (0x7E21 5004)

YNOPSIS

The AUXENB register is used to enable the three modules; UART, SPI1, SPI2.

Bit(s) Field Name Description Type Reset

31:3

2

Reserved, write zero, read as don’t care

SPI2 enable If set the SPI 2 module is enabled.

R/W 0

If clear the SPI 2 module is disabled. That also
disables any SPI 2 module register access

1

SPI 1 enable If set the SPI 1 module is enabled.

R/W 0

If clear the SPI 1 module is disabled. That also
disables any SPI 1 module register access

0

Mini UART
enable

If set the mini UART is enabled. The UART will
immediately start receiving data, especially if the

R/W 0

UART1_RX line is low.

If clear the mini UART is disabled. That also disables
any mini UART register access

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If the enable bits are clear you will have no access to a peripheral. You can not even read or
write the registers!

GPIO pins should be set up first the before enabling the UART. The UART core is build to
emulate 16550 behaviour. So when it is enabled any data at the inputs will immediately be
received . If the UART1_RX line is low (because the GPIO pins have not been set-up yet)
that will be seen as a start bit and the UART will start receiving 0x00-characters.

Valid stops bits are not required for the UART. (See also Implementation details). Hence
any bit status is acceptable as stop bit and is only used so there is clean timing start for the
next bit.

Looking after a reset: the baudrate will be zero and the system clock will be 250 MHz. So
only 2.5 µseconds suffice to fill the receive FIFO. The result will be that the FIFO is full and
overflowing in no time flat.

2.2 Mini UART

The mini UART is a secondary low throughput4 UART intended to be used as a console. It
needs to be enabled before it can be used. It is also recommended that the correct GPIO
function mode is selected before enabling the mini Uart.

The mini Uart has the following features:

• 7 or 8 bit operation.

• 1 start and 1 stop bit.

• No parities.

• Break generation.

• 8 symbols deep FIFOs for receive and transmit.

• SW controlled RTS, SW readable CTS.

• Auto flow control with programmable FIFO level.

• 16550 like registers.

• Baudrate derived from system clock.

This is a mini UART and it does NOT have the following capabilities:

• Break detection

• Framing errors detection.

• Parity bit

• Receive Time-out interrupt

• DCD, DSR, DTR or RI signals.

The implemented UART is not a 16650 compatible UART However as far as possible the
first 8 control and status registers are laid out like a 16550 UART. Al 16550 register bits
which are not supported can be written but will be ignored and read back as 0. All control
bits for simple UART receive/transmit operations are available.

4

The UART itself has no throughput limitations in fact it can run up to 32 Mega baud. But doing so requires

significant CPU involvement as it has shallow FIFOs and no DMA support.

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S

2.2.1 Mini UART implementation details.

The UART1_CTS and UART1_RX inputs are synchronised and will take 2 system clock
cycles before they are processed.

The module does not check for any framing errors. After receiving a start bit and 8 (or 7)
data bits the receiver waits for one half bit time and then starts scanning for the next start bit.
The mini UART does not check if the stop bit is high or wait for the stop bit to appear. As a
result of this a UART1_RX input line which is continuously low (a break condition or an
error in connection or GPIO setup) causes the receiver to continuously receive 0x00
symbols.

The mini UART uses 8-times oversampling. The Baudrate can be calculated from:

__

freqclocksystem

baudrate

=

( )

regbaudrate

1_*8

+

If the system clock is 250 MHz and the baud register is zero the baudrate is 31.25 Mega
baud. (25 Mbits/sec or 3.125 Mbytes/sec). The lowest baudrate with a 250 MHz system
clock is 476 Baud.

When writing to the data register only the LS 8 bits are taken. All other bits are ignored.
When reading from the data register only the LS 8 bits are valid. All other bits are zero.

2.2.2 Mini UART register details.

AUX_MU_IO_REG Register (0x7E21 5040)

YNOPSIS

The AUX_MU_IO_REG register is primary used to write data to and read data from the
UART FIFOs.
If the DLAB bit in the line control register is set this register gives access to the LS 8 bits
of the baud rate. (Note: there is easier access to the baud rate register)

Bit(s) Field Name Description Type Reset

31:8

7:0

7:0

Reserved, write zero, read as don’t care

LS 8 bits
Baudrate
read/write,
DLAB=1

Transmit data
write,
DLAB=0

Access to the LS 8 bits of the 16-bit baudrate
register.

(Only If bit 7 of the line control register (DLAB bit)
is set)

Data written is put in the transmit FIFO (Provided it
is not full)

(Only If bit 7 of the line control register (DLAB bit)

R/W 0

W 0

is clear)

7:0

Receive data
read,
DLAB=0

Data read is taken from the receive FIFO (Provided
it is not empty)

(Only If bit 7 of the line control register (DLAB bit)

R 0

is clear)

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AUX_MU_IIR_REG Register (0x7E21 5044)

S

YNOPSIS

The AUX_MU_IER_REG register is primary used to enable interrupts
If the DLAB bit in the line control register is set this register gives access to the MS 8 bits
of the baud rate. (Note: there is easier access to the baud rate register)

Bit(s) Field Name Description Type Reset

31:8

7:0

Reserved, write zero, read as don’t care

MS 8 bits
Baudrate
read/write,

Access to the MS 8 bits of the 16-bit baudrate register.

(Only If bit 7 of the line control register (DLAB bit) is
set)

R/w 0

DLAB=1

7:2

Reserved, write zero, read as don’t care

Some of these bits have functions in a 16550
compatible UART but are ignored here

1

0

Enable receive
interrupt

(DLAB=0)

Enable
transmit
interrupt

If this bit is set the interrupt line is asserted whenever
the receive FIFO holds at least 1 byte.

If this bit is clear no receive interrupts are generated.

If this bit is set the interrupt line is asserted whenever
the transmit FIFO is empty.

If this bit is clear no transmit interrupts are generated.

R 0

R 0

(DLAB=0)

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AUX_MU_IER_REG Register (0x7E21 5048)

S

YNOPSIS

The AUX_MU_IIR_REG register shows the interrupt status.
It also has two FIFO enable status bits and (when writing) FIFO clear bits.

Bit(s) Field Name Description Type Reset

31:8

7:6 FIFO enables

Reserved, write zero, read as don’t care

Both bits always read as 1 as the FIFOs are always

R 11

enabled

5:4 - Always read as zero R 00

3 -

Always read as zero as the mini UART has no

R 0

timeout function

2:1 READ:

Interrupt ID
bits

WRITE:

FIFO clear
bits

On read this register shows the interrupt ID bit

00 : No interrupts

01 : Transmit holding register empty

10 : Receiver holds valid byte

11 : <Not possible>

On write:

R/W 00

Writing with bit 1 set will clear the receive FIFO

Writing with bit 2 set will clear the transmit FIFO

0

Interrupt
pending

This bit is clear whenever an interrupt is pending R 1

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AUX_MU_LCR_REG Register (0x7E21 504C)

S

S

YNOPSIS

The AUX_MU_LCR_REG register controls the line data format and gives access to the
baudrate register

Bit(s) Field Name Description Type Reset

31:8

7 DLAB access

Reserved, write zero, read as don’t care

If set the first to Mini UART register give access the

R/W 0
the Baudrate register. During operation this bit must
be cleared.

6 Break

If set high the UART1_TX line is pulled low

R/W 0
continuously. If held for at least 12 bits times that will
indicate a break condition.

5:1

Reserved, write zero, read as don’t care

Some of these bits have functions in a 16550

0

compatible UART but are ignored here

0 data size If clear the UART works in 7-bit mode

R/W 0

If set the UART works in 8-bit mode

AUX_MU_MCR_REG Register (0x7E21 5050)

YNOPSIS

The AUX_MU_MCR_REG register controls the 'modem' signals.

Bit(s) Field Name Description Type Reset

31:8

7:2

Reserved, write zero, read as don’t care

Reserved, write zero, read as don’t care

Some of these bits have functions in a 16550

0

compatible UART but are ignored here

1 RTS If clear the UART1_RTS line is high

R/W 0

If set the UART1_RTS line is low

This bit is ignored if the RTS is used for auto-flow
control. See the Mini Uart Extra Control register
description)

0

Reserved, write zero, read as don’t care

This bit has a function in a 16550 compatible UART

0

but is ignored here

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AUX_MU_LSR_REG Register (0x7E21 5054)

S

S

YNOPSIS

The AUX_MU_LSR_REG register shows the data status.

Bit(s) Field Name Description Type Reset

31:8

7

Reserved, write zero, read as don’t care

Reserved, write zero, read as don’t care

This bit has a function in a 16550 compatible UART

0

but is ignored here

6

5

4:2

Transmitter
idle

Transmitter
empty

This bit is set if the transmit FIFO is empty and the
transmitter is idle. (Finished shifting out the last bit).

This bit is set if the transmit FIFO can accept at least
one byte.

Reserved, write zero, read as don’t care

Some of these bits have functions in a 16550

R 1

R 0

0

compatible UART but are ignored here

1

Receiver
Overrun

This bit is set if there was a receiver overrun. That is:
one or more characters arrived whilst the receive

R/C 0

FIFO was full. The newly arrived charters have been
discarded. This bit is cleared each time this register is
read. To do a non-destructive read of this overrun bit
use the Mini Uart Extra Status register.

0 Data ready

This bit is set if the receive FIFO holds at least 1

R 0
symbol.

AUX_MU_MSR_REG Register (0x7E21 5058)

YNOPSIS

The AUX_MU_MSR_REG register shows the 'modem' status.

Bit(s) Field Name Description Type Reset

31:8

7:6

Reserved, write zero, read as don’t care

Reserved, write zero, read as don’t care

Some of these bits have functions in a 16550

0

compatible UART but are ignored here

5 CTS status

This bit is the inverse of the UART1_CTS input Thus

R 1
:

If set the UART1_CTS pin is low

If clear the UART1_CTS pin is high

3:0

Reserved, write zero, read as don’t care

Some of these bits have functions in a 16550

0

compatible UART but are ignored here

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S

S

AUX_MU_SCRATCH Register (0x7E21 505C)

YNOPSIS

The AUX_MU_SCRATCH is a single byte storage.

Bit(s) Field Name Description Type Reset

31:8

7:0 Scratch

Reserved, write zero, read as don’t care

One whole byte extra on top of the 134217728

R/W 0
provided by the SDC

AUX_MU_CNTL_REG Register (0x7E21 5060)

YNOPSIS

The AUX_MU_CNTL_REG provides access to some extra useful and nice features not
found on a normal 16550 UART .

Bit(s) Field Name Description Type Reset

31:8

7

Reserved, write zero, read as don’t care

CTS assert
level

This bit allows one to invert the CTS auto flow
operation polarity.

R/W 0

If set the CTS auto flow assert level is low*

If clear the CTS auto flow assert level is high*

6

5:4

3

RTS assert
level

RTS AUTO
flow level

Enable
transmit Auto
flow-control
using CTS

This bit allows one to invert the RTS auto flow
operation polarity.

If set the RTS auto flow assert level is low*

If clear the RTS auto flow assert level is high*

These two bits specify at what receiver FIFO level the
RTS line is de-asserted in auto-flow mode.

00 : De-assert RTS when the receive FIFO has 3
empty spaces left.

01 : De-assert RTS when the receive FIFO has 2
empty spaces left.

10 : De-assert RTS when the receive FIFO has 1
empty space left.

11 : De-assert RTS when the receive FIFO has 4
empty spaces left.

If this bit is set the transmitter will stop if the CTS
line is de-asserted.

If this bit is clear the transmitter will ignore the status
of the CTS line

R/W 0

R/W 0

R/W 0

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2

Enable receive
Auto flow­control using
RTS

If this bit is set the RTS line will de-assert if the
receive FIFO reaches it 'auto flow' level. In fact the
RTS line will behave as an RTR (Ready To Receive)
line.

If this bit is clear the RTS line is controlled by the
AUX_MU_MCR_REG register bit 1.

R/W 0

1

Transmitter
enable

If this bit is set the mini UART transmitter is enabled.

If this bit is clear the mini UART transmitter is

R/W 1

disabled

0

Receiver
enable

If this bit is set the mini UART receiver is enabled.

If this bit is clear the mini UART receiver is disabled

R/W 1

Receiver enable

If this bit is set no new symbols will be accepted by the receiver. Any symbols in progress of
reception will be finished.

Transmitter enable

If this bit is set no new symbols will be send the transmitter. Any symbols in progress of
transmission will be finished.

Auto flow control

Automatic flow control can be enabled independent for the receiver and the transmitter.

CTS auto flow control impacts the transmitter only. The transmitter will not send out new
symbols when the CTS line is de-asserted. Any symbols in progress of transmission when
the CTS line becomes de-asserted will be finished.

RTS auto flow control impacts the receiver only. In fact the name RTS for the control line is
incorrect and should be RTR (Ready to Receive). The receiver will de-asserted the RTS
(RTR) line when its receive FIFO has a number of empty spaces left. Normally 3 empty
spaces should be enough.

If looping back a mini UART using full auto flow control the logic is fast enough to allow
the RTS auto flow level of '10' (De-assert RTS when the receive FIFO has 1 empty space
left).

Auto flow polarity

To offer full flexibility the polarity of the CTS and RTS (RTR) lines can be programmed.
This should allow the mini UART to interface with any existing hardware flow control
available.

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AUX_MU_STAT_REG Register (0x7E21 5064)

S

YNOPSIS

The AUX_MU_STAT_REG provides a lot of useful information about the internal status of
the mini UART not found on a normal 16550 UART.

Bit(s) Field Name Description Type Reset

31:28

27:24

Reserved, write zero, read as don’t care

Transmit
FIFO fill level

These bits shows how many symbols are stored in the
transmit FIFO

R 0

The value is in the range 0-8

23:20

19:16

Reserved, write zero, read as don’t care

Receive FIFO
fill level

These bits shows how many symbols are stored in the
receive FIFO

R 0

The value is in the range 0-8

15:10

9

Reserved, write zero, read as don’t care

Transmitter
done

This bit is set if the transmitter is idle and the transmit
FIFO is empty.

R 1

It is a logic AND of bits 2 and 8

8

Transmit
FIFO is empty

If this bit is set the transmitter FIFO is empty. Thus it
can accept 8 symbols.

R 1

7 CTS line This bit shows the status of the UART1_CTS line. R 0

6 RTS status This bit shows the status of the UART1_RTS line. R 0

5

Transmit

This is the inverse of bit 1 R 0

FIFO is full

4

Receiver
overrun

This bit is set if there was a receiver overrun. That is:
one or more characters arrived whilst the receive

R 0

FIFO was full. The newly arrived characters have
been discarded. This bit is cleared each time the
AUX_MU_LSR_REG register is read.

3

2

Transmitter is
idle

Receiver is
idle

If this bit is set the transmitter is idle.

If this bit is clear the transmitter is idle.

If this bit is set the receiver is idle.

If this bit is clear the receiver is busy.

R 1

R 1

This bit can change unless the receiver is disabled

1

Space
available

If this bit is set the mini UART transmitter FIFO can
accept at least one more symbol.

R 0

If this bit is clear the mini UART transmitter FIFO is
full

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S

0

Symbol
available

If this bit is set the mini UART receive FIFO contains
at least 1 symbol

R 0

If this bit is clear the mini UART receiver FIFO is
empty

Receiver is idle

This bit is only useful if the receiver is disabled. The normal use is to disable the receiver.
Then check (or wait) until the bit is set. Now you can be sure that no new symbols will
arrive. (e.g. now you can change the baudrate...)

Transmitter is idle

This bit tells if the transmitter is idle. Note that the bit will set only for a short time if the
transmit FIFO contains data. Normally you want to use bit 9: Transmitter done.

RTS status

This bit is useful only in receive Auto flow-control mode as it shows the status of the RTS
line.

AUX_MU_BAUD Register (0x7E21 5068)

YNOPSIS

The AUX_MU_BAUD register allows direct access to the 16-bit wide baudrate counter.

Bit(s) Field Name Description Type Reset

31:16

Reserved, write zero, read as don’t care

15:0 Baudrate mini UART baudrate counter R/W 0

This is the same register as is accessed using the LABD bit and the first two register, but
much easier to access.

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2.3 Universal SPI Master (2x)

The two universal SPI masters are secondary low throughput5 SPI interfaces. Like the UART
the devices needs to be enabled before they can be used. Each SPI master has the following
features:

• Single beat bit length between 1 and 32 bits.

• Single beat variable bit length between 1 and 24 bits

• Multi beat infinite bit length.

• 3 independent chip selects per master.

• 4 entries 32-bit wide transmit and receive FIFOs.

• Data out on rising or falling clock edge.

• Data in on rising or falling clock edge.

• Clock inversion (Idle high or idle low).

• Wide clocking range.

• Programmable data out hold time.

• Shift in/out MS or LS bit first

A major issue with an SPI interface is that there is no SPI standard in any form. Because the
SPI interface has been around for a long time some pseudo-standard rules have appeared
mostly when interfacing with memory devices. The universal SPI master has been developed
to work even with the most 'non-standard' SPI devices.

2.3.1 SPI implementation details

The following diagrams shows a typical SPI access cycle. In this case we have 8 SPI clocks.

Clk

Cs_n

1 Bit time

Set-up Operate

Hold

(optional)

Idle

One bit time before any clock edge changes the CS_n will go low. This makes sure that the
MOSI signal has a full bit-time of set-up against any changing clock edges.

The operation normally ends after the last clock cycle. Note that at the end there is one half­bit time where the clock does not change but which still is part of the operation cycle.

There is an option to add a half bit cycle hold time. This makes sure that any MISO data has
at least a full SPI bit time to arrive. (Without this hold time, data clocked out of the SPI
device on the last clock edge would have only half a bit time to arrive).

5

Again the SPIs themselves have no throughput limitations in fact they can run with an SPI clock of 125 MHz.

But doing so requires significant CPU involvement as they have shallow FIFOs and no DMA support.

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Last there is a guarantee of at least a full bit time where the spi chip select is high. A longer
CS_n high period can be programmed for another 1-7 cycles.

The SPI clock frequency is:

__

freqclocksystem

_

=

CLKSPIx

fieldspeed

)1_(*2

+

If the system clock is 250 MHz and the speed field is zero the SPI clock frequency is 125
MHz. The practical SPI clock will be lower as the I/O pads can not transmit or receive
signals at such high speed. The lowest SPI clock frequency with a 250 MHz system clock is

30.5 KHz.

The hardware has an option to add hold time to the MOSI signal against the SPI clk. This is
again done using the system clock. So a 250 MHz system clock will add hold times in units
of 4 ns. Hold times of 0, 1, 4 and 7 system clock cycles can be used. (So at 250MHz an
additional hold time of 0, 4, 16 and 28 ns can be achieved). The hold time is additional to the
normal output timing as specified in the data sheet.

2.3.2 Interrupts

The SPI block has two interrupts: TX FIFO is empty, SPI is Idle.

TX FIFO is empty:
This interrupt will be asserted as soon as the last entry has been read from the transmit FIFO.
At that time the interface will still be busy shifting out that data. This also implies that the
receive FIFO will not yet contain the last received data. It is possible at that time to fill the
TX FIFO again and read the receive FIFO entries which have been received. Note that there
is no "receive FIFO full" interrupt as the number of entries received is always equal to the
number of entries transmitted.

SPI is IDLE:
This interrupt will be asserted when the transmit FIFO is empty and the SPI block has
finished all actions (including the CS-high time) By this time the receive FIFO will have all
received data as well.

2.3.3 Long bit streams

The SPI module works in bursts of maximum 32 bits. Some SPI devices require data which
is longer the 32 bits. To do this the user must make use of the two different data TX
addresses: Tx data written to one address cause the CS to remain asserted. Tx data written to
the other address cause the CS to be de-asserted at the end of the transmit cycle. So in order
to exchange 96 bits you do the following:
Write the first two data words to one address, then write the third word to the other address.

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2.3.4 SPI register details.

S

AUXSPI0/1_CNTL0 Register (0x7E21 5080,0x7E21 50C0)

YNOPSIS

The AUXSPIx_CNTL0 register control many features of the SPI interfaces.

Bit(s) Field Name Description Type Reset

31:20

Speed

Sets the SPI clock speed. spi clk freq =

R/W 0

system_clock_freq/2*(speed+1)

19:17

16

15

chip selects The pattern output on the CS pins when active. R/W 111

post-input
mode

Variable CS

If set the SPI input works in post input mode.

For details see text further down

If 1 the SPI takes the CS pattern and the data from the

R/W 0

R/W 0

TX fifo

If 0 the SPI takes the CS pattern from bits 17-19 of
this register

Set this bit only if also bit 14 (variable width) is set

14

Variable width

If 1 the SPI takes the shift length and the data from

R/W 0

the TX fifo

If 0 the SPI takes the shift length from bits 0-5 of this
register

13:12

DOUT Hold
time

Controls the extra DOUT hold time in system clock
cycles.

R/W 0

00 : No extra hold time

01 : 1 system clock extra hold time

10 : 4 system clocks extra hold time

11 : 7 system clocks extra hold time

11

Enable

Enables the SPI interface. Whilst disabled the FIFOs

R/W 0

can still be written to or read from

This bit should be 1 during normal operation.

10

In rising

If 1 data is clocked in on the rising edge of the SPI

R/W 0

clock

If 0 data is clocked in on the falling edge of the SPI
clock

9

Clear FIFOs

If 1 the receive and transmit FIFOs are held in reset

R/W 0

(and thus flushed.)

This bit should be 0 during normal operation.

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8

Out rising

If 1 data is clocked out on the rising edge of the SPI
clock

If 0 data is clocked out on the falling edge of the SPI
clock

R/W 0

7

6

Invert SPI
CLK

Shift out MS
bit first

If 1 the 'idle' clock line state is high.

If 0 the 'idle' clock line state is low.

If 1 the data is shifted out starting with the MS bit.
(bit 15 or bit 11)

R/W 0

R/W 0

If 0 the data is shifted out starting with the LS bit. (bit

0)

5:0 Shift length Specifies the number of bits to shift

R/W 0

This field is ignored when using 'variable shift' mode

Invert SPI CLK
Changing this bit will immediately change the polarity of the SPI clock output. It is
recommended not to do this when also the CS is active as the connected devices will see this
as a clock change.

DOUT hold time
Because the interface runs of fast silicon the MOSI hold time against the clock will be very
short. This can cause considerable problems on SPI slaves. To make it easier for the slave to
see the data the hold time of the MOSI out against the SPI clock out is programmable.

CLK

CLK

MOSI

No hold time

MOSI

With hold time

Variable width
In this mode the shift length is taken from the transmit FIFO. The transmit data bits 28:24 are
used as shift length and the data bits 23:0 are the actual transmit data. If the option 'shift MS
out first' is selected the first bit shifted out will be bit 23. The receive data will arrive as
normal.

Variable CS
This mode is used together with the variable width mode. In this mode the CS pattern is
taken from the transmit FIFO. The transmit data bits 31:29 are used as CS and the data bits
23:0 are the actual transmit data. This allows the CPU to write to different SPI devices
without having to change the CS bits. However the data length is limited to 24 bits.

Post-input mode
Some rare SPI devices output data on the falling clock edge which then has to be picked up
on the next falling clock edge. There are two problems with this:

1. The very first falling clock edge there is no valid data arriving.

2. After the last clock edge there is one more 'dangling' bit to pick up.

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S

The post-input mode is specifically to deal with this sort of data. If the post-input mode bit is
set, the data arriving at the first falling clock edge is ignored. Then after the last falling clock
edge the CS remain asserted and after a full bit time the last data bit is picked up. The
following figure shows this behaviour:

Clk

Cs_n

Get first bit Get last bit

In this mode the CS will go high 1 full SPI clock cycle after the last clock edge. This
guarantees a full SPI clock cycle time for the data to settle and arrive at the MISO input.

AUXSPI0/1_CNTL1 Register (0x7E21 5084,0x7E21 50C4)

YNOPSIS

The AUXSPIx_CNTL1 registers control more features of the SPI interfaces.

Bit(s) Field Name Description Type Reset

31:18

10:8

7

- Reserved, write zero, read as don’t care

CS high time Additional SPI clock cycles where the CS is high. R/W 0

TX empty IRQ

If 1 the interrupt line is high when the transmit FIFO

R/W 0

is empty

6

5:2

1

Done IRQ If 1 the interrupt line is high when the interface is idle R/W 0

- Reserved, write zero, read as don’t care

Shift in MS bit
first

If 1 the data is shifted in starting with the MS bit. (bit

15)

R/W 0

If 0 the data is shifted in starting with the LS bit. (bit

0)

0 Keep input

If 1 the receiver shift register is NOT cleared. Thus

R/W 0

new data is concatenated to old data.

If 0 the receiver shift register is cleared before each
transaction.

Keep input
Setting the 'Keep input' bit will make that the input shift register is not cleared between
transactions. However the contents of the shift register is still written to the receive FIFO at
the end of each transaction. E.g. if you receive two 8 bit values 0x81 followed by 0x46 the
receive FIFO will contain: 0x0081 in the first entry and 0x8146 in the second entry. This
mode may save CPU time concatenating bits (4 bits followed by 12 bits).

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S

CS high time
The SPI CS will always be high for at least 1 SPI clock cycle. Some SPI devices need more
time to process the data. This field will set a longer CS-high time. So the actual CS high time
is (CS_high_time + 1) (In SPI clock cycles).

Interrupts
The SPI block has two interrupts: TX FIFO is empty, SPI is Idle.

TX FIFO is empty:
This interrupt will be asserted as soon as the last entry has been read from the transmit FIFO.
At that time the interface will still be busy shifting out that data. This also implies that the
receive FIFO will not yet contain the last received data.

It is possible at that time to fill the TX FIFO again and read the receive FIFO entries which
have been received. There is a RX FIFO level field which tells exactly how many words are
in the receive FIFO. In general at that time the receive FIFO should contain the number of
Tx items minus one (the last one still being received). Note that there is no "receive FIFO
full" interrupt or "receive FIFO overflow" flag as the number of entries received can never
be more then the number of entries transmitted.

AUX is IDLE:
This interrupt will be asserted when the module has finished all activities, including waiting
the minimum CS high time. This guarantees that any receive data will be available and
`transparent' changes can be made to the configuration register (e.g. inverting the SPI clock
polarity).

AUXSPI0/1_STAT Register (0x7E21 5088,0x7E21 50C8)

YNOPSIS

The AUXSPIx_STAT registers show the status of the SPI interfaces.

Bit(s) Field Name Description Type Reset

31:24

23:12

11:5

4

TX FIFO level The number of data units in the transmit data FIFO R/W 0

RX FIFO level The number of data units in the receive data FIFO. R/W 0

- Reserved, write zero, read as don’t care

TX Full If 1 the transmit FIFO is full

R/W 0

If 0 the transmit FIFO can accept at least 1 data unit.

3

TX Empty If 1 the transmit FIFO is empty

R/W 0

If 0 the transmit FIFO holds at least 1 data unit.

2

RX Empty If 1 the receiver FIFO is empty

R/W 0

If 0 the receiver FIFO holds at least 1 data unit.

6

Busy Indicates the module is busy transferring data. R/W 0

5:0 Bit count

The number of bits still to be processed. Starts with

R/W 0

'shift-length' and counts down.

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S

S

Busy
This status bit indicates if the module is busy. It will be clear when the TX FIFO is empty
and the module has finished all activities, including waiting the minimum CS high time.

AUXSPI0/1_PEEK Register (0x7E21 508C,0x7E21 50CC)

YNOPSIS

The AUXSPIx_PEEK registers show received data of the SPI interfaces.

Bit(s) Field Name Description Type Reset

31:16

15:0 Data

- Reserved, write zero, read as don’t care

Reads from this address will show the top entry from

RO 0
the receive FIFO, but the data is not taken from the
FIFO. This provides a means of inspecting the data
but not removing it from the FIFO.

AUXSPI0/1_IO Register

(0x7E21 50A0-0x7E21 50AC

0x7E21 50E0-0x7E21 50EC)

YNOPSIS

The AUXSPIx_IO registers are the primary data port of the SPI interfaces
These four addresses all write to the same FIFO.

Writing to any of these addresses causes the SPI CS_n pins to be de-asserted at
the end of the access

Bit(s) Field Name Description Type Reset

31:16

- Reserved, write zero, read as don’t care

15:0 Data

Writes to this address range end up in the transmit
FIFO. Data is lost when writing whilst the transmit
FIFO is full.

Reads from this address will take the top entry from
the receive FIFO. Reading whilst the receive FIFO is
will return the last data received.

R/W 0

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AUXSPI0/1_TXHOLD Register

S

(0x7E21 50B0-0x7E21 50BC

0x7E21 50F0-0x7E21 50FC)

YNOPSIS

The AUXSPIx_TXHOLD registers are the extended CS port of the SPI interfaces
These four addresses all write to the same FIFO.

Writing to these addresses causes the SPI CS_n pins to remain asserted at the
end of the access

Bit(s) Field Name Description Type Reset

31:16

15:0 Data

- Reserved, write zero, read as don’t care

Writes to this address range end up in the transmit

R/W 0
FIFO. Data is lost when writing whilst the transmit
FIFO is full.

Reads from this address will take the top entry from
the receive FIFO. Reading whilst the receive FIFO is
will return the last data received.

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Address

C

S

DLEN

A

FIFO

DIV

DEL

3 BSC

3.1 Introduction

The Broadcom Serial Controller (BSC) controller is a master, fast-mode (400Kb/s) BSC
controller. The Broadcom Serial Control bus is a proprietary bus compliant with the Philips®
I2C bus/interface version 2.1 January 2000.

• I2C single master only operation (supports clock stretching wait states)

• Both 7-bit and 10-bit addressing is supported.

• Timing completely software controllable via registers

3.2 Register View

The BSC controller has eight memory-mapped registers. All accesses are assumed to be 32­bit. Note that the BSC2 master is used dedicated with the HDMI interface and should not be
accessed by user programs.

There are three BSC masters inside BCM. The register addresses starts from

• BSC0: 0x7E20_5000

• BSC1: 0x7E80_4000

• BSC2 : 0x7E80_5000

The table below shows the address of I2C interface where the address is an offset from one of
the three base addreses listed above.

I2C Address Map

Offset

0x0

0x4

0x8

0xc

Register Name Description Size

Control 32

Status 32

Data Length 32

Slave Address 32

0x10

0x14

0x18

Data FIFO 32

Clock Divider 32

Data Delay 32

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0x1c

CLKT

Synopsis

Bit(s)

Field Name

Description

Type

Reset

Reserved

-

Write as 0, read as don't care

Reserved

-

Write as 0, read as don't care

Clock Stretch Timeout 32

C Register

The control register is used to enable interrupts, clear the FIFO, define a read or write
operation and start a transfer.
The READ field specifies the type of transfer.
The CLEAR field is used to clear the FIFO. Writing to this field is a one-shot operation
which will always read back as zero. The CLEAR bit can set at the same time as the
start transfer bit, and will result in the FIFO being cleared just prior to the start of
transfer. Note that clearing the FIFO during a transfer will result in the transfer being
aborted.
The ST field starts a new BSC transfer. This has a one shot action, and so the bit will
always read back as 0 .
The INTD field enables interrupts at the end of a transfer the DONE condition. The
interrupt remains active until the DONE condition is cleared by writing a 1 to the
I2CS.DONE field. Writing a 0 to the INTD field disables interrupts on DONE.
The INTT field enables interrupts whenever the FIFO is or more empty and needs
writing (i.e. during a write transfer) - the TXW condition. The interrupt remains active
until the TXW condition is cleared by writing sufficient data to the FIFO to complete the
transfer. Writing a 0 to the INTT field disables interrupts on TXW.
The INTR field enables interrupts whenever the FIFO is or more full and needs reading
(i.e. during a read transfer) - the RXR condition. The interrupt remains active until the
RXW condition is cleared by reading sufficient data from the RX FIFO. Writing a 0 to
the INTR field disables interrupts on RXR.
The I2CEN field enables BSC operations. If this bit is 0 then transfers will not be
performed. All register accesses are still permitted however.

31:16

15 I2CEN I2C Enable

RW 0x0
0 = BSC controller is disabled
1 = BSC controller is enabled

14:11

10 INTR INTR Interrupt on RX

RW 0x0
0 = Don t generate interrupts on RXR condition.
1 = Generate interrupt while RXR = 1.

9 INTT INTT Interrupt on TX

RW 0x0
0 = Don t generate interrupts on TXW condition.
1 = Generate interrupt while TXW = 1.

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8 INTD INTD Interrupt on DONE

Reserved

-

Write as 0, read as don't care

Reserved

-

Write as 0, read as don't care

0 = Don t generate interrupts on DONE
condition. 1 = Generate interrupt while DONE =

1.

RW 0x0

7 ST ST Start Transfer

0 = No action. 1 = Start a new transfer. One shot
operation. Read back as 0.

6

5:4 CLEAR CLEAR FIFO Clear

00 = No action. x1 = Clear FIFO. One shot
operation. 1x = Clear FIFO. One shot operation.
If CLEAR and ST are both set in the same
operation, the FIFO is cleared before the new
frame is started. Read back as 0.
Note: 2 bits are used to maintain compatibility to
previous version.

3:1

0 READ READ Read Transfer

0 = Write Packet Transfer. 1 = Read Packet
Transfer.

RW 0x0

RW 0x0

RW 0x0

S Register

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