Bright Way BL24C02, BL24C04, BL24C08, BL24C16 Schematics

BRIGHT WAY

BL24C02/04/08/16

BL24C02/BL24C04/BL24C08/BL24C16

2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8)

Two-wire Serial EEPROM

 Features

 Two-wire Serial Interface

 VCC = 1.8V to 5.5V



Bi-directional Data Transfer Protocol



Internally Organized
BL24C02, 256 X 8 (2K bits)

BL24C04, 512 X 8 (4K bits)
BL24C08, 1024 X 8 (8K bits)
BL24C16, 2048 X 8 (16K bits)

 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility

8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes



Self-timed Write Cycle (5 ms max)



1 Million Write Cycles guaranteed



Data Retention > 100 Years



 Operating Temperature: -40℃ to +85℃

 8-lead PDIP, 8-lead SOP and 8-lead TSSOP Packages

 Description

BL24C02/BL24C04/BL24C08/BL24C16 provides 2048/4096/8192/16384 bits of serial electrically
erasable and programmable read-only memor y (EEPROM) organize d as 256/512/102 4/2048 words of 8
bits each. The device is optimized for use in many industrial and commercial applications where
low-power and low-voltage operations are essential. The BL24C02/BL24C04/BL24C08/BL24C16 is
available in space-saving 8-lead PDIP, 8-lead SOP, and 8-lead T SSOP packages and is accessed via a
two-wire serial interface.

 Pin Descriptions

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Block Diagram

BL24C02/04/08/16

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BL24C02/04/08/16

DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that
are hard wired for the BL24C02. Eight 2K devices may be addressed on a sing le bus system (device
addressing is discussed in detail under the Device Addressing section).
The BL24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be
addressed on a single bus system. The A0 pin is a no connect and can be connected to ground.
The BL24C08 only uses the A2 input for hardwire addressing and a total of t wo 8K devices may be
addressed on a single bus system. The A0 and A1 pins are no connects and can be connected to
ground.
The BL24C16 does not use the device address pins, which limits the number of devices on a single bus
to one. The A0, A1 and A2 pins are no connects and can be connected to ground.

SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven
and may be wire-ORed with any number of other open-drain or open- collector devices.

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device
and negative edge clock data out of each device.

WRITE PROTECT (WP): The BL24C02/BL24C04/BL24C08/BL24C16 has a Write Protect pin that
provides hardware data protection. The Write Protect pin allows normal read/write operations when
connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection feature
is enabled and operates as shown in the following Table 2.

WP Pin Status:

Part of the Array Protected

BL24C02 BL 24C04 BL 24C08 BL 24C16

At V

CC

Full (2K)

Array

Full (4K)

Array

Full (8K)

Array

Full (16K) Array

At GND Normal Read/Write Operations

 Memory Organization

BL24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an

8-bit data word address for random word addressing.

BL24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a
9-bit data word address for random word addressing.

BL24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a
10-bit data word address for random word addressing.

BL24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K

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requires an 11-bit data word address for random word addressing.

BL24C02/04/08/16

 Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data

on the SDA pin may change only during SCL low time periods (see to Figure 1 on page 4). Data changes
during SCL high periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must
precede any other command (see to Figure 2 on page 4).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read
sequence, the stop command will place the EEPROM in a standby power mode (see Figure 2 on pag e

4).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in
8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens
during the ninth clock cycle. STANDBY MODE: The K24C02/K24C04/K24C08/K24C16 features a
low-power standby mode which is enabled: (a) upon po wer-up and (b) after the receipt of the ST OP bit
and the completion of any internal operations

MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be
reset by following these steps:

1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition.

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BL24C02/04/08/16

 Device Addressing

The 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start
condition to enable the chip for a read or write operation (see to Figure 4 on page 7).

The device address word consists of a mandatory "1", "0" sequenc e for the first four mos t signific ant bit s
as shown. This is common to all the Serial EEPROM devices.

The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must
compare to their corresponding hardwired input pins.

The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page
address bit. The two device address bits must compare to their correspondin g hard wired input pins. T he

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